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? 2010 microchip technology inc. ds39881d pic24fj64ga004 family data sheet 28/44-pin general purpose, 16-bit flash microcontrollers http://
ds39881d-page 2 ? 2010 microchip technology inc. i n f o r m a t i on c ont a i ne d in t h is p ubli c a t i on reg a r d in g d e v i ce ap pli c a t i ons a nd t he lik e is p r o v id ed on ly f o r yo ur c o n v e n ien c e an d m a y be su pe rs ed ed by up da t e s . i t is y o u r r e s p o n s i bil i t y t o e n s u r e t h a t yo ur ap pl i c a t i o n me e t s wi t h yo ur sp ec if ic at io n s . mi c r o c h i p m akes n o r e pr e sen t a tion s or w a r r a n tie s of an y kin d w h eth e r ex pr e ss or im pl i e d , wr itte n o r o r al , st a t u t or y or ot he r w is e , re la t e d t o t h e i n f o rm a t i o n, in c l u d i ng b u t not l i m i t e d t o it s c o nd i t i o n, qu a l ity , pe r form a nc e, m e r chan t ab il i t y or fitn ess for pu r p o s e . mi c r oc hip dis c l aim s al l lia bility ar is ing f r o m t h is i n f o r m a t i on an d it s us e. u s e o f m i cr oc hip de vic e s in li f e su pp ort a nd/ o r s a f e t y ap plic at io ns is e n t i r e ly at t he bu ye r ? s r i sk , a n d t h e buy er a g r e e s t o def e nd, ind e m n i f y and ho ld h a rm le ss m i cr o c h i p f r om a n y an d al l da ma ge s, c l aim s, su it s, o r e x p ens es re su lt ing f r om s u ch u s e . n o li ce ns es are co nv ey ed , im pli c it ly o r ot he rw is e, u nde r an y m i cr oc hip in t e llec t ua l pr ope rty rig ht s. t r ad emarks t he m i c r ochip name and l ogo , t he micr ochip logo, ds pi c, k ee l oq , k ee l oq l ogo , mpla b, p i c , pi c m i c ro, pi c s t a r t , rf pi c and uni / o a r e re gi s t ered t r ademar ks of mic r ochip t e c hnol o g y i n cor porat ed in t he u. s . a . and ot her count ries. f i lt erlab, ham p shire, hi -t ech c, linear ac t i ve t hermist or , m x d e v , m x lab , se ev al and t he em bedded cont r o l solut i ons c o mp any are regist ered t r ad emark s o f microc hip t e c hnol o g y i n cor porat ed in t he u. s . a . analog-f o r-t he-digit al age, ap pl ica t ion m aest r o, codeg uard, dsp i cde m, ds pi cdem . ne t , dsp i c w orks , dssp ea k, e c an, e c onom oni t or, f a n s e n s e , h i - t ide , in - cir c u it se r i a l pro g ramm ing, i c s p , mindi, miw i , m p as m, m p la b cert if ied logo, mp li b , mp li nk , mt ouch, o c t opus, o m niscient code g enerat i on, pi cc, pi cc-18, p i cde m, p i c d em . net , pi ckit , p i ct ai l, p i c 32 logo, re al i c e , rf la b, s e lect m ode, t o t a l endur ance, t s ha rc, uniw in driver , w i perlock and z e na are t r ade mark s of microc hip t e c hnology i n c o rporat ed in t he u. s . a . and ot her count ries. sq t p is a s e rvice ma rk of micr ochip t e chnology i n corpor at ed in the u.s . a . all ot her t r ademark s ment i o ned here i n are propert y of t h eir respe c t i ve com p ani es. ? 2 010, micr ochip t e chnology i n c o rporat ed, pr i n t ed i n t h e u. s . a . , a ll right s r e s erved. printed on recycled paper. isbn: 978-1-60932-022-5 no te t h e fo l l o w i n g d e t a i l s o f th e co d e p r o t ecti o n featu r e o n m i cro c h i p d evi ces: ? m icr o chip pr oduct s m eet t he s pecif icat ion c ont ained in t heir part i cular m i c r ochip dat a sheet . ? m icr o chip bel iev e s t hat i t s f a mily of produc t s is one of t he mo s t sec u re f a m i l i es of i t s kind on t he m a rket t oday , when used i n t he int ended man ner and under norm a l condit i ons. ? t h e re ar e dishone st and possibly il legal met hods used t o breach t h e code prot ect i on f eat ur e. all of t h ese met hods, t o o u r knowledge, require using t he m i croc hi p pr oduc t s in a m anner out side t h e o perat ing spe c if icat ions cont ained in m i croc hi p ? s dat a sheet s. m o st likely , t he person doing s o is engaged i n t hef t of int e ll ec t ual propert y . ? m icr o chip is will ing t o work wit h t he c u st omer who i s c oncerned about t he int egrit y of t heir c ode. ? n eit her m i croch i p nor any o t her sem i conduc t o r m anuf ac t u re r c an guarant ee t he sec u rit y of t heir code . code prot ect i on does not mean t h at we ar e guaran t eeing t he product a s ? unbreakable. ? code prot ect i on is c onst ant ly ev olving. w e at m i croc hi p ar e co mm it t ed t o c ont inuously im provi ng t he code prot ect i on f eat ures of our product s. a t t e m p t s t o break m i c r ochip? s c ode prot ect i on f eat ure may be a violat ion of t he digit al millennium copyr i ght a c t . i f su ch act s all o w unaut horized acce ss t o your sof t w are or ot her c opyright ed w o rk, you m a y ha ve a right t o s ue f o r r e l i ef unde r t hat ac t . mi cr och i p r e cei v ed i s o/t s - 16 949 :20 02 cer t i f i cati o n f o r i t s w o rl dw i d e he adq ua rter s, d e si g n a nd w a fer fa bri ca t i o n fa ci l i t i es i n ch a ndl e r a nd t e m p e , a r i zo n a ; gr esh a m, or ego n a nd desi g n ce nte r s i n ca l i f o r n i a an d in di a. th e c o mpan y? s qu al i t y s ystem pr oce sses and pr oce dur es ar e fo r i t s p i c ? m c u s an d d sp i c ? dscs, k ee l oq ? co de ho pp i n g d e vi ce s, se r i a l eepro m s , m i cr o p e r ip h e r a ls , n o n vo l a t ile m e m o r y a n d an al og p r od ucts. in a ddi t i on, mi cr och i p? s q u a l i t y sys tem fo r the de si gn an d m anu fac t ur e of de vel o p m e n t s ystem s i s i s o 90 01 :200 0 c e rt i f i ed.
? 2010 microchip technology inc. ds39881d-page 3 pic24fj64ga004 fa mily hi gh-per f or m a nc e cpu: ? m od i f i ed h a r v ar d ar chi t ec t u r e ? u p t o 16 m i ps o p er at i o n @ 3 2 m h z ? 8 mhz in te rn a l os c i l l a t o r wit h 4 x pl l op tio n a n d mu lti p l e d i v i d e op tio n s ? 1 7 - bit b y 1 7 - b i t sin g l e - cy c l e ha rd w a r e m u lt ip lie r ? 3 2 - bit b y 1 6 - b i t ha rd wa r e div i d e r ? 1 6 - bi t x 16- bi t wor k i n g r egi st e r ar r a y ? c co mp i l e r op timi z e d in s t ru c t io n se t ar c h ite c tu re : - 7 6 b a se i n st ru ct i o ns - f l e xi bl e ad dr es s i ng m o d e s ? t wo a d d r e s s ge n e ra ti o n un it s fo r s e p a r a t e r e a d an d w r i t e a ddr es si ng o f d a t a m e m o r y s p eci al m i cro c ontr o ll er feat ures: ? o pe r a t i ng v o l t age r ange of 2. 0v t o 3. 6v ? 5 . 5 v t o l e r ant i n pu t ( d i g i t al p i n s on l y ) ? hig h - cu rr e n t sin k / s o u r c e ( 1 8 m a/ 1 8 ma) o n all i/o pin s ? f la sh p r o g ra m me mo r y : - 10, 00 0 er a s e/ w r i t e - 20- ye ar da t a r et ent i on m i ni m u m ? p ow er m a nag em en t m o des : - s l e e p , i d l e , d o z e an d al t e r n at e c l o ck m ode s - o p e ra t i ng curre nt 65 0 ? a/ m i ps t y p i c a l at 2 . 0v - s l e e p cu r r e n t 15 0 na t y pi ca l a t 2 . 0 v ? f ai l - s af e c l oc k m oni t or o per at i on: - d et ect s cl oc k fa i l ur e and sw i t ch es t o on- chi p , l o w- p o we r rc o s c ill a t o r ? o n- c hi p , 2. 5v r e gu l a t o r w i t h t r ac ki ng m o de ? p o w e r - o n re se t (p or), p o we r-u p t i me r (p wr t ) a n d os c i lla to r s t a r t- u p t i me r ( o s t ) ? f l e xi bl e w a t chd o g t i m e r ( w d t ) w i t h o n - c hi p , l o w- p o we r rc os c i lla to r fo r re lia b l e op e r a t io n ? i n - c i rc u i t s e ria l p r o g ra mmin g ? (i cs p ? ) a n d i n - c i r cu i t d e b ug ( i c d ) vi a 2 pi n s ? jt a g b oun dar y sc an su pp or t anal og fe atur es: ? 1 0 - bi t , u p t o 1 3 - c han nel a n a l og- t o - d i g i t al c onve r t e r : - 5 0 0 ks p s c onv er si on r a t e - c on ver s i on av ai l a bl e dur i n g sl eep an d i d l e ? d ua l an al og c o m p a r a t o r s w i t h pr og r a m m abl e i npu t / o u t p ut c onf i gur at i on per i pher a l feat ures: ? p e r ip h e ra l p i n s e le c t : - a l l ow s i nde pendent i / o m appi ng of m any per i pher al s - u p t o 26 a v ai l a bl e pi ns ( 4 4- pi n d ev i c e s) - c ont i nuous har dw ar e i n t egr i t y checki ng and sa f e t y i n t e r l ocks prevent uni nt ent i onal conf i gurat i on ch anges ? 8 - b it pa r a l l e l m a s t er /sla ve po r t ( p m p / p sp) : - u p t o 1 6 - b i t m u l t i p l e xed ad dr e ssi ng , w i t h u p t o 1 1 de di cat ed ad dr ess p i ns o n 44- pi n dev i ces - p r ogr am m ab l e po l a r i t y on co nt r ol l i ne s ? h ar dw a r e r eal - t i m e c l oc k/ c al e nda r ( r t c c ) : - p r o vi de s cl ock , cal e n dar and al ar m f u n c t i o n s ? p ro g r a mma b l e cy cl i c re d u n d a n c y ch e ck (crc) ? t w o 3 - w i r e / 4 - w i r e spi m o d u l e s ( sup po r t 4 fr am e m o de s) w i t h 8- le ve l fi fo bu f f e r ?t w o i 2 c ? m o d u l es s u pp or t m u l t i - m a st er / s l a ve mo d e a n d 7 - bi t/1 0 - bit ad d r e ssi n g ? t wo u a r t mo d u le s: - s up por t s r s - 4 85, r s - 2 32, a nd li n 1. 2 - o n- chi p ha r d w a r e e n co der / d eco der fo r ir d a ? - a ut o- w ak e- u p on s t a r t b i t - a ut o- bau d d e t e ct - 4 - l e v el dee p fi f o b u f f er ? f i v e 1 6- b i t t i m e r s / c ou nt e r s w i t h pr ogr am m abl e p r e sca l er ? f i ve 1 6- b i t c a pt ur e i n pu t s ? f iv e 1 6 -bit co mp a r e / pw m ou tp u t s ? c o n f i g u ra b l e op e n - dra i n ou tp u t s o n dig it a l i/o pin s ? u p t o 4 ex t e r n al i n t e r r upt sou r c e s p i c 24f j d evi ce pi n s p r ogr a m me mo r y ( b yt es ) s ram (b ytes) r e map p ab l e peri p h e ral s i 2 c? 1 0 - b it a /d (c h ) co mp ar ato r s pmp/p s p jt ag rema p p ab l e pin s t i mers 16- bi t c a pt ure in put co mp are/ pwm out put uart w/ ir d a ? sp i 1 6 g a 0 0 2 28 16k 4k 16 5 5 5 2 2 2 10 2 y y 3 2 g a 0 0 2 28 32k 8k 16 5 5 5 2 2 2 10 2 y y 4 8 g a 0 0 2 28 48k 8k 16 5 5 5 2 2 2 10 2 y y 6 4 g a 0 0 2 28 64k 8k 16 5 5 5 2 2 2 10 2 y y 1 6 g a 0 0 4 44 16k 4k 26 5 5 5 2 2 2 13 2 y y 3 2 g a 0 0 4 44 32k 8k 26 5 5 5 2 2 2 13 2 y y 4 8 g a 0 0 4 44 48k 8k 26 5 5 5 2 2 2 13 2 y y 6 4 g a 0 0 4 44 64k 8k 26 5 5 5 2 2 2 13 2 y y 28/44-pin general pu rpose, 16-bit flas h mi cr oc ont r olle rs
pic24fj64ga004 family ds39881d-page 4 ? 2010 microchip technology inc. pi n di agrams pic24fjxxga002 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 -p in spd ip , sso p , so ic 28 -p in q f n (1 ) 10 1 1 2 3 6 1 18 19 20 21 22 12 13 1 4 15 8 7 16 17 23 24 25 26 27 28 9 pic 24fjxxg a 0 0 2 5 4 mclr v ss v dd an0 / v re f +/cn 2 / ra0 an1 / v re f - / cn 3 / ra1 p g d1 / e m u d 1 /an2 /c2 i n- / rp0 /cn 4 /rb 0 sosco / t 1 ck/cn0 /pm a 1 / ra4 so sci / rp4 / p m be/cn 1 / rb4 o s co / c l k o / cn2 9 / pm a0 / r a3 osci /cl k i / cn3 0 / ra2 an5 / c1 i n +/ rp 3 /scl 2 / cn 7 / rb3 an 4 / c 1 i n - / rp2 / s da2 / cn 6 / rb2 pgc1 /em uc1 / a n 3 /c2 i n+/ rp1 /cn 5 /rb 1 pg d3 / e m ud3 / rp5 / asda1 / c n27 / pm d 7 / r b5 v dd v ss pgc3 /em u c3 / rp6 / ascl 1 / cn2 4 / pm d6 / r b6 di svreg v ca p /v dd co re rp7 /i nt 0 / cn2 3 / p m d5 /rb7 td o / rp9 /sda1 / cn2 1 / pm d 3 /rb9 tc k /r p 8 /scl 1 / cn2 2 / pm d4 /rb8 an9 / rp 1 5 / cn1 1 / pm cs1 / rb1 5 an1 0 / c v re f /r t cc/ rp1 4 / cn1 2 / pm wr/ r b1 4 an1 1 / rp1 3 /cn1 3 / pm rd/rb1 3 an1 2 / rp1 2 /cn1 4 / pm d0 /rb1 2 pgd2 /em u d2 /t di/ rp1 0 /cn1 6 / pm d2 / r b1 0 pgc2 /em u c2 /t m s / rp1 1 /cn1 5 / pm d1 / r b1 1 v ss p g d1 /e mud 1 /a n2 /c2 i n-/ rp0 /c n4/rb 0 os c o /c l k o/ c n 2 9/ p m a 0 / r a 3 osci /cl k i / cn3 0 / ra2 an5 / c1 i n +/ rp 3 /s c l 2/c n 7/r b 3 an 4 / c 1 i n - / rp2 / s d a 2/c n 6/r b 2 pgc1 /em uc1 / a n3 /c2 i n+/ rp1 /c n5/rb 1 di svreg v ca p /v ddc o r e td o / rp9 /sda1 / cn2 1 / pm d3 /r b9 an1 1 / rp1 3 /cn1 3 / pm rd/r b 1 3 an1 2 / rp1 2 /cn 14/ p m d0 /rb 1 2 pgd2 /em ud2 / t di / rp1 0 /cn1 6 / pm d2 /rb1 0 pgc2 /em uc2 / t m s / rp1 1 /cn1 5 / pm d1 /rb1 1 v dd p g c3 /em uc3 / rp6 /a s c l1/c n 24/ p m d 6 / r b 6 sosco/ t 1 ck / cn0 /pm a 1 / ra4 so sci / rp4 /pm b e/cn 1 / rb4 rp7 /int 0 /cn2 3/p m d5/rb 7 tc k / rp8 /s c l1/ c n 22/ p m d 4 / r b 8 p g d3 /em ud3 / rp5 / asda 1 / cn2 7 / pm d 7 / r b5 mc l r an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 v dd v ss an9/ rp15 /cn11/pmcs1/rb15 an10/cv ref /rtcc/ rp14 /cn12/pmwr/rb14 le ge nd : r pn repr esent s r e mapp ab l e peripheral pi n s . no te 1: b a ck p ad on q f n devices should be c o nnect ed t o v ss.
? 2010 microchip technology inc. ds39881d-page 5 pic24fj64 ga004 family pin diagrams (continued) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 p i c 24fjx xga 004 37 4 4 -pin q f n (1 ) rp8 /scl1/cn22/pmd4/rb8 rp7 /int0/cn23/pmd5/rb7 pgc3/emuc3/ rp6 /ascl1 / cn24/pmd6/rb6 pgd3/emud3/ rp5 /asda1 / cn27/pmd7/rb5 v dd tdi/pma9/ra9 sosco/t1ck/cn0/ra4 v ss rp21 /cn26/pma3/rc5 rp20 /cn25/pma4/rc4 rp19 /cn28/pmbe/rc3 an 1 2 / rp1 2 /cn1 4 / pm d0 /rb1 2 pgc2 /em uc2 / rp1 1 / cn1 5 / p m d1 / rb 1 1 p g d2 /em ud2 / rp1 0 /cn1 6 / pm d2 /rb1 0 v ca p /v dd co re di svreg rp2 5 / c n 1 9 / pm a6 / r c 9 rp2 4 / c n 2 0 / pm a5 / r c 8 rp2 3 / c n 17/ p m a 0 /r c 7 rp2 2 / c n 18/ p m a 1 /r c 6 rp9 /sda1 / cn2 1 / pm d3 /rb9 an1 1 / rp1 3 / cn1 3 / p m rd/rb1 3 an4 / c1 i n - / rp2 /sda2 / cn6 /r b 2 an5 / c1 i n +/ rp3 /scl 2 / cn7 / r b3 an6 / rp1 6 / cn8 /rc0 an7 / rp1 7 / cn9 /rc1 an8 / rp1 8 / cn1 0 / pm a2 / r c2 so sci / rp4 /cn1 /rb4 v dd v ss o s c i/clk i/ cn30/ ra 2 o s c o/cl k o / cn2 9 / ra3 t d o/p m a 8/ra 8 pgc1 / e m uc1 / a n3 /c2 i n+/ rp1 /cn 5 /rb 1 pg d1 /em ud1 /an2 / c 2 i n- / rp0 /cn 4 /rb 0 an1 / v re f - / cn 3 / ra1 an0 / v re f +/cn 2 / ra0 mc l r tms/pma10/ra10 av dd av ss an9/ rp15 /cn11/pmcs1/rb15 an10/cv ref /rtcc/ rp14 /cn12/pmwr/rb14 tck/pma7/ra7 le g e nd: r p n repres ent s rem app able peripheral pins. no te 1: bac k p ad on q f n dev i c es should be connec t ed t o vs s.
pic24fj64ga004 family ds39881d-page 6 ? 2010 microchip technology inc. pi n di agrams (cont inued) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 44 -pin tqf p pic24 f jxxga00 4 an12/ rp12/ cn14/pmd0/rb12 p g c2 /em uc2 / rp1 1 / cn1 5 / pm d 1 / r b1 1 pgd2 /em ud2 / rp1 0 /cn1 6 / pm d2 /rb1 0 v ca p /v d dco re di s v reg rp2 5 /cn1 9 / pm a6 / rc9 rp2 4 /cn2 0 / pm a5 / rc8 rp2 3 /cn1 7 / pm a 0 /rc7 rp2 2 /cn1 8 / pm a 1 /rc6 rp9 /sda1 / cn2 1 / pm d3 /rb9 an1 1 / rp1 3 / cn1 3 / pm r d / r b1 3 an4 / c1 i n - / rp2 /sda2 / cn6 /rb2 an5 / c1 i n +/ rp 3 /scl 2 / cn7 / rb 3 an6 / rp1 6 /c n8 /rc0 an7 / rp1 7 /c n9 /rc1 an8 / rp1 8 /c n1 0 / p m a2 /rc2 so sci / rp4 /cn1 /rb4 v dd v ss os ci /clk i/cn 30/r a 2 osco /cl k o/ cn2 9 / ra3 t d o/p m a 8/ra 8 rp8 /s c l1/ c n 22/ p m d 4 / r b 8 rp7 /int 0 /cn2 3/p m d5/rb 7 pg c3 /em u c3 / rp6 / a scl 1 / cn2 4 / pm d6 / r b6 pg d3 /em u d3 / rp5 / a sda1 / cn2 7 / pm d7 / r b5 v dd t d i/p m a 9/ra 9 so s c o / t 1 ck/cn0 / r a4 v ss rp2 1 /cn2 6 / pm a 3 /rc5 rp2 0 /cn2 5 / pm a 4 /rc4 rp1 9 /cn2 8 / pm b e /r c3 pg c1 / em uc1 / an3 / c2 i n +/ rp1 /cn5 /rb1 pgd1 / e m ud1 / a n2 /c2 i n- / rp0 /cn4 /rb0 an1 / v re f - / cn3 /ra1 an0 / v re f +/cn2 /ra0 mc l r tms/pma10/ra10 av dd av ss an9/ rp15 /cn11/pmcs1/rb15 an10/cv ref /rtcc/ rp14 /cn12/pmwr/rb14 tck/pma7/ra7 le ge n d : r pn repres ent s r e mapp able peripheral pi ns .
? 2010 microchip technology inc. ds39881d-page 7 pic24fj64 ga004 family t a bl e of c o n t ent s 1 . 0 d e v ic e ov e r v i e w . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. 9 2.0 guidelines for getting s t a r t e d wit h 1 6 - b i t m i c r o c o n t r o lle r s .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 1 9 3 . 0 c p u . .. .. .. .. .. .. . . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 2 5 4. 0 m em ory o r ganizat i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 3 1 5 . 0 f la s h pr o g r a m m e m o r y . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 4 9 6 . 0 r e se ts .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 5 5 7 . 0 i n t e r r u p t c o n t r o lle r . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 6 1 8. 0 o scillat o r confi g urat ion . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 9 5 9 . 0 p o w e r - s a v i n g fe a t u r e s . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 0 3 1 0 . 0 i /o po r t s . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 0 5 1 1 . 0 t im e r 1 . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 2 5 12. 0 t im er2/ 3 and t i m e r4/ 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 2 7 13. 0 i nput c apt ure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 3 1 4 . 0 ou t p u t co m p a r e .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 3 5 15. 0 s erial peripheral i n t e rf ace (sp i ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 4 1 16. 0 i nt er-i nt egr at ed circuit (i 2 c? ) . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. . . .. .. .. .. .. .. .. .. .. . 1 5 1 17. 0 u nivers al as ynchr onous receiver t r ansm i t t er ( u art ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 1 5 9 1 8 . 0 p a r a l le l m a st e r p o r t ( p m p ) . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 6 7 19. 0 r eal-t i m e cl o ck and calendar (rt cc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 7 7 20. 0 p rog r amm able cy clic re dundancy chec k ( crc) g e n e rat o r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. . .. .. .. .. .. .. .. .. .. . 1 8 7 21. 0 10-b i t high- speed a/ d con vert e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 9 1 22. 0 c ompa rat o r m odule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 0 1 23. 0 c ompa rat o r v o l t age ref e re nce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 0 5 2 4 . 0 s p e c i a l fe a t u r e s . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 0 7 25. 0 d evelopm ent suppor t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 1 7 2 6 . 0 i n s t r u c t i o n s e t su m m a r y . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 2 1 2 7 . 0 e le ct r i ca l ch a r a cte r i st ic s . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 2 9 2 8 . 0 p a c ka g i n g in fo r m a tio n . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 4 7 appendix a : revision hi s t or y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 5 9 appendix b : addit i onal g u i dan ce f o r pi c24f j 64g a004 f a mily applicat i o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. ... .. .. .. .. .. .. .. .. .. 2 6 0 i ndex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. . 2 6 1 t h e m i c r o ch i p we b si te .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 6 5 cust omer change not i f i cat i on se rvice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 6 5 cust omer s upport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .... .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 6 5 reader respons e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .... .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 6 6 p r o d u ct i d e n t i f i c a t i o n s ys t e m . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 6 7
pic24fj64ga004 family ds39881d-page 8 ? 2010 microchip technology inc. t o our v a lue d cus t o me rs i t i s our int ent ion t o pr ovide our valued cust omer s wi t h t he be s t docum ent at ion possible t o ensu r e s u cce ssf ul us e of your m i c r o chi p product s . t o t h is end, we wi ll cont i n ue t o i m prov e our pu bl ica t ions t o bet t e r s u it your needs . o u r publicat ions w i ll be r e f i ned and enhanced as new volumes and updat es ar e int r oduced. i f y ou have any quest i on s o r c o mm ent s r egardi ng t h is publicat ion, p l eas e c ont ac t t h e m a rket ing co mm uni c a t i ons dep a r t m ent via e - m a il at d o cerro rs@mi c ro ch i p . c o m or f a x t he read er resp o n se f o rm in t he back of t h is dat a sheet t o (480) 79 2-4150. w e welcom e yo ur f eedback . mo st cu r r en t da t a s h ee t t o obt ain t he mos t up-t o -dat e ver s ion of t h is dat a s heet , please regist er at our w o rldwide w eb sit e at : ht tp: / / w ww .mic ro c hip. c om y ou can det erm i ne t he v e rsion of a dat a s heet by examining i t s li t e rat u re nu mber f ound on t he bot t o m out s i de cor ner of an y p a g e . t h e last c haract e r of t he li t e rat u re number is t he vers i o n num ber , (e. g . , ds30000a is ver sion a of doc ument d s 30000). er rat a an errat a she e t , desc r ibing minor operat ional dif f erences f r om t he dat a sheet and recom m ended workar ounds, m a y ex i s t f o r curre n t devices . a s device/ docum ent at ion issu es bec ome k nown t o us , w e will publi s h an er rat a sheet . t he errat a will spec i f y t he revisi on of silicon a nd rev i sion of doc ument t o whi c h it applies. t o det er mine if an errat a sheet exis t s f o r a p a rt i c ular dev i ce, please chec k w i t h one of t he f o ll o w i ng: ? m icr o chip? s w o rldwide w eb sit e ; ht t p : / / w w w . m icroc h ip. com ? y our local m i croc hi p sales of f i ce (see last p age) w hen cont act i ng a s a l e s of f i c e , please s pecif y which device, re vision of sili c on and dat a s heet (inc l ude lit erat ur e number) y o u are using. cu st o m er no t i f i c a t i o n sy st em regist er on our web sit e at w w w .m ic r o c h ip .c o m t o rec e i v e t he m o st c u rrent inf o rmat i on on all of our produc t s .
? 2010 microchip technology inc. ds39881d-page 9 pic24fj64 ga004 family 1 . 0 d ev ic e o ver vi ew th is d o cu me nt co nt a i ns d e v i ce -sp e c i fi c info rm atio n for th e fo ll ow in g de vi ce s: ? p i c 24 f j 1 6g a 00 2 ? p i c 24 f j 3 2g a 00 2 ? p i c 24 f j 4 8g a 00 2 ? p i c 24 f j 6 4g a 00 2 ? p i c 24 f j 1 6g a 00 4 ? p i c 24 f j 3 2g a 00 4 ? p i c 24 f j 4 8g a 00 4 ? p i c 24 f j 6 4g a 00 4 this family in trod uc es a ne w li ne of mi cro c h i p de vi ces : a 16 -bi t m i c r oc on trol ler fam i l y w i th a br oad p e rip hera l fe atu r e se t a n d e nha nc ed co mp ut a t io nal p e rfo r ma nc e. th e pic 2 4 f j6 4g a00 4 f a m ily o f f e rs a ne w m i gr atio n o p tio n for th os e hig h -pe r form an ce a ppl ic ati ons w h ic h m a y be ou tgro w i ng thei r 8-bi t pl at fo rms , bu t don ?t re qui re th e nu me rica l p r oc essi n g po w e r of a dig i t a l s i g nal pro c es s o r . 1. 1 c ore feat ures 1.1 . 1 16- b i t ar chit e c t u r e c e ntral to al l pic 24f de vi ce s is the 16 -bi t m od i fie d h a rvar d arc h i t ec ture , firs t i n trod uc ed w i th m i c r oc hi p? s ds p i c ? di git a l s i gn al c ont roll ers . the pi c 2 4f c p u co re o f fe rs a wi d e ra nge of enh ancem en t s , su ch as : ? 1 6-bi t da t a and 24 -bit add res s p a th s w i th t he a bil ity to mo ve inf orm ati on b etw e en dat a an d me mo r y s p a c e s ? l ine a r a ddre s s i n g of up to 12 m b y t es (p rogra m s p a c e) and 64 kby t es (da t a) ? a 1 6 -e lem e n t work in g re gis t er array wit h b u il t-in so ftw ar e stac k su p p o r t ? a 1 7 x 17 ha rdware m u lti p l i er w i th sup p o r t for in t e ge r ma th ? h ar dw are su ppo rt fo r 32 by 16 -bit di vis i o n ? a n in stru cti on se t tha t s upp ort s m u l t ipl e a ddre s s i n g m ode s a n d is op tim i z ed for h i gh -le v el l ang uag es su ch as ?c ? ? o pe rati ona l p e rfo r ma nce up to 16 mips 1 . 1. 2 p owe r - s a v i n g t e c hnol ogy al l of th e dev ic es in th e pic 2 4 f j6 4g a00 4 fam i l y inco rpo r ate a ra nge o f f e at ures that c an s i gn ifi c a n tl y re duc e pow e r c o n s um pt ion d u rin g ope r ati o n. ke y i t em s i n c lud e: ? o n -the - fly cloc k sw itch ing: the dev ic e c l o c k c an be c h a nge d u nde r s o f t w a re c ont rol to th e t i mer 1 s ourc e o r th e i n tern al, lo w - pow e r r c os c ill ato r du ring op erat ion , al low i ng the us er to i n co rpo r ate p o w e r-s av in g id eas in to the i r s o f t w a re de si gns . ? doz e m ode o p era t ion: whe n ti mi ng-s en s i t iv e ap pl ica t io ns , s uch as s eria l c om m u ni c at ion s , re qui re t he uni nte rrup t ed op erat ion of pe riph era l s, th e c p u c l o c k sp eed c an be s el ec t iv ely reduc ed, al lo w i ng in crem en t a l po w e r s a v i ng s w i tho u t m i s s i ng a be at. ? in structi on-bas e d pow e r-sav i ng m o d es: the m i c r oc ont roll er c an su sp end al l opera t ion s , or s e le cti v e l y sh ut dow n it s c o re w h il e le av ing it s pe rip hera l s ac tiv e , w i th a s i ng le ins t ru cti on in so ft war e . 1.1 . 3 o sci lla t o r op t i o n s and fea t ure s al l o f the de vi ce s i n t he p i c 24f j64 g a004 fam i l y of f e r fi ve d i f f ere n t os ci lla tor op tio n s , all o w i n g us ers a rang e of c ho i c es in d ev elo pi ng ap pli c a t io n hard w are. th es e i n cl ud e: ? t w o cr ys t a l m ode s usi n g cr y s t a ls o r ce r a m i c re s o n a to rs . ? t w o ex te rnal c l oc k mo des of f e rin g the o p ti on of a di vi de- by- 2 c loc k out put. ? a f a st int e rna l o s cil l a t or (f rc ) with a n o m i na l 8 m h z ou tpu t, w h i c h ca n a l s o be di vi ded un der s of t w a re c ont rol t o pro v i de c l o c k sp ee ds a s l ow as 3 1 kh z. ? a ph as e l o ck l oop (pll ) freq ue ncy m u lt ipl i er , av ai lab l e to th e ext e rna l os ci ll ator m ode s an d the fr c os ci ll ator , w h ic h al low s clo c k sp eed s of u p to 32 m h z. ? a s e p a rat e i n tern al rc os ci lla tor ( l prc) with a fi xe d 31 k h z o utpu t, w h ic h pr ovi de s a lo w - p ow er op tio n fo r ti mi ng-i n s ens iti v e ap pli c a t io ns. th e in tern al o s c i l l at or bl oc k al so prov id es a st abl e re fere nce s ourc e for the fai l -sa f e c l oc k mo nito r . thi s op tio n c o n s t a ntl y m o n i to rs t he m a i n c l o c k so urc e ag ai nst a r e fere nc e si gna l pro v i ded b y th e int e rna l os c ill ato r an d ena ble s the c on t roll er to sw i t ch to th e i ntern al os ci lla tor , al lo w i ng for co nti nue d l o w - s pee d op era t io n or a s a fe ap pli c a t ion s hut d o w n .
pic24fj64ga004 family ds39881d-page 10 ? 2010 microchip technology inc. 1 . 1. 4 e as y mi g r a t i o n r e gard l es s o f t he m e m o ry s i z e , a ll de vi ce s sh are th e s a m e ric h s e t of p e rip h e r als , al low i ng fo r a sm oo th m i g r ati on p a th as ap pli c a t io ns grow and ev olve . th e co nsi s t ent pi nou t s c hem e us ed thro ug hou t th e e n tir e fa mi ly al so ai ds in mi grat ing to the ne xt larg er d evi ce . this is tru e w h en m ov i ng b etw ee n dev ic es w i th th e sam e pi n c oun t, or e v e n ju mp ing from 28 -pin to 44 - p in de vi c e s . th e pic 2 4 f fa mi ly i s pin - co mp ati b le w i t h d e v i c e s in th e d s pic 3 3 fam i l y , and s h a r es s o m e c o mp ati b i lity w i th th e p i no ut s c hem a f o r pic 1 8 a nd dsp i c 30. thi s e x t end s th e ab il ity of ap pli c a t io ns to gro w from the rela tiv e l y s i m p le , to th e po w e rfu l an d co mp lex , y e t s t ill se lec t in g a mi cro c h ip dev ic e. 1. 2 o th er s p eci al feat ures ? com m un ica t ions : the pic 2 4fj 64g a0 04 f a m ily i n c o rpo r ate s a ran ge of s e ri al c o m m uni ca tion p e rip hera l s to han dle a rang e o f ap pli c a t io n re qui rem ent s. the r e ar e tw o ind e p end ent i 2 c m o d u le s t hat su ppo rt bo th m a s t er and sla v e m o d e s of o pera t io n. d e vi ce s a l s o ha ve , th roug h th e pe riph era l pin s e l e c t fea t ure, t w o ind epe nd ent u a r t s wi th bui lt-i n i r d a enc od er/d ec ode rs a nd t w o s p i mo du l e s . ? pe r i phera l pin sele ct: t he peri phe ral pin se le ct fe atu r e a llo w s m o s t d i gi t a l pe riph eral s to b e m a p ped ov er a fix e d se t of di git a l i / o pin s . u s er s m ay i nde pe nde ntly ma p the in pu t a nd/ or out put of an y on e of t h e ma ny d i g i ta l pe r i ph er a l s t o a n y on e o f the i/o p i ns . ? pa r a lle l m aste r /enha nce d para llel slav e port: o n e of the gen eral pu rpo s e i/o po rt s can be re co nfig ure d fo r en ha nce d p a ra lle l d a t a co mm un i- c a ti ons . in th is mo de, the por t can b e c onf igu r ed fo r bo th m a s t er and s l av e o pera t io ns , an d s upp ort s 8 - bit and 16 -bit da t a tr ans fers wi t h up to 1 6 ex te rnal ad dres s lin es in ma ste r m ode s. ? re a l -t im e cloc k / ca l e nda r: t h is mo du le i m p l em en t s a ful l -fe a tu red cl oc k an d c a l end ar w i th a l arm fu nc tio n s in hard w are, free ing up tim e r re so urc e s and pro g ram m e m o ry sp ac e fo r us e of th e c o re ap pli c a t ion . ? 1 0 -bit a/d c o nv e r te r: th is mo dul e i nc orpo r ate s p r ogra m m a b l e ac qui si tion ti me, al low i ng f o r a c han ne l to be se lec t ed an d a co nv ers i on to be i n it iate d w i thou t w a i t in g fo r a sa mpl i n g pe rio d , a s w e ll a s fas t er s am pl i ng sp ee ds. 1. 3 d et ai ls on indi vi dual famil y members d e v i c e s i n the pi c 2 4fj 6 4 g a0 04 fa mi ly are av ail a bl e i n 28 -pi n an d 4 4 -p in p a c k a ges . t he g e n e ral bl oc k di ag ram for all de vic e s is s how n in fig u re 1-1 . th e dev ic es a r e dif f ere n ti ate d from e a c h o t he r i n tw o wa ys: 1. fl ash pr og ra m me mor y ( 6 4 kb yt es f o r p i c24 f j6 4ga de vice s, 4 8 k b yt es f o r p i c24 f j4 8ga de vice s, 3 2 k b yt es f o r p i c24 f j3 2ga de vice s an d 1 6 k b yt es f o r p i c 2 4 f j1 6ga dev ice s ). 2. in tern al sr a m m e m o ry (4k fo r pic24 f j 16ga de vi ce s, 8k for a l l oth e r d e vi ce s i n t he f a m ily ) . 3. a v ai la ble i / o p i ns and port s (21 p i n s on 2 port s f o r 28 - p in de vi ce s and 35 p i ns o n 3 p o r t s fo r 44 - p i n d e vi ce s) . al l ot her fea t ure s fo r de vi ce s i n th is fa mi ly are ide nti ca l. th es e a r e s u m m a r iz ed i n t a b l e 1 -1. a l i s t of the pi n fe atu r es av ail abl e o n th e pic 2 4fj 6 4 g a0 04 fa mi ly dev ice s , s o rte d by func ti on, i s s how n i n t a ble 1 -2 . n o te tha t thi s t a b l e s how s t he pi n l oca tio n of i ndi vi dua l pe riph eral fea t ures an d not h ow th ey are m u l t ip lex e d o n th e s a m e pi n. th is info rma t io n i s pro v i ded in th e pi no ut di agr ams in the b egi nn ing of th e d a t a sh eet . m u lti p l e xe d f eatu r es are s o rted by th e pr iori ty giv e n to a fea t ure , w i t h th e hi gh est pri o rit y pe rip hera l b e in g l i s t ed firs t.
? 2010 microchip technology inc. ds39881d-page 11 pic24fj64 ga004 family t able 1 - 1 : dev i ce fea t ures for the pic 24fj6 4ga00 4 fami ly fea t ures 16ga002 32ga002 48ga002 64ga002 16ga004 32ga004 48ga004 64ga004 o p e r ati ng freq uen cy d c ? 3 2 m h z pro g ram m e m o ry (by t es ) 16k 3 2 k 4 8 k 64 k 16k 3 2 k 4 8 k 64 k pro g ram m e m o ry (in s tr uct i on s) 5,5 0 4 1 1 , 00 8 1 6 , 51 2 22, 016 5,5 0 4 1 1 , 00 8 1 6 , 51 2 2 2, 016 d a t a m e m o ry (by t es ) 4 096 819 2 4 096 81 92 in terru pt s ourc e s ( s of t ve cto r s/ nm i t r ap s ) 43 (39 / 4) i/ o p o rt s port s a, b p ort s a, b, c t o tal i / o p i n s 21 35 ti m e r s : t o t a l n u m ber ( 16-b i t) 5 (1 ) 32 -bi t (f rom p a i r ed 1 6 -b it ti m e rs ) 2 in put capt ure c han nel s 5 (1 ) o u tp ut c o mp are / pwm c h a nne ls 5 (1 ) in put chan ge no ti fic a ti on i n te rrupt 2 1 3 0 se rial co m m u n i c at ion s : uar t 2 (1 ) spi (3-wi r e/4 - wire ) 2 (1 ) i 2 c? 2 pa rall el comm u n ic ati ons (pmp /psp) y e s j t ag boun dary sc an y e s 1 0 -bit ana l og -to-d i git a l m o d u le (i npu t c han nel s) 10 13 an alo g co mp arato r s 2 r em a ppab l e p i ns 16 26 r e set s (a nd del ay s) po r , bo r , reset i n st r u ct i o n , mcl r , wdt , ill ega l o p c o d e , repeat i n st ruc t ion , h a r d w a re t r ap s, c o nfi gura t io n w o rd mi sm at ch (pwr t , o s t , pl l l o c k ) in str u ct ion set 7 6 bas e ins t ruc t io ns , m u lti p l e ad dres si ng mo de v a r i ati o n s pa c k age s 28-pi n spdip /sso p / so i c /q f n 44-pi n qfn/t q f p note 1 : pe riph era l s are accessible through remappable pins.
pic24fj64ga004 family ds39881d-page 12 ? 2010 microchip technology inc. f i g ure 1- 1: pi c24f j6 4g a00 4 fam i ly ge nera l blo c k diagram instruction decode & control 16 p ch p c l 16 p r o g ra m c o un ter 16-bit alu 23 24 data bus inst register 16 divide support in st l a tch 16 ea m u x read agu write agu 16 16 8 interrupt controller psv & t a b l e dat a a cces s co n t r o l blo c k st a c k c ont rol lo gi c r ep eat co n t r o l l ogi c da t a la tch da t a ram ad d r e s s lat ch address latch p r o g ra m mem o r y data latch 16 addre ss bus literal data 23 c o ntr o l s i gn al s 16 16 16 x 16 w re g ar r a y multiplier 17 x17 o s ci/clk i os co/cl k o v dd , ti m i n g g ene rat i on v ss mc l r po w e r - u p ti m e r oscilla to r s t a r t- up t i m e r po w e r - o n re set w at c hdo g ti m e r bo r a n d pr e c isio n re fe r e n ce ba n d g a p f rc/l p r c os cill a t o r s re g u la t o r vo l t a g e v ddcore /v cap di svreg port a (1 ) po rtc (1 ) ra0:ra9 rc0 :rc9 port b rb0 : rb1 5 no t e 1 : n o t al l p i ns o r fe atu r e s ar e i m pl em en ted on al l de vi ce pi no ut c onf i g ur ati o n s. s e e t a bl e 1 -2 for i/o po rt p i n d e scr i p ti o n s. 2: b o r a n d l v d fun cti on al i t y i s pr ovi d e d wh en the on -bo a r d vo l t ag e r egu l a to r i s ena bl ed . 3: p e r i phe ral i /os are acc e ssi bl e th rou gh rem a p p a b l e pi ns. rp (1) rp0 : rp2 5 c o mp a r at or s (3 ) time r 2 / 3 (3 ) t i me r1 rtcc ic1- 5 (3 ) adc 10- b i t pwm/ spi 1 / 2 (3) i2c1/2 time r 4 / 5 (3 ) p m p/ psp oc1-5 (3 ) cn1 - 2 2 (1 ) uar t 1/2 (3) lvd (2 )
? 2010 microchip technology inc. ds39881d-page 13 pic24fj64 ga004 family t abl e 1 - 2 : pi c24f j6 4g a00 4 f a m i ly p i nout de scr i ptions function pi n n u m b e r i/ o input bu ff er des c rip t io n 28- p i n sp d i p / ssop/ soic 28 -p i n qf n 44 -p i n qfn / tqfp an0 2 27 19 i a na a / d ana l og i n p u t s. an1 3 28 20 i a na an 2 4 1 2 1 i an a an 3 5 2 2 2 i an a an 4 6 3 2 3 i an a an 5 7 4 2 4 i an a an 6 ? ? 2 5 i an a an 7 ? ? 2 6 i an a an 8 ? ? 2 7 i an a an 9 2 6 2 3 1 5 i an a an10 25 22 14 i a na an1 1 24 21 1 1 i a na an12 23 20 10 i a na as c l 1 1 5 1 2 4 2 i / o i 2 c a lt ernat e i 2 c1 sy nchronous s e rial clock i nput / o u t p ut . (1) as d a1 1 4 1 1 4 1 i / o i 2 c a lt ernat e i 2 c2 sy nchronous s e rial clock i nput / o u t p ut . (1 ) av dd ? ? 17 p ? p o sit i v e s upply f o r analog modules. av ss ? ? 16 p ? g r oun d ref e rence f o r a n alog m odules. c1i n - 6 3 2 3 i ana c o m p a rat o r 1 nega t i ve i nput . c 1 in + 7 4 2 4 i an a c o m p a r a t o r 1 p o si ti v e i n p u t. c2i n - 4 1 2 1 i ana c o m p a rat o r 2 nega t i ve i nput . c 2 in + 5 2 2 2 i an a c o m p a r a t o r 2 p o si ti v e i n p u t. clki 9 6 30 i a na m a in cloc k i nput connec t i on. clko 10 7 3 1 o ? s yst em clock o u t put . le ge n d : t t l = t t l input buf f e r s t = sc hmit t t r igger i n p u t buf f e r ana = analog l e vel input / out put i 2 c? = i 2 c/ s m b u s i n put buf f e r no te 1: alt e rnat iv e m u l t iplexing wh en t he i 2 c1se l c onf igurat ion bit is cleared.
pic24fj64ga004 family ds39881d-page 14 ? 2010 microchip technology inc. cn0 12 9 3 4 i st i n t e rrupt -on-change i npu t s. cn1 1 1 8 3 3 i s t cn2 2 2 7 1 9 i s t cn3 3 2 8 2 0 i s t cn4 4 1 21 i s t cn5 5 2 22 i s t cn6 6 3 23 i s t cn7 7 4 24 i s t cn8 ? ? 25 i s t cn9 ? ? 26 i s t cn10 ? ? 2 7 i s t cn1 1 2 6 2 3 1 5 i s t cn12 2 5 2 2 1 4 i s t cn13 2 4 2 1 1 1 i s t cn14 2 3 2 0 1 0 i s t cn15 2 2 1 9 9 i s t cn16 2 1 1 8 8 i s t cn17 ? ? 3 i s t cn18 ? ? 2 i s t cn19 ? ? 5 i s t cn20 ? ? 4 i s t cn21 1 8 1 5 1 i s t cn22 1 7 1 4 4 4 i s t cn23 1 6 1 3 4 3 i s t cn24 1 5 1 2 4 2 i s t cn25 ? ? 3 7 i s t cn26 ? ? 3 8 i s t cn27 1 4 1 1 4 1 i s t cn28 ? ? 3 6 i s t cn29 1 0 7 31 i s t cn30 9 6 3 0 i s t cv re f 25 22 14 o a na co mp arat or v o l t age ref e r ence o u t put . di s v re g 19 16 6 i s t v olt age regulat or disable. em uc1 5 2 21 i / o s t i n-circ u i t e m ulat or cl oc k i nput / o ut put . em ud1 4 1 22 i / o s t i n-circ u i t e m ulat or dat a i npu t / o u t put . em uc2 22 19 9 i / o st i n -circ u i t e m ulat or cl oc k i nput / o ut put . em ud2 21 18 8 i / o st i n -circ u i t e m ulat or dat a i npu t / o u t put . em uc3 15 12 42 i / o s t i n-circ u i t e m ulat or cl oc k i nput / o ut put . em ud3 14 1 1 41 i / o s t i n-circ u i t e m ulat or dat a i npu t / o u t put . i n t 0 16 13 43 i s t e xt ernal i n t e r r upt i n put . mclr 1 2 6 1 8 i st m aster clear (device rese t) input. this line is brought low to cause a reset. t a bl e 1 - 2 : pi c24f j6 4g a00 4 f a m i l y p i nout de scr i ptions (continue d) func t i on pi n nu m b e r i/ o input bu ff er des c rip t io n 28- p i n sp d i p / ssop/ soic 28 -p i n qf n 44 -p i n qfn / tqfp le ge n d : t t l = t t l input buf f e r s t = sc hmit t t r igger i n p u t buf f e r ana = analog l e vel input / out put i 2 c? = i 2 c / sm bu s in pu t b u f fe r no te 1: alt e rnat iv e m u l t iplexing wh en t he i 2 c1se l c onf igurat ion bit is cleared.
? 2010 microchip technology inc. ds39881d-page 15 pic24fj64 ga004 family o s ci 9 6 30 i a na m ain o s c i l l at or i nput connec t i on. o s co 10 7 3 1 o ana m ain o sc i l l at or o u t put connec t i on. pg c1 5 2 22 i / o s t i n-circ u i t d ebugger and i c sp ? pr ogramm i ng cloc k pg d1 4 1 21 i / o s t i n-circ u i t d ebugger and i c sp p r ogram ming dat a . pg c2 22 19 9 i / o st i n -circ u i t d ebugger and i c sp p r ogram ming clock. pg d2 21 18 8 i / o st i n -circ u i t d ebugger and i c sp p r ogram ming dat a . pg c3 14 12 42 i / o s t i n-circ u i t d ebugger and i c sp p r ogram ming clock. pg d3 15 1 1 41 i / o s t i n-circ u i t d ebugger and i c sp p r ogram ming dat a . pm a0 10 7 3 i / o s t / t t l p arallel m a st er p o rt addr ess bit 0 i nput ( b uf f e red slave m odes) and o u t put (m ast e r modes ). pm a1 12 9 2 i / o s t / t t l p arallel m a st er p o rt addr ess bit 1 i nput ( b uf f e red slave m odes) and o u t put (m ast e r modes ). pm a2 ? ? 27 o ? p a rallel m a st er p o rt addr ess (dem ult i plexed mas t er m odes) . pm a3 ? ? 38 o ? pm a4 ? ? 37 o ? pm a5 ? ? 4 o ? pm a6 ? ? 5 o ? pm a7 ? ? 13 o ? pm a8 ? ? 32 o ? pm a9 ? ? 35 o ? pm a10 ? ? 1 2 o ? pm a1 1 ? ? ? o ? pm a12 ? ? ? o ? pm a13 ? ? ? o ? pm be 1 1 8 3 6 o ? p arallel m a st er p o rt by t e enable s t robe. pm cs1 2 6 2 3 1 5 o ? p arallel m a st er p o rt chip s e lect 1 s t r obe/ a ddress b i t 14. pm d0 23 20 10 i / o s t / t t l p arallel m a st er p o rt dat a (dem ult i plexed mas t er m o de) or a d dress / dat a (mult i p l e x ed m a st er m odes) . pm d1 22 19 9 i / o st / t t l pm d2 21 18 8 i / o st / t t l pm d3 18 15 1 i / o st / t t l pm d4 17 14 44 i / o s t / t t l pm d5 16 13 43 i / o s t / t t l pm d6 15 12 42 i / o s t / t t l pm d7 14 1 1 41 i / o s t / t t l pm rd 24 21 1 1 o ? p a rallel m a st er p o rt read s t r obe. pm w r 25 22 14 o ? p a rallel m a st er p o rt w r it e s t r obe. t abl e 1 - 2 : pi c24f j6 4g a00 4 f a m i l y p i nout de scr i ptions (continue d) func t i on pi n nu m b e r i/ o input bu ff er des c rip t io n 28- p i n sp d i p / ssop/ soic 28 -p i n qf n 44 -p i n qfn / tqfp le ge n d : t t l = t t l input buf f e r s t = sc hmit t t r igger i n p u t buf f e r ana = analog l e vel input / out put i 2 c? = i 2 c/ s m b u s i n put buf f e r no te 1: alt e rnat iv e m u l t iplexing wh en t he i 2 c1se l c onf igurat ion bit is cleared.
pic24fj64ga004 family ds39881d-page 16 ? 2010 microchip technology inc. ra 0 2 27 19 i / o s t p or t a digit al i/ o. ra1 3 28 20 i / o s t ra 2 9 6 3 0 i /o s t ra 3 1 0 7 31 i / o s t ra 4 1 2 9 34 i / o s t ra 7 ? ? 1 3 i /o s t ra 8 ? ? 3 2 i /o s t ra 9 ? ? 3 5 i /o s t ra10 ? ? 12 i / o s t rb 0 4 1 2 1 i /o s t p o r t b digit al i / o. rb 1 5 2 2 2 i /o s t rb 2 6 3 2 3 i /o s t rb 3 7 4 2 4 i /o s t rb 4 1 1 8 33 i / o s t rb 5 1 4 1 1 4 1 i /o s t rb 6 1 5 1 2 4 2 i /o s t rb 7 1 6 1 3 4 3 i /o s t rb 8 1 7 1 4 4 4 i /o s t rb 9 1 8 1 5 1 i / o s t rb10 21 18 8 i / o st rb1 1 22 19 9 i / o st rb12 23 20 10 i / o s t rb13 24 21 1 1 i / o s t rb14 25 22 14 i / o s t rb15 26 23 15 i / o s t rc0 ? ? 25 i / o s t p or t c digit al i / o . rc1 ? ? 26 i / o s t rc2 ? ? 27 i / o s t rc3 ? ? 36 i / o s t rc4 ? ? 37 i / o s t rc5 ? ? 38 i / o s t rc6 ? ? 2 i /o s t rc7 ? ? 3 i /o s t rc8 ? ? 4 i /o s t rc9 ? ? 5 i /o s t t a bl e 1 - 2 : pi c24f j6 4g a00 4 f a m i l y p i nout de scr i ptions (continue d) func t i on pi n nu m b e r i/ o input bu ff er des c rip t io n 28- p i n sp d i p / ssop/ soic 28 -p i n qf n 44 -p i n qfn / tqfp le ge n d : t t l = t t l input buf f e r s t = sc hmit t t r igger i n p u t buf f e r ana = analog l e vel input / out put i 2 c? = i 2 c / sm bu s in pu t b u f fe r no te 1: alt e rnat iv e m u l t iplexing wh en t he i 2 c1se l c onf igurat ion bit is cleared.
? 2010 microchip technology inc. ds39881d-page 17 pic24fj64 ga004 family rp0 4 1 2 1 i / o st re mapp able peripher al . rp 1 5 2 2 2 i /o s t rp 2 6 3 2 3 i /o s t rp 3 7 4 2 4 i /o s t rp 4 1 1 8 33 i / o s t rp 5 1 4 1 1 4 1 i /o s t rp 6 1 5 1 2 4 2 i /o s t rp 7 1 6 1 3 4 3 i /o s t rp 8 1 7 1 4 4 4 i /o s t rp 9 1 8 1 5 1 i / o s t rp10 21 18 8 i / o st rp1 1 22 19 9 i / o st rp12 23 20 10 i / o s t rp13 24 21 1 1 i / o s t rp14 25 22 14 i / o s t rp15 26 23 15 i / o s t rp16 ? ? 25 i / o s t rp17 ? ? 26 i / o s t rp18 ? ? 27 i / o s t rp19 ? ? 36 i / o s t rp20 ? ? 37 i / o s t rp21 ? ? 38 i / o s t rp 22 ? ? 2 i /o s t rp 23 ? ? 3 i /o s t rp 24 ? ? 4 i /o s t rp 25 ? ? 5 i /o s t r t c c 25 22 14 o ? re al - t ime clock alarm o u t put . scl1 17 14 44 i / o i 2 c i 2c1 sync hronous se ri a l clock i n put / o u t put . scl2 7 4 24 i / o i 2 c i 2c2 sync hronous se ri a l clock i n put / o u t put . sda 1 18 15 1 i / o i 2 c i 2c1 dat a i n put / o u t put . sd a 2 6 3 23 i/ o i 2 c i 2c2 dat a i n put / o u t put . so s c i 1 1 8 33 i a na s e condar y o s cil l at or/ t imer1 clock i nput . so s c o 1 2 9 34 o a na s e condar y o s cil l at or/ t imer1 clock o u t p u t . t abl e 1 - 2 : pi c24f j6 4g a00 4 f a m i l y p i nout de scr i ptions (continue d) func t i on pi n nu m b e r i/ o input bu ff er des c rip t io n 28- p i n sp d i p / ssop/ soic 28 -p i n qf n 44 -p i n qfn / tqfp le ge n d : t t l = t t l input buf f e r s t = sc hmit t t r igger i n p u t buf f e r ana = analog l e vel input / out put i 2 c? = i 2 c/ s m b u s i n put buf f e r no te 1: alt e rnat iv e m u l t iplexing wh en t he i 2 c1se l c onf igurat ion bit is cleared.
pic24fj64ga004 family ds39881d-page 18 ? 2010 microchip technology inc. t 1 ck 12 9 3 4 i s t t i m e r1 clock . t c k 1 7 1 4 1 3 i st j t a g t e st clock i nput . t d i 2 1 1 8 3 5 i st j t a g t e st dat a i nput . t d o 1 8 1 5 3 2 o ? j t a g t e st da t a ou tp u t . t m s 2 2 1 9 1 2 i st j t a g t e st m ode s e l e ct i npu t . v dd 13, 28 10, 25 28, 40 p ? p o sit i v e s upply f o r periphera l digit al logi c and i / o p i ns . v dd ca p 20 17 7 p ? e xt ernal f ilt er cap a c i t o r connect i on (r egul a t or enabled). v dd co re 20 17 7 p ? p osit iv e s upply f o r micro cont r o l l er core logic (regulat or dis abl ed ). v re f - 3 28 20 i a na a / d and comp ar at or ref e rence v o l t age ( l ow) i nput . v re f + 2 27 19 i a na a / d and comp ar at or ref e rence v o l t age ( h igh) i nput . v ss 8, 27 5, 24 29, 39 p ? g r oun d ref e rence f o r logic and i / o p i ns . t a bl e 1 - 2 : pi c24f j6 4g a00 4 f a m i l y p i nout de scr i ptions (continue d) func t i on pi n nu m b e r i/ o input bu ff er des c rip t io n 28- p i n sp d i p / ssop/ soic 28 -p i n qf n 44 -p i n qfn / tqfp le ge n d : t t l = t t l input buf f e r s t = sc hmit t t r igger i n p u t buf f e r ana = analog l e vel input / out put i 2 c? = i 2 c / sm bu s in pu t b u f fe r no te 1: alt e rnat iv e m u l t iplexing wh en t he i 2 c1se l c onf igurat ion bit is cleared.
? 2010 microchip technology inc. ds39881d-page 19 pic24fj64 ga004 family 2.0 g ui d e line s f o r ge tting s t arted w i th 16 -bit microcontrolle rs 2. 1 b asi c conn ecti on req u ir em ent s g e tt ing s t arte d w i th t he p i c 24f j64 g a004 fam i l y of 1 6 -bi t mic r oc on trol lers requ ire s atte nti on to a m i ni ma l s et of de vi ce p i n c onn ect i on s be fore p r oc eed ing w i th d e ve lo pm ent. th e f oll ow in g p i ns m us t al w ays b e c onn ec ted: ?a l l v dd an d v ss pi ns (s ee sect ion 2 .2 ?p ow er su pply pins ? ) ?a l l a v dd an d a v ss pin s , r ega rdl e ss of whet her or n o t th e a nal og dev ic e f eatu r es are us ed (s ee sect ion 2 .2 ?p ow er su pply pins ? ) ?m clr pi n (s ee sect ion 2 .3 ? m aste r c l ea r (mc l r ) pin? ) ? e nvreg/disvreg a n d v ca p /v ddco re pi ns ( p ic 2 4 fj de vi ce s o n ly ) (s ee sect ion 2 .4 ? v olt a ge re gula t or pins (envreg/disvreg a nd v cap /v dd co re )? ) t h e s e p i ns mu s t al s o be c o n n e c t ed i f t h ey a r e be i n g u s ed in the en d a ppl ic ati on: ? p g e cx /pg e d x p i ns us ed for in-circ u i t se rial pro g ram m i ng ? (ic sp?) and de bug gin g p u rpo s e s (s ee sect ion 2 .5 ? i csp pi ns? ) ? o sc i and osc o pi ns w h e n an ex ter nal os ci lla tor s our ce is us ed (s ee sect ion 2 .6 ? e xte r nal o s cill ator pi ns? ) ad dit i on all y , th e fo ll ow in g pi ns ma y be r equ ired : ?v re f +/v re f - pi ns us ed w h en ex terna l v o l t ag e re fere nce fo r an alo g m odu le s i s i m p l em en ted th e mi nim um man d a t ory c onn ec tio ns are s ho w n i n fi gu re 2- 1. figure 2-1: re comme nde d min i mum conne ctions note: the av dd and a v ss p i ns mus t alw a ys b e c onn ec ted, re ga rdle ss o f w h eth e r any of th e a nal og mo dul es are bei ng us ed. pic24fxxxx v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss c1 r1 v dd mclr v ca p /v d dco r e r2 (en/dis)vreg (1) c7 c2 (2 ) c3 (2) c4 (2) c5 (2 ) c6 (2) key ( a l l val u es are reco mmen d at i o n s ): c1 t h rough c6: 0. 1 ? f , 20v cer a mic c7: 10 ? f , 6. 3v or great er , t ant alum or cer a mic r1: 10 k ? r2: 100 ? to 4 7 0 ? no te 1: see s e c t i o n 2 .4 ?v ol t a g e r e gu la t o r pi ns (e n v re g / dis v re g an d v ca p /v dd co re )? f o r explanat ion of e n vr eg / d i s v r eg pin connec t i ons. 2: t h e exa m ple s hown i s f o r a pi c24f de vice wit h f i ve v dd /v ss and a v dd /a v ss p a i r s. o t her device s m a y have more or less p a irs; adjust t he num ber of decoupling c a p a cit o rs appropriat e ly . (1)
pic24fj64ga004 family ds39881d-page 20 ? 2010 microchip technology inc. 2. 2 p ower suppl y pi ns 2.2 . 1 d ec ou pli n g capaci t o r s th e us e o f d e co up lin g c a p a c i to rs on ev ery p a i r of po w e r su p p l y pi n s , s u c h as v dd , v ss , a v dd an d av ss is re qui red. c o nsi de r the fo llo w i ng c r ite r ia w hen us in g d ec oup lin g ca p a c i t o r s: ? v a lue and type of c a p a cito r : a 0.1 ? f (1 00 nf), 10-20 v ca p a c i to r is rec o m m e nde d. th e c a p a c i t or s hou ld be a l o w - esr de vi ce w i th a re so nan ce fre qu enc y in t he rang e o f 200 m h z a nd hig her . c e ram i c ca p a c i to rs are r e co mm en ded . ? pla c e m en t on th e pri n ted circu i t boa rd: th e d eco up lin g c ap aci tors s hou ld be pla c e d as c l os e to the pi ns as po ss ibl e . it is re com m end ed to p l ac e t he c a p a c i to rs o n th e s a m e s i d e o f the b oard as th e de vi ce . if s p a c e is c onstric ted , th e c a p a ci tor can be pl ac ed o n a not her lay e r o n th e pc b u s i ng a v i a; how e v e r , e n su re t hat the trac e le n gt h fr o m t h e p i n t o t h e c apac i t o r is no gr e a t e r th an 0.2 5 in ch (6 m m ) . ? ha ndlin g hig h -frequ e nc y no ise : if th e b oar d is e x pe rie n c i ng hi gh-fr equ enc y noi se (u p w a r d o f te ns of mh z) , ad d a se co nd cer a mi c typ e c a p a ci - to r in p a r all el to t he abo ve des cr ibe d d eco up lin g ca p a c i t o r . t h e va l u e of t h e se c o n d c apa ci t o r ca n b e in th e ra nge of 0 . 01 ? f to 0.0 0 1 ? f . pl ac e th is s e c ond cap a c i to r nex t to ea ch p r im ary dec ou pli ng c a p a ci tor . in hig h -s pee d c i rc ui t de si gns, c onsid er i m p l em en tin g a dec ad e p a ir o f c a p a ci t a n c e s a s c l o s e to th e p o w e r and gro und pi ns as pos s i bl e (e .g., 0.1 ? f i n par a l l e l w i t h 0 . 00 1 ? f) . ? m a x i miz i ng perform a nc e: o n the boa rd l a y out fro m the pow e r su pp ly ci rcu i t, ru n t he p o w e r and re turn trac es to the dec ou pli n g ca p a c i t o rs firs t, a nd th en to the d e v i c e pi ns . thi s en su res t hat t he de c o u p l i n g capac it o r s a r e f i r s t i n t h e p o w e r ch a i n . eq ual ly im po rt an t is to ke ep t he trac e l eng th b e tw ee n th e c a p a c i tor and th e po w e r p i ns to a m i n i m u m, the r eb y re ducin g pc b t r ace indu ct a n c e . 2 . 2. 2 t an k c a p a c i to r s o n bo ards w i th po w e r trac es r unn ing l ong er tha n si x in ch e s in le ng t h , i t i s s u gg e s t ed to us e a tan k ca pac it o r fo r int egra t ed c i rc ui t s in cl udi ng m i c r oc on trol lers to s upp ly a l oc al p ow er sou r ce . th e v alu e of the t an k c a p a ci tor s hou ld b e det erm i ne d ba sed on th e trac e re si st a n c e tha t co nn ect s th e po w e r s upp ly s o u r ce to th e dev ic e, and th e m a x i m u m c u rre nt draw n by th e d e vi ce i n the ap pli c a t io n. in oth e r w o rds , s e l e c t th e t a n k c a p a ci tor s o tha t it m eet s the ac cep t ab le v o l t age sag at th e d e v i ce . t y pi ca l v a l ues ran g e from 4. 7 ? f t o 47 ? f. 2. 3 m ast er c l ear ( m clr ) pin the mclr p i n pr o v i d es t w o sp ec if i c d e vi ce fu nc tion s: dev ic e r e se t, a nd d ev i c e p r ogra m m i n g an d d ebu gg ing . if prog ram m i n g and de bug gin g a r e no t re qui red in the end appl ic atio n, a d i rec t c onn ec tio n to v dd m a y b e all that i s req u ir ed. th e ad di tion of oth e r c o m pon en t s , to h e lp in cre a s e th e ap pl ic atio n? s res i s t a n ce t o sp urio us r e set s from v olt age s ags , m ay be be nef ici al . a t y pi ca l c onf igu r ati on is s how n in fi gu re 2 - 1. oth e r ci rcu i t de si gns m a y b e im pl em ent ed, d epe nd ing on th e ap pl ic atio n? s requ irem en t s . d u ri ng pro g ram m i ng an d d ebu gg ing , th e re si st a n c e an d cap ac i t a nc e t hat ca n b e add ed to the pi n m us t be con s i dere d . d e v i c e pro g ram m e rs a nd de bug ger s dr ive th e mc lr pi n. c o ns equ en tly , sp ec ifi c v ol t ag e le v e l s ( v ih and v il ) an d fas t si gna l tra nsi tio ns m u s t no t be ad ve rsel y af fec t ed . the r efor e, sp eci f ic val u e s of r 1 an d c 1 w i l l n eed to be adj us ted bas ed on th e ap pl ic ation and p c b re qui rement s. fo r e x am pl e, it i s re comm end ed th at the c a p a c i t or , c 1 , be i s ol ate d f r om t h e mc lr pi n duri ng pro g ram m i ng an d de bu ggi ng ope rati ons b y us ing a jum p e r (fi g ur e 2 -2 ). th e ju mp er i s re pla c e d fo r norm a l run- tim e op era t io ns. an y co mp one nt s a s s o c i at ed w i th th e mclr pi n s hou ld be pla c ed w i t h in 0.2 5 i n c h (6 mm) of the pin. figure 2-2: example of mclr pin connections no te 1: r1 ? 10 k ? is r e comm ended. a sugges t e d s t art i ng v a lue is 10 k ? . ensure that the mclr pin v ih and v il specif icat ions are met . 2: r2 ? 470 ? will l im i t any c u rr ent flowing int o mc l r f r om t h e ext e rnal capacit or , c, i n t h e ev ent of mclr p i n break down, due t o e l ect r ost a t i c dis charge ( esd ) or e l ec t r ica l o v e r st ress (e o s ). ensure that the mclr pin v ih and v il specifications are met. c1 r2 r1 v dd mclr pi c 2 4 f xx xx jp
? 2010 microchip technology inc. ds39881d-page 21 pic24fj64 ga004 family 2. 4 v ol t a ge regu lat o r pins ( e nv reg/ disvreg and v cap /v ddcore ) th e on -ch i p vo lt a ge re gul ato r e nab le/ dis ab le pi n (env r e g or d i svr eg , d epe ndi ng o n the dev ic e fa mi ly ) mu st alw a ys be co nne ct ed d i re ctl y to ei the r a s upp ly vo lt ag e or t o gro und . the p a rti c u l ar c o n nectio n i s dete r mi ne d b y w het her or not the re gul ato r is t o b e us e d: ? f o r envreg , t i e t o v dd to ena ble the reg u la tor , o r to grou nd to d i s abl e th e re gul ato r ? f o r di svr eg , tie to g r oun d t o en abl e t he re gul ato r or t o v dd to dis a b l e t he regu lat o r re fer to sec t ion 2 4.2 ?o n-c h i p v o lt ag e r e g u lato r ? fo r de t a i l s on c o n necti ng a nd us ing the on- chi p re gul ato r . when the regul ator is e nabled, a low - esr (<5 ? ) c a p a citor is required on the v ca p /v dd co r e pin to s t a b ilize the vol t age r e g u lator o u tput v o lt age. the v ca p /v dd co r e pin mus t not be c onnec t e d to v dd , and m u st use a cap a c i tor of 10 ? f c onnected to ground. the typ e c an be ceramic o r t ant alu m . a su it able exam ple is the mu r at a g r m 21bf50j10 6ze 0 1 (10 ? f , 6.3v) or equ ivalent. d esig ners may use figure 2-3 to ev aluate esr e quivalen c e of cand idate devic es. th e p l ac em en t of thi s c a p a c i to r sh oul d b e c l o s e to v ca p /v ddc o r e . it i s re co mm en ded tha t the trac e l eng th n o t e x c e e d 0. 25 inc h (6 m m ). r e fer to se ction 2 7 . 0 ? e lec t r i ca l c har a c ter i stics ? for a ddi tio nal in form ati on. w hen th e regu lat o r i s di sa ble d , the v ca p /v ddc o r e pi n m us t be ti ed t o a vo lt a ge s up ply at th e v d dco re le ve l. re fer to se ctio n 2 7 . 0 ?elect r i cal c ha r acte r istic s ? for infor m a t ion on v dd and v d dco re . figure 2-3: freque ncy vs . es r pe rf o r man c e f o r su gg e s t e d v cap 2. 5 i csp pin s t h e p g e c x an d p g e d x p i n s a r e us ed f o r i n - c ir c u i t se rial progra m m i n g (ic sp) an d de bug gin g pu rpos es . it is rec o m m e nde d to ke ep th e t r ac e len g th b e tw ee n th e ic sp co nne cto r an d th e ic sp pin s o n t he d e v i c e a s s hort as pos si ble . if t he ic sp c o n n ec tor is e x p e c t ed to ex pe rie n ce an esd ev ent, a s e ri es re si sto r i s rec o m - m end ed , w i t h t he va lue i n the ran ge of a few ten s of oh ms , n o t t o e x c eed 10 0 ? . pu ll-u p res i s t ors , se rie s di ode s and c a p a c i t ors on th e pg ec x and pg ed x p i ns are no t rec o m m end ed as the y w i l l in terf ere w i th th e pro g ram m e r/d ebu gge r co mm un i- c a ti ons to the de vi ce . if su ch di sc rete co mp on ent s a r e an a ppl ic ati on requ ire m e n t, the y sho u l d b e re mo ve d fro m th e ci rcu i t dur ing p r ogr amm i n g an d deb ugg i n g . al tern ativ el y , re fer to the ac/dc c har act e ris t i c s an d ti mi ng re qui rem en t s i nfo rma t io n in the re sp ec tiv e de vi ce fla s h pro gram m i ng sp ec ifi c at ion for info rma t io n on c a p a ci tiv e loa d i ng lim it s and pi n inp u t vo lt ag e hig h (v ih ) an d i npu t lo w (v il ) r equ irem en t s . f o r de vi ce emu l a t io n, en su r e t h a t th e ?c o mmu ni ca ti on c h an ne l s e l e c t? (i. e ., pg ec x /pg ed x pi ns ) p r og ra mm e d in t o th e d e vi ce m a t c h e s t h e ph ysi ca l con n e ct i o n s fo r t h e ic s p to t he m i c r oc h i p de bu gg er/ e m u l a t o r too l . fo r m o re i n for m at ion o n ava i l abl e m i c r oc hi p de ve lop m e n t too l s c onn ec tio n re qu irem en t s , ref e r to se ction 25. 0 ? d eve lopm ent suppo rt ? . note : th is s e c t io n a ppl ies o n l y to pic 24fj devices with an on-chip voltage regulator. 10 1 0.1 0.01 0.001 0.01 0.1 1 10 100 1000 1 0 ,00 0 fr eq u en cy (mh z) esr ( ? ) no t e : d at a f o r m ur at a gr m 21 b f5 0 j 10 6z e 0 1 s h ow n . m e a sur eme n ts at 25 c , 0 v d c bi a s.
pic24fj64ga004 family ds39881d-page 22 ? 2010 microchip technology inc. 2. 6 e xt ernal osci l l at or pins m a n y m i cr oco n tro l l e rs h a v e op tion s fo r at le as t tw o o s c ill ato r s: a hi gh-f r equ enc y prim ary os c ill ato r and a l o w - fre que nc y s e c ond ary os ci lla tor (r efer to se ction 8 .0 ?o s c illa tor con f igurat ion? for det ail s ). th e osci l l a t or c i rc ui t s h o u ld be p l ac ed on th e s a m e s i d e of t he b oard as the d e v i c e . place the os cil l a t or c i rc uit cl ose to th e res p e c ti ve os cil l a t or pi ns w i th n o mo r e t h an 0 . 5 i nc h ( 1 2 m m) b e t w e e n t h e c i r c ui t c om pon en t s a nd the pin s . t he l oa d c ap a c i t ors sh oul d b e pl ace d ne xt t o the os ci lla tor i t se lf, o n the sa me sid e o f the bo ard. u s e a gr oun ded c o p per p our a r oun d th e os ci lla tor c i r- c u i t to i s o l at e i t from s u rro und ing ci rcu i t s . th e g r oun ded co ppe r pou r sh oul d be route d di rect ly to th e m c u gro und . d o not run an y s i g nal tra c e s o r po w e r tra c e s i n s i de th e gro u n d po ur . als o , i f us in g a tw o-s i de d b oard, av oid any tra c es on the othe r si de o f the boa rd w h ere t he crys t a l i s p l a c ed . l a yo ut s ugg es tion s are s h o w n in fi gure 2 - 4. in -lin e p a c k ag es m a y be han dl ed w i th a s i n g le -si ded la yo ut th at com p l e te ly en com p a s s e s th e o s c ill ato r pi ns . wi th fi ne- pitc h p a c k age s, it i s not al w ay s pos s i bl e to com - p l ete l y s u rrou n d the pi ns an d c o m p o nen t s . a s u it abl e s o l u tio n is to t i e the b r ok en gu ard s e ct ion s to a m i rrore d g r oun d laye r . in al l c a s e s , t he gua rd trac e(s) m u s t b e re turn ed t o g r oun d. in pl ann ing the app li ca tion ? s ro utin g a nd i / o ass i g n - m e n t s, e n s u re t hat adj ac ent p o rt p i ns an d oth e r s i g nal s i n c l os e p r ox im ity to th e o s c ill ato r are ben ign (i.e ., fre e o f hi gh f r equ en cie s , sh ort ri se an d fa ll t i m es and oth er s i m i l a r no is e). fo r ad dit i on al i nfo rma t io n an d de si gn g uid an ce o n os ci l l a t or c i r c ui ts, pl e a s e r e f e r t o t h es e m i c r oc h i p ap pli c a t io n n o tes, av ail abl e at the c o rp orat e w e b si te (www .m ic roc h i p .c om ): ? a n 8 26, ?c ryst al o s c ill ato r bas i c s and cr ys t a l se lec t io n f o r rfpi c? and picm ic ro ? de vi ce s? ? a n 8 49, ?bas ic pic m i c ro ? o s c ill ato r de s i gn ? ? a n9 43, ?prac t ic al picm i c ro ? os ci l l a t or a n al ys is a nd d e si gn? ? an9 49, ?ma k i ng y our os ci ll ator work ? f i g ure 2- 4: su gg e s t e d p l a c em ent of the oscillator circu it gnd ` ` ` osci osco sosco sosc i c o p per pour pr im a r y oscilla to r cr ysta l s e co nd ary cr yst al devi ce pi ns pr im a r y oscilla t o r c1 c2 se c o scillator: c1 se c o sc i ll a t o r : c 2 (tied to ground) gnd osco osci bottom layer c opp er p o ur os cill a t o r cr ys tal to p l aye r c o ppe r p o ur c2 c1 devi ce pi ns (ti e d to gr oun d) (tied to ground) sing l e -si d ed an d i n -l i n e l a yo u t s: fi ne - p i t c h ( d u a l - si d e d) l a y o ut s : oscilla to r
? 2010 microchip technology inc. ds39881d-page 23 pic24fj64 ga004 family 2. 7 c onf igur ati on of analog and di git a l p i ns duri ng i c sp oper ati ons if a n i c sp c o m p l i an t e m u l at or is s e le ct ed as a d ebu g- g er , it auto m a t ic al ly in iti ali ze s a l l of the a/d inp ut pin s (anx) a s ?dig it a l ? p i ns . d epe ndi ng on the p a r tic u l a r d e vi ce , th is is don e by s e tti ng a l l bit s i n the ad npc f g re gis t er(s), or c l ea rin g al l b i t i n t he an sx re gis t ers . al l pic 2 4 f de vice s w ill hav e ei the r one or mo re ad n p c f g re gis t ers or se ve ral an sx re gis t er s (on e for ea c h po r t ) ; n o d e v ic e w i ll ha ve bo t h . r e f e r t o se ction 2 1 .0 ? 10-b i t h igh-s p eed a /d c onv er ter ? for mo r e s p e c i f ic in f o r m at i o n. th e bi t s i n the s e re gi ste r s th at co rres pon d to t he a/d pi n s t h a t i n it i a l i z e d t h e em ul a t or mu st no t be ch an g e d by t he u s e r ap pli c a t io n fi rmw a re; o t he rw is e, c o m m u n ic at ion e rrors w i ll res u l t betw e en th e deb ugg er a nd t he dev ic e. if yo ur app lic ati o n ne eds t o u s e ce rt ai n a/d pi ns a s an al og i n p u t p i ns du rin g th e d ebu g s e s s i o n, the us er ap pl ic atio n m us t mo dify t he app r op riat e bi t s durin g i n iti a l i za tio n o f the adc m odu le, as fol l o w s: ? f o r de vi ce s wi th a n adnp c f g regi ste r , c l e a r th e bi t s co rres pon di ng t o th e p i n(s ) to be co nfi gure d as a nal og. do n o t c h a nge any o t her bit s , p a rt icu - l a rly th ose c o rres p o ndi ng to t he pg ec x / pg ed x p air , at any ti me. ? f o r de vi ce s w i th an sx reg i s t ers , s e t t he bit s c o rre spo ndi ng to the pin ( s) t o b e c onf igu r ed as an al og. d o no t c han ge any ot her bit s , p a rti c u l ar ly th os e c o rres p o ndi ng to t he pgec x / pg ed x p a i r , at an y ti me . wh en a mi cro c h i p de bug ger/ em ula t or is u s ed a s a pr ogra m m e r , the u s er ap pli c a t ion fi rmw a re m u s t c o rre ctl y c o n f igu r e t he ad n p c f g or an sx reg i s t ers . au tom ati c i nit ial i z atio n o f thi s r egi ste r is on ly don e du rin g d ebu gg er o pera t io n. fai l ure to c o rrec t l y c onf igu r e the reg i s t er(s ) w i l l res u lt in al l a/d p i ns b e in g re cog n i z ed a s an alo g in put pi ns , res u lti n g i n the po rt v a lu e b e in g re ad as a lo gi c ' 0 ' , w h i c h ma y a f f e ct us er ap pl ic atio n func tio nal ity . 2. 8 u nused i/ os u n us ed i / o p i ns s h o u l d b e co nf i g ur e d as o u t p uts a n d dr ive n t o a log i c l o w st a t e. alte rnat ive l y , co nne ct a 1 k to 1 0 k r e si sto r to v ss on u nused pi ns a n d dri v e th e ou tpu t to lo gic lo w .
pic24fj64ga004 family ds39881d-page 24 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 25 pic24fj64 ga004 family 3. 0 c p u the pi c 24f c p u has a 16-bi t (dat a) mod i fied h a rvard arch itecture w i t h an en hanced ins t r u ction set and a 24-bit instructio n w o rd w i th a v a riable length op code fiel d. the program c ounter (pc ) is 23 bit s w i de and add r es s es up to 4m in structions of us er program mem o ry sp ac e. a s i ngle-cy cle instruc t ion prefetch m e chanis m i s us ed to help m a int a in throughput and pro- v i des predic t able ex ecution. all i nstructions exec ute in a s i ngle cyc le, w i t h the ex ception of ins t r u c t ions that c hange th e program flow , the double-w o rd m o ve ( mov .d ) instruction and the t able instruc t i ons. ove r - hea d- free program loo p c onstruct s are sup port e d u s ing the repea t in structions , w h ic h are interruptible at any poi nt. pic 2 4f de vi ce s ha ve s i x t ee n, 16 -bi t w o rki ng re gis t e r s i n t he prog ram m e r ? s mo del . ea ch of the w o r k in g re gis t er s c an a c t as a da t a , a ddre s s or a ddr ess of fs et re gis t er . the 1 6 th w o rki ng reg i s t er (w1 5 ) op erat es a s a s o ftw ar e s t ac k p o in t e r f o r i n te r r u pts a n d c a l l s . the uppe r 32 kbytes o f the dat a sp ace mem o ry map c an op tionally be map ped i nto program s p ace at any 16k w o r d bounda r y defin ed by the 8-bit program s p ace v i s i bility p a g e a d d r es s (ps v p a g ) regi ster . the program to da t a sp ac e mappi ng feature let s any ins t r u ction ac cess program sp ac e as if it w er e d at a sp ac e. th e ins t ru cti on se t ar chi t ec tur e (isa) has bee n s i g nifi c a ntl y enh anc ed be yo nd tha t o f t he pic 18 , b ut ma in tai n s a n ac ce pta b l e le ve l of b a ckw ar d co mpa t i b il - i t y . al l pic 1 8 i n s t ruct io ns and ad dre s s i ng m ode s a r e s upp orted, e i th er d i rec t l y , or throu g h si mp le m a c r os . m a n y of the isa en han ce me nt s h a v e bee n driv en b y c o m p il er e f fi ci en cy nee ds . th e c o re s upp ort s in her ent (no ope ran d ), r e la tiv e , li t e ra l , me mo r y d i re c t an d t h r ee g r o ups of ad dr e s s i ng m o d e s. al l mo de s su ppo rt r egi ste r d i rec t and var i ou s r e gis t er i ndi rec t mo des . eac h g r oup of fers up t o s e ve n addre s s i n g mo des. in stru cti ons are a s s o c i a t ed w i th p r ede fin ed add res s i ng mo des d epe nd ing up on the i r f un c t i on a l r e qu i r em en ts. f or m os t i ns t r u c t i o ns , t he c or e i s c apa bl e of e x e c ut i ng a d a t a (o r prog ram dat a) me mo ry re ad, a w o rki n g re g- i s te r (da t a) re ad, a d a t a me mo ry w r i t e a nd a pro g ram (i ns t r uc tio n ) m e m o ry rea d pe r ins t ruc t io n c y c l e. as a r es u lt , th r e e par a m e t er i ns t ru c t i o ns ca n b e su p po r t e d , al lo w i ng tr ina r y op erat ion s (th a t is , a + b = c ) to b e ex ec ute d i n a si ngl e c y c l e . a hig h -s pee d, 17 -bit b y 17-b i t mu lti p li er ha s bee n i ncl ud ed to si gni fic an t ly enh an ce t he c ore arit hm eti c c a p a b i lity an d th roug hpu t. th e m u lti p l i er s u p p ort s si gne d, u n s i g ned and mi xe d mo de, 16-b it b y 16 -bi t or 8- bit by 8-bi t, i n te ger m u l t ip lic at ion . all m u lti p l y in s t r u ct i o ns e x ec ut e in a s i n g l e cyc l e . th e 16-b i t alu has b een e nha nc ed w i th i n teg e r div i d e as s i s t h a rdw a re tha t s u p port s an ite r ati v e n o n-re st orin g di vi de a l go rith m. it op era t es i n co nju nc t io n w i th th e repeat i n s t ruc t io n lo opi ng m e c h a n is m a nd a se lec t io n of i t era t iv e di vi de in str uct ion s to s up port 3 2-bi t (or 16 -bi t ), div i d ed by 1 6 -b it, in tege r s i g ned a nd un si gne d di vi si on. all div i d e o pera t io ns requ ire 19 c y c le s to c o m p le te b u t are i n te rrup t ibl e a t an y cy cl e bo un dary . t h e p i c 2 4 f h a s a v e c t or e d ex ce pt i o n s c h e m e w i t h up to 8 s ourc es o f n on - ma sk abl e trap s and u p t o 1 1 8 int er- ru pt s ourc e s . ea ch inte rrup t so urc e c an b e a s s i gn ed to on e o f s ev en p r io rity le ve ls. a b l oc k dia g ra m o f th e c p u i s s h o w n in fi gure 3 -1 . 3. 1 p ro gramm e r ? s model t h e pr o g r a mm er ? s mo de l f o r t h e p i c 2 4f i s sh ow n in fi gur e 3 -2 . a ll reg i st ers in th e prog ram m e r ? s mo del a r e m em ory m ap ped a nd ca n be m ani pu late d dir ect ly b y in s t r u ct i o ns . a de sc r ip t i o n o f ea ch r e g is t er i s pr o v i d ed in t a bl e 3 - 1 . a l l r e g i st e r s as so ci at e d wi t h t h e pr ogra m m e r ? s m ode l a r e m e m o ry m app ed. note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f d e v i c e s . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 2. cpu? (ds39703).
pic24fj64ga004 family ds39881d-page 26 ? 2010 microchip technology inc. f i g ure 3- 1: pi c24f c p u core block d i agram instr u ct i o n d e c ode & control p ch p c l 16 p r og ram c o unt er 16-bit alu 23 23 24 23 da t a bu s instruction reg 16 16 x 16 w register array divide support rom l a tch 16 ea m u x ragu wagu 16 16 8 interrupt controller ps v & t a b l e da t a a ccess co n t r o l blo c k stack control logic lo op co n t r o l lo gi c dat a la tch da t a r a m a d dr es s la tch c o nt r ol s i gn al s to v a ri ou s b l ock s p ro g r a m me mo r y d a t a lat ch a d dr es s b u s 16 l i t e r a l da ta 16 16 har d w a r e m u ltip lie r 16 t o peripheral modules a ddress latch
? 2010 microchip technology inc. ds39881d-page 27 pic24fj64 ga004 family t able 3 - 1 : cpu core regis t ers figure 3-2: programmer?s model re gis t e r (s ) na m e de s c ripti o n w 0 th roug h w 1 5 w o r ki ng r e gi ste r arr a y pc 23-bi t pro g ram co unte r sr alu st a t us reg i s t er spl im s t ack po inte r li mi t v a lu e r e gis t er tb lp ag t a ble me mo ry page add r es s r e gis t er psvp ag progr am s p ac e v i s i bi lit y pa ge addre s s reg i s ter r c o u n t r epe at l oop co u n ter r egi ste r corco n c pu co n t ro l r e g i s t e r no vz c tb lpag 22 0 7 0 0 15 progr am count er t able mem o ry page alu st at u s r egi st er (sr ) wo rking/ addres s regist e r s w0 (w r e g) w1 w2 w3 w4 w5 w6 w7 w8 w9 w1 0 w1 1 w1 2 w1 3 f r ame point e r st a c k po i n t e r p svp ag 7 0 p r ogr am spac e v i s i bilit y ra 0 rcount 15 0 repeat loop count e r spl i m st ack poi n t e r li m i t sr l regist ers or bit s shadow ed f o r push.s and pop .s i n st ruct i ons. 0 0 page addre ss regist er 15 0 cp u control register (corcon) srh w1 4 w1 5 dc ip l 21 0 ?? ? ? ? ? ? ipl 3 psv ? ? ?????????? ?? pc divider w o rking r egi s t er s mult i p l i er regist ers 15 0 value regist er addres s regist er regist e r
pic24fj64ga004 family ds39881d-page 28 ? 2010 microchip technology inc. 3. 2 c pu con t rol r e gist ers regis t er 3-1: sr: a l u s t a t us regis t er u-0 u -0 u-0 u -0 u-0 u -0 u-0 r /w -0 ? ? ? ? ? ? ?d c bi t 15 bi t 8 r/w - 0 (1 ) r/ w - 0 (1 ) r/w - 0 (1 ) r-0 r / w -0 r/w -0 r /w -0 r/w -0 ipl 2 (2 ) ipl 1 (2 ) ip l 0 (2 ) ra n o v z c bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 9 un im pl e m e n te d : read as ? 0 ? bi t 8 dc: al u ha l f ca rry/bo rro w b i t 1 = a c a rry -ou t from the 4 t h l o w - ord e r bi t (for by te-s i z ed dat a) or 8t h lo w - o r de r bit (fo r w o rd-s iz ed dat a ) o f th e re s u lt o c c u rre d 0 = n o ca rry- out from th e 4t h or 8th lo w - o r de r bi t of the res u lt has o c c u rre d bi t 7- 5 ip l 2 : i pl 0 : cp u i n ter r upt prio rity le vel s t atu s bit s (1 , 2 ) 11 1 = cp u in t er r u p t p r io r i ty le ve l is 7 ( 1 5); us er i n te r r u pts d i s a bl ed . 11 0 = cp u in t e r r u p t p r io r i ty le ve l is 6 ( 1 4) 10 1 = cpu in terru pt priori ty lev el is 5 (13) 10 0 = cp u in t e r r u p t p r io r i ty le ve l is 4 ( 1 2) 01 1 = c p u i n te rrupt pri o rit y l e v e l i s 3 (1 1) 01 0 = cp u in t e r r u p t p r io r i ty le ve l is 2 ( 1 0) 00 1 = cp u in t e r r u p t p r io r i ty le ve l is 1 ( 9 ) 00 0 = cp u in t e r r u p t p r io r i ty le ve l is 0 ( 8 ) bi t 4 ra: repeat lo op acti ve bi t 1 = repeat l o op in pr o g r es s 0 = repeat l o op no t in pr o g r es s bi t 3 n: al u ne g a ti v e b i t 1 = r e s u l t wa s ne gat iv e 0 = r e s u l t wa s no n-n ega tiv e (z ero or p o s i ti ve) bi t 2 ov : a l u ov er f l ow b i t 1 = o v e r flo w oc cu rred for s i g ned (2? s co mp lem e n t ) ar ithm et ic in thi s a r ith m e t ic op erati o n 0 = no o v er f l ow h a s oc cu r r e d bi t 1 z: alu z e ro bit 1 = an ope rati on whic h e f fe ct s th e z bit ha s s e t it a t s o m e ti me in the p a s t 0 = th e m o s t re cen t o pera t io n w h i c h ef fec t s the z b i t h a s cl eare d i t (i. e ., a no n-z e ro res u lt ) bi t 0 c: alu carry /bo rrow bi t 1 = a c a rry -ou t fro m t he m o s t si gni fic a n t bi t of the res u l t oc cu rred 0 = no car r y-o u t fr om the mo st sign ifi c a n t b i t o f th e re sul t o c c u rred note 1 : th e i p l s t atu s bit s a r e re ad-o n ly w h en n s t d is (in t c o n 1 < 15>) = 1 . 2: th e i p l s t atu s bit s a r e c onc at ena ted w i th the ipl3 bi t (c o r c o n <3 >) to fo rm t he c p u inte rrupt prio rity l e ve l (i pl). t he val u e in p a re nth e ses ind i c a te s t he i p l w h e n i p l3 = 1 .
? 2010 microchip technology inc. ds39881d-page 29 pic24fj64 ga004 family 3. 3 a ri t h m e t i c logi c uni t (alu) t h e p i c 2 4 f al u is 16 bi ts w i de an d i s c apab l e o f a d d i - ti on, s u b t rac t io n, b i t sh if t s an d lo gic ope rati ons . u n l e s s ot h e r w i s e me nt i o n e d , ar i t hm et i c op e r at i o n s ar e 2 ? s c o m p le me nt in n a tu re. d e p end ing on th e ope rati on, th e al u m a y af fec t the v a lue s of the carr y (c ) , ze ro (z), n e gati v e (n ), o v erflo w (o v) an d d i gi t c a rry (d c ) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bit s , res pec ti ve ly , fo r s ubtra ct ion op erat ion s . th e al u ca n p e rfo r m 8-bi t or 16- bit ope rati ons , d epe ndi ng on t he mo de o f th e i nst ruc t ion th at i s u s e d. da t a for the alu ope rati on ca n com e from the w re gis t er a rray , o r d a t a me mo ry , dep end in g on th e a ddre s s i n g m od e o f t he ins t ru cti on. li ke w i se , o utp ut d a t a from th e al u ca n b e wri tten to the w re gis ter arra y o r a d a t a me mo ry loc a ti on. th e pic 2 4f c p u i n c o rpo r ate s h a rdw a re s upp ort f o r bo th m ult ipl i c atio n an d div i s i on . thi s in clu de s a de di cat ed ha rdw a r e mu ltip li er and s u p port h a rdw a re f o r 1 6 - b i t d i vi so r d i vi si o n . 3.3 . 1 m ul t i pl ier th e alu c o n t ai ns a hi gh-s p e ed, 17 -bi t x 1 7 -b it m ult ipl i er . it s upp ort s u ns i gn ed, s i gn ed or mi xe d s i g n op era t io n in s e ve ral mu lti p li ca tio n m ode s: 1. 16 -bi t x 16-b i t sig n e d 2. 16 -bi t x 16-b i t unsig ned 3. 16 -bi t s i gn ed x 5 - bit (li t era l ) un si gne d 4. 16 -bi t un si gne d x 16 -bit un sig ne d 5. 16 -bi t un si gne d x 5-b i t ( lite r al ) un sig n e d 6. 16 -bi t un si gne d x 16 -bit si gne d 7. 8- bit uns ig ned x 8-bi t un si gne d regis t er 3-2: corcon: cp u control regis t er u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 u-0 r/c-0 r/w-0 u-0 u-0 ? ? ? ?ipl3 (1) psv ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 4 un im pl e m e n te d : r ead as ? 0 ? bi t 3 ip l 3 : c p u inte rrupt prio rity le ve l s t at us bit (1 ) 1 = cpu i n terr upt prio rity le ve l i s g r ea ter th an 7 0 = c p u i n terr upt prio rity le ve l i s 7 or les s bi t 2 ps v : prog ram s p ac e v i s i bi li ty i n d a t a s p a c e ena b le bi t 1 = pro g ram s p ac e vis i b l e in dat a s p ac e 0 = pro g ram s p ac e not vi sib l e in dat a s p ac e bi t 1- 0 un im pl e m e n te d : r ead as ? 0 ? note 1: user interrupts are disabled when ipl3 = 1 .
pic24fj64ga004 family ds39881d-page 30 ? 2010 microchip technology inc. 3.3 . 2 d iv ider th e div i d e blo c k s u p por t s 32 -bit /16-b i t an d 16-b i t/1 6-b i t s i g ned and un si gne d i n teg e r d i v i de op erat ions w i th th e fo ll ow in g da t a siz e s : 1 . 3 2 -bi t s i gn ed/ 16-b i t s i g ned di vi de 2 . 3 2-bi t un si gne d/1 6-bi t u nsi gn ed d i v i de 3 . 1 6 -bi t s i gn ed/ 16-b i t s i g ned di vi de 4 . 1 6-bi t un si gne d/1 6-bi t u nsi gn ed d i v i de th e q uoti en t for a l l div i d e in str uct ion s e nds up in w0 a nd th e re ma ind e r in w1. six t een - b i t si gne d an d u n si gn ed di v in str u cti o n s c a n sp ec ify an y w r e g i s t er fo r b o th th e 16-b i t di vi sor (wn ) , and a n y w reg i s t er (a lig ned ) p a i r (w(m + 1 ) :wm ) for the 3 2 -b it di v i den d. th e div i d e alg ori thm t a ke s on e c y c le p er bit o f d i v i so r , s o bot h 32-b i t/ 16-b i t an d 16-b i t/1 6-b i t in stru cti ons t a k e th e s a m e n u m ber of c y c l e s t o e x ec ut e. 3.3 . 3 m ul ti- b it s h if t su pp o r t th e pic 2 4f a l u s upp ort s bo th s i n g le bi t an d s i ng le -cy c l e , m u l t i-b i t a r ith m e t ic an d l ogi c sh if t s . m u lt i-bi t s h if t s are i m p l e m en ted us ing a s h i f te r blo c k , c a p a b l e of pe rform i n g up t o a 15 -bi t arit hme t ic rig h t s h if t, or up to a 15-b i t le f t sh if t , i n a si ng le c y c l e. al l m u lt i-bi t s h if t in stru ct ion s o n ly s u pp ort r e gis t er d i rec t ad dres si ng f o r bo th th e op erand s ourc e a nd re su lt de st ina t io n. a ful l su mm ary o f ins t ruc t io ns t hat us e the s h i f t op era t io n is p r ovi d e d be lo w in t a b l e 3 -2 . t a ble 3 - 2 : ins t ructions that us e the s i ngle and multi-bit s h if t ope ration i n s t r u ct i o n d es cr ip t i o n asr ari t hm eti c shi f t ri gh t so urc e re gis t e r by on e or mo re b i t s . sl sh if t lef t s ourc e re gi ste r by on e o r mo re b i t s . lsr l ogi ca l s h if t rig h t sou r ce reg i s t er b y one or m o re bi t s .
? 2010 microchip technology inc. ds39881d-page 31 pic24fj64 ga004 family 4 . 0 m em ory organization a s h a r v ar d ar chi t ec tur e d e vi ce s, p i c 2 4 f m i c r o- c ont roll ers fe atu r e s e p a rat e p r ogra m and da t a me mo ry s p a c es and b u s s e s . thi s arc h i t ec ture a l s o all o w s th e di r e ct ac ce ss of p r og r a m me mo r y f r om th e da ta s p a c e d u rin g c o d e ex ec uti on. 4. 1 p r ogram addr ess s p ace th e pr o g r a m a d d r e s s me mor y spac e of t h e p i c2 4f j6 4ga 0 0 4 fa mi ly de vi ces is 4 m i n st r u c t i o n s . th e space i s ad dr es sab l e b y a 24 -b it val u e d e r i ved fr om ei th er th e 2 3 -b it prog ra m c o un te r (pc ) d u ri ng pro - gr a m e x e c ut io n, o r f r om t a bl e op er at io n or d a ta space r e ma pp in g, as de scr ib ed in s ect i o n 4 . 3 ? i n t er f a ci ng p r og r a m an d d a t a me mo r y sp a c e s ? . u s er acc es s to the p r ogra m m emo ry sp ac e is res t ri cte d to the l o w e r h a l f of the ad dre s s ran ge (000 00 0h to 7f ffff h). the e x c e p t ion i s the u s e o f tb lrd/tblwt op era t io ns w h ic h us e tblp ag <7> to p e rm it ac c e s s to th e c on f igu r ati on b i t s and d ev i ce id se cti ons of th e c onf igu r ati on mem or y s p a c e. me mo r y ma p s f o r t h e p i c2 4 f j 6 4 g a 0 0 4 fa mi l y of de vi ce s a r e s h o w n in fi gure 4 -1 . figure 4-1: pr o g ram s p ac e m e m o r y m a p f o r p i c2 4f j64 g a 004 f a mil y de vice s 000000h 0000feh 00 000 2h 00 010 0h f 8 00 0e h f 8 00 10 h fefff eh ffff ffh 00 000 4h 00 020 0h 00 01f e h 00 010 4h r e se t a d d r ess user flas h p r ogra m memo ry (1 1k i ns t ruc t i ons ) de vi d ( 2 ) g oto i n st r u ct io n re se r v e d a l ter nate v e c t or t a bl e re se r ve d i n te rrupt v e c t or t a bl e p i c 24f j32g a c o n f i gur ati o n m e m o ry s p a c e u s er me mo r y s p ac e flash config word s no t e : mem o ry areas are not shown t o sc ale. reset address d e vi ce c o nfi g r egi st ers dev i d ( 2 ) go to in str u ct ion re s e r v e d a l t e rnat e v e cto r t abl e re s e r v e d i n te r r u pt v e ct or t a b l e pi c24f j48g a ff0 00 0h f7f ffeh f 8 00 00 h dev i ce c o n f i g r egi st ers 800000h 7fffffh reserve d re s e r v e d fl as h config words 00 a c 0 0h 0 0 abfeh u ni m pl e m ent ed r e ad ? 0 ? u ni m pl ement ed r ead ? 0 ? r eset address device confi g r egi s t ers us e r f la s h p r og ram m e mory ( 2 2 k in st r u c t io n s ) d evi d ( 2 ) go to in st r u ct io n re s e r v e d a l t e rna t e v e cto r t abl e re s e r v e d int e rru pt v e ct or t abl e pi c24f j64g a reserved flas h c onf i g w o rds u n i m pl emen ted r ead ? 0 ? r e se t a d d r ess devid (2) g oto i n st r u ct io n re se r v e d a l ter nate v e c t or t a bl e re se r ve d i n te rrupt v e c t or t a bl e pi c24f j16g a fl ash c o nfi g w ord s device config registers rese r v e d u ni m pl e m ent ed r e ad ? 0 ? 00 580 0h 00 57f e h 00 2c 0 0 h 00 2b fe h use r f l a sh p r ogr am me mo ry (5. 5 k in st ruc t i ons ) 0 084 00 h 00 83f e h use r f l a sh p r og r a m me mo ry ( 16k in str u ction s)
pic24fj64ga004 family ds39881d-page 32 ? 2010 microchip technology inc. 4 . 1. 1 p r o g r am me mo ry orga ni zati on th e pro gram me mo ry s p ac e is orga niz ed i n w o rd-ad d res s abl e blo c k s . al thou gh it i s trea ted a s 24 b i ts w i de , i t i s mo r e ap p r op r i a t e t o t h i n k of e a c h a ddre s s o f the pro gra m me mo ry as a l ow er an d upp er w or d , w i t h t h e up pe r b y t e of t h e up p er w o r d be i ng u nim pl em ent ed. the low e r w ord al w ays h as an eve n a ddre s s , w h i l e th e up per w o rd ha s an odd add ress (f igu r e 4 -2). pro g ram me mo ry a ddre s s e s a r e al w a y s w o rd -ali gne d o n the low e r w o rd, an d ad dre s s e s a r e in cre m e n te d or d ecr em ente d by t w o duri ng c ode e x e c u t ion . thi s a rrang em ent a l s o pro v id es c o m p a t ib ili ty w i th da t a m e m o ry sp ac e a ddre s s i ng an d m a k e s it p o s s ib le to ac ce ss da ta i n t h e p r og r a m me mo r y s p a c e . 4.1 . 2 h ar d me mo ry v e c t o r s al l pic 2 4f dev ic es res e rv e t he add res s es b e tw ee n 0 000 0h a nd 0 0 0 200 h fo r hard co ded pro g ram ex ec u- ti on v e ct ors . a ha rdw a re r e se t v e c t or is p r ov ide d to re dire ct c ode e x e c u t ion f r om th e def aul t val u e of th e pc on de vi ce r e s e t to th e a c tu al s t art of c ode . a goto i n s t ruc t io n i s pro g ramm ed by th e use r a t 0 000 00h wi th th e a c tu al add res s f o r th e s t art of cod e a t 00 000 2h . pic 2 4f de vi ces als o ha ve tw o inter r upt v ec t or t ab l es , l o c a ted fr om 00 000 4h to 0 000 ffh an d 000 100 h to 0 001 ffh. t hes e v e ct or t a b l e s al low ea ch o f the m a n y d evi ce in terru pt s ou r ce s to be ha ndl ed b y sep ara te isr s . a m o re de t a i l ed d i sc us si on of th e i n te rrupt v e c t or t a bl es is pro v i ded i n se ction 7 .1 ? i nte r rup t v e ctor ta b l e ? . 4 . 1. 3 f l a s h co nf ig ur a t i o n w o r d s in pi c 24fj 6 4 g a 004 fa mi ly d e v i c e s , t h e to p tw o w o rd s of o n -ch i p pro g ra m me mo ry are rese rv ed fo r c onf igu r a- ti on i nfo rma t io n. o n de vi ce r e se t, th e co nfi gura t io n i n form at ion is c o p i ed in to the ap prop ria t e c o nfi gura t io n re gis t ers . th e ad dres s e s o f the fla s h c o nfi gurat io n w o rd for de vi ces i n the pic 2 4 f j 64g a00 4 f a m ily a r e sh o w n i n t a b l e 4 - 1 . t h ei r lo ca t i on i n t h e m e m o r y m a p i s s h o w n wi th th e ot her mem o r y v e c t ors in fi gure 4 -1 . the c onfiguration w o rds in program mem o ry are a co mp act forma t . the ac t u al c on f i guration bit s are m apped in sev e r a l d i f f erent regi sters in the co nfiguration m e mory sp ace . their order in the flash c o nfiguration w or d s do not reflect a corresp onding a r rang ement i n the co nfiguration s p ace. addi t i onal det a ils on the dev ice c onfiguration w o rds are provided in section 24.1 ?configur a t ion bit s ? . t a b l e 4 - 1 : fl as h con f igu ratio n w o rds f o r pic24f j64g a 0 04 fa m i ly de vice s figure 4-2: program me mory organization de v i c e progra m mem o r y (k w o rds) config uratio n wo r d a ddr es ses pic2 4fj 1 6 g a 5 . 5 00 2bfc h: 0 02bf e h pic2 4fj 3 2 g a 1 1 005 7fc h : 0 057 feh pic2 4fj 4 8 g a 1 6 008 3fc h : 0 083 feh pic2 4fj 6 4 g a 2 2 00 abfch: 00abf eh 0 8 16 pc ad dre s s 000000h 000002h 0000 04h 0 000 06h 23 00000000 00000000 00000000 00000000 p r o g r am me mo r y ? p ha nt o m ? b y t e (read as ? 0 ?) least s i gn ifi c a n t w o rd mo st si gn i f i c an t wor d in str u ct ion width 000 00 1h 000 00 3h 000 00 5h 000 00 7h ms w add r es s (l s w ad dre s s )
? 2010 microchip technology inc. ds39881d-page 33 pic24fj64 ga004 family 4. 2 d at a addres s s p ace the pic 24f core has a sep a rate, 16-bit w i de dat a mem- ory sp ac e, add r es s able as a s i ngle linear range . the dat a sp a c e is a cces s ed using tw o address g eneration u n it s (ag u s ) , one each for read an d w r ite o perations. the da t a sp ace m e mory m ap is s how n in figure 4 -3. all ef fectiv e address es ( eas) in the dat a memo r y sp ace are 16 bit s w i de and point to bytes w i thin the dat a s p ace. this giv es a dat a sp a c e a ddress range of 64 kbytes or 32k w ords. the lo w er hal f of the dat a me mory sp ace (that is, w hen ea<15> = 0 ) is use d for implem ented m e mory address e s, w h ile the u pper h a lf (ea<15> = 1 ) is rese r v ed for t h e program sp ac e v i sibil i ty area (see section 4 .3.3 ? r ea ding dat a from progr am memory u s ing pr ogr am s p ace v i s i bi lity ? ). pic 2 4fj 64g a fa mi ly d e vi ce s im pl em ent a to t a l of 8 k by tes of d a t a me mo ry . sho u ld an ea poi n t to a lo c a t i on ou tsi d e o f t h is ar e a , a n a l l ze r o w o r d o r by t e w i ll be ret u rne d . 4 . 2. 1 d at a s p ac e wi d t h th e da t a m e mor y space i s or ga niz e d i n byt e - a d d r e ss abl e, 1 6 - b i t w i de b l oc ks. d a ta is a lig ne d i n d a t a m e m o ry an d re gis t e r s as 16 -bit w o rd s, but al l da t a sp ac e eas re sol v e to by tes . t he l e a s t sign ifi c a n t by tes o f e a c h w o rd hav e ev en ad dre s s e s , w h ile th e m o s t sig n i f ic ant byte s hav e o dd add res s e s . figure 4-3: dat a s p ac e m e m o r y m a p for p i c2 4fj64 ga004 family de vice s (1) 0000h 07f eh fffe h ls b addres s lsb msb ms b add r es s 0 001 h 07 f f h 1f ff h ffff h 8 001 h 800 0h 7f ff h 0 801 h 080 0h 2 001 h n ear 1ff e h sfr sf r sp a c e da t a ram 200 0h 7fffh p r og r a m s pac e v i s i b ili ty area note 1 : d a t a me mo ry area s a r e n o t s h o w n to sc al e. 2: uppe r m e mory limit for pic24fj16gaxxx devices is 17ffh. 27feh (2) 280 0h 27ffh (2) 2 801 h sp a c e da t a s pace implemented da t a ram u n i m plemented read as ? 0 ?
pic24fj64ga004 family ds39881d-page 34 ? 2010 microchip technology inc. 4 . 2. 2 d a t a m e m o ry orga ni zati on and al ig nme n t t o maint a i n backw ard co mp atibil ity w i th p i c ? devic es and improv e dat a sp ac e me mory u s age ef ficien cy , the pic 24f in struction set support s both w o rd and byte ope r a ti ons. as a conse quence of byte ac cess ibility , all ef fec t ive addres s (ea) calc ulations are internall y sc aled to step through w o rd-aligned m e mory . fo r ex ample, the c o r e rec ognizes t h at pos t -m odified r e gister indirect address i ng mode [ws ++] w ill result in a valu e o f ws + 1 for byte operatio ns and ws + 2 for w o rd operations . d a t a by te read s w i ll re ad t he c om pl ete w o rd w h ich co n- t a in s the by te, u s in g th e lsb o f any ea to d e term in e w h ich byt e to s e le ct. t he s e le cte d by te is pl ace d on to th e lsb of th e dat a p a t h . tha t is , d a t a m e m o ry and re g- i s te rs ar e orga ni zed as tw o p a ra lle l, by te -w ide e n ti tie s w i th s hare d (w ord ) ad dres s d e c ode but se p a ra te w r i t e l i ne s. d a t a by te w r ite s on ly w r i t e to th e co rres pon din g s i d e of th e arra y o r r egi ste r w h ic h m a tc he s the by te a ddre s s . al l w o rd a c c e s s es m u s t be al ig ned to an eve n a ddr ess . m i s a li gn ed w o rd da t a fet c he s are n o t su ppo rted , s o ca r e m u s t b e tak e n w h en mi xi ng by t e an d w o r d o p e r a - ti ons, or trans la tin g f r om 8- bit mc u co de. if a m i s a li gn ed re ad o r w r ite is atte mp ted , an add res s e rror t r ap w i l l be ge ne r a t e d . i f t h e er r o r o c cu r r e d o n a r e ad , th e in st ruc t ion un derw a y is c om ple ted ; if i t oc cu rred o n a w r i t e, th e ins t ru cti on w i l l be e x e c u t ed b u t the w r i t e w i l l n o t o c c u r . in ei ther ca se , a tra p i s then ex ec ute d , all o w - in g t h e sy st e m an d/ o r u s er to ex am in e t h e ma ch i n e s t at e pri o r t o e x ec ut ion of t he add res s f aul t. al l b y te l oad s into an y w re gi ste r are l oad ed int o th e l eas t sign ifi c a n t byte . t he m o st si gni fic ant by te is n o t mo di f i ed . a si gn - e xt e n d in s t r u ct i o n ( se ) is pr o v i d ed t o a l lo w us ers to tra n s l at e 8 - bit si gne d d a t a to 16- bit si gne d v a lu es . a l ternati v e l y , for 16 -bi t u n s i gn ed da t a , u s er s c an cl ear the m sb o f a n y w reg i st er by ex ec uti ng a z e ro- e xt end ( ze ) in str u ct ion o n t he ap prop ria t e ad dre s s . al thou gh m o s t i n s t ruc t io ns a r e cap a b l e of op era t ing o n w o rd o r by te dat a s i z e s , i t s hou ld be no ted tha t s o m e i nst ruc t ion s ope rate onl y on w o rds . 4 . 2. 3 n ea r d a t a s p ac e th e 8-kb yte area bet w e en 0 000 h an d 1ff f h i s re ferre d to as th e nea r d a t a s p a c e. l o c a tio n s i n thi s s p ac e are dire ctl y ad dre s s abl e vi a a 13 -bit a b so lu te ad dre s s fie l d w i t h in all me mo ry di rec t in stru cti o ns . th e re ma ind e r o f th e d a t a sp ac e i s add res s ab le in dire ctl y . ad diti on all y , th e w h o l e dat a s p a c e is ad dres sa bl e us in g mov ins t ru cti ons , w h ic h s u p port me mo ry d i rec t ad dres si ng wi th a 1 6 -bi t ad dre s s fie l d. 4.2 . 4 s f r s pace th e firs t 2 k by te s of the ne ar dat a sp ace , from 0 0 00 h to 07f fh, a r e p r im aril y o c c upi ed w i th s p e c i a l f u nc tio n r e gi st e r s ( s fr s ) . t h es e ar e us ed by t h e p i c 2 4 f c o r e an d peri phe ral m odu les fo r c ont roll ing th e o p e r atio n of th e d e vi ce . sfr s a r e dis t ri bute d am ong th e mo dul es th at the y c ont rol an d are ge nera lly grou ped to ge ther by m o d u l e . m uc h of th e sfr sp ace c on t ai ns u nus ed a ddr ess es ; th es e are rea d as ? 0 ? . a di a g r a m of th e s f r s p a c e , s how i ng w here sfr s are ac tu all y i m p l em en ted , i s s how n i n t a bl e 4 -2 . eac h im ple m e n te d are a ind i c a te s a 3 2 -by t e re gi on w h e r e at l eas t on e ad dres s i s im pl e- m ent ed as an sfr . a c o m p l e te li sti ng of im pl eme n te d sfr s , i n c l ud ing th eir add res s e s , is sh ow n in t a b l e s 4 - 3 th roug h 4 -24. t a ble 4 - 2 : imp l em ente d re gions of s f r dat a s p ace sf r s p a ce a ddr es s xx 00 xx 20 xx 40 xx 60 xx 80 x x a 0 xx c 0 xx e0 000 h core icn i n t erru pt s ? 100 h ti mers capture ? compare ? ? ? 200h i 2 c? uart spi ? ? i/o 300h a/d ? ? ? ? ? ? 400h ? ? ? ? ? ? ? ? 500h ? ? ? ? ? ? ? ? 600 h pmp r tc/comp crc ? pps 700h ? ? system nvm/pmd ? ? ? ? le gen d : ? = no i m p l em en ted sfrs in this block
? 2010 microchip technology inc. ds39881d-page 35 pic24fj64ga004 family t a ble 4 - 3 : cpu core regis t ers ma p f ile na m e a d d r b i t 1 5 b i t 1 4 b i t 1 3 b i t 1 2 b i t 1 1 b i t 1 0 b i t 9b i t 8b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 all re s e t s wreg 0 0 0 0 0 w o r kin g re g i ste r 0 0000 wreg 1 0 0 0 2 w o r kin g re g i ste r 1 0000 wreg 2 0 0 0 4 w o r kin g re g i ste r 2 0000 wreg 3 0 0 0 6 w o r kin g re g i ste r 3 0000 wreg 4 0 0 0 8 w o r kin g re g i ste r 4 0000 wreg 5 0 0 0 a w o r kin g re g i ste r 5 0000 w r e g 6 0 00c w o r kin g re g i ste r 6 0000 wreg 7 0 0 0 e w o r kin g re g i ste r 7 0000 wreg 8 0 0 1 0 w o r kin g re g i ste r 8 0000 wreg 9 0 0 1 2 w o r kin g re g i ste r 9 0000 w r e g 10 00 14 w o r kin g re g i ste r 1 0 0000 w r e g 1 1 00 16 w or ki n g r e gi st er 1 1 0000 w r e g 12 00 18 w o r kin g re g i ste r 1 2 0000 w r e g 13 00 1a w o r kin g re g i ste r 1 3 0000 w r e g 14 0 01c w o r kin g re g i ste r 1 4 0000 w r e g 15 00 1e w o r kin g re g i ste r 1 5 0800 s p l im 00 20 s t ac k p o i n t e r li mi t v a l ue r egi st er xxxx pcl 0 0 2 e p r og ra m c o unt er low b y te re gi ste r 0000 pch 0 0 3 0 ? ? ? ? ? ? ? ? p r ogr am c ounter register high byte 0000 tblpag 0032 ? ? ? ? ? ? ? ? t ab l e memory page address register 0000 psvpag 0034 ? ? ? ? ? ? ? ? p r o g r a m s p a c e v i sib ility pa g e a d d r e ss re g i ste r 0000 rc ount 0 0 3 6 r epe at l o o p c o unt er r egi st er xxxx sr 0042 ? ? ? ? ? ? ? d c i pl 2 i pl 1 ipl0 ra n ov z c 0000 corcon 0044 ? ? ? ? ? ? ? ? ? ? ? ? ipl3 psv ? ? 0000 disicnt 0052 ? ? d i s abl e int e rr up t s c o unt er r egi st er xxxx le ge nd: ? = u n i m pl e m en t e d , r ead as ? 0 ?. reset values are shown in hexadecimal. t a ble 4 - 4 : icn r e gis t e r m a p f ile na m e a d dr b i t 1 5 bit 1 4 bit 1 3 bit 1 2 bit 1 1 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn 14i e c n 13i e c n 12i e c n 1 1 i e c n 1 0i e (1 ) cn 9 i e (1 ) cn 8 i e (1 ) c n 7 i e c n6 ie cn 5 i e c n4 ie c n 3 i e c n2 ie cn 1 i e c n 0 ie 00 00 c n e n 2 0062 ? c n 30i e c n 29i e c n 28i e (1 ) c n 27 i e c n 2 6i e (1 ) c n 25i e (1) c n 24i e c n 23 i e c n 2 2i e c n 21i e c n 20i e (1 ) cn 1 9 ie (1 ) cn 1 8 ie (1 ) c n 17i e (1 ) c n 16i e 00 00 c n p u 1 0068 c n 15pu e c n 14p u e c n 13p u e c n 12p u e c n 1 1 pu e c n 1 0pu e (1 ) cn 9 p u e (1 ) cn 8 p u e (1 ) cn 7 p ue cn 6 p ue c n5 p u e cn 4 p u e cn 3 p ue cn 2 p ue c n1 p u e c n0 p u e 00 00 c n p u 2 0 06a ? cn 3 0 p ue cn 2 9 p ue cn28pue (1 ) c n 27 pu e c n 2 6pu e (1 ) cn 2 5 p ue (1) cn 2 4 p ue c n 2 3 pu e c n2 2 p u e cn 2 1 p ue cn 2 0 p ue (1 ) cn 1 9 p ue (1 ) c n 18pu e (1 ) cn 1 7 p ue (1 ) cn 1 6 p ue 00 00 l e ge nd: ? = un im pl em en t ed, r e a d as ? 0 ? . r e se t val ues ar e sh ow n in hexa deci m al . no te 1 : b i ts ar e n o t ava i la bl e on 2 8 - p i n d e vi ces ; r e ad a s ? 0 ?.
pic24fj64ga004 family ds39881d-page 36 ? 2010 microchip technology inc. t a ble 4 - 5 : inte rrupt co n t ro lle r re giste r ma p fi l e na m e a d d r b i t 15 bi t 14 bit 1 3 bit 1 2 b i t 1 1 bit 1 0 b i t 9 b i t 8 b it 7 b it 6 b it 5 b it 4 b it 3 b i t 2 b i t 1 b it 0 al l re s e t s in t c o n 1 0 08 0 n s t d i s ? ? ? ? ? ? ? ? ? ? m a t herr addrer r st ker r oscfail ? 0000 i n t c on2 0 0 8 2 a l t iv t disi ? ? ? ? ? ? ? ? ? ? ? i nt 2 e p i nt 1 e p i nt 0 e p 0000 i f s 0 0084 ? ? a d1 if u1 t x if u1 rxi f spi1 i f spf 1 i f t 3 i f t 2 i f o c 2 if ic2if ? t 1 i f o c1 if ic1 i f i nt 0if 0000 i f s 1 00 86 u 2 t x if u2 rx if i n t 2 if t 5 if t 4 if oc 4if oc3if ? ? ? ? i nt 1 i f cnif c m i f m i2 c1 if si2 c 1 i f 0000 i f s 2 0088 ? ?pmpif ? ? ?oc5if ? i c5 if ic4 i f ic3if ? ? ? spi 2 i f spf 2 i f 0000 if s 3 008a ?rtcif ? ? ? ? ? ? ? ? ? ? ?m i 2 c 2 i fsi2c2if ? 0000 i f s 4 008c ? ? ? ? ? ? ?lvdif ? ? ? ? crc if u2 erif u1erif ? 0000 i e c 0 0094 ? ? a d1 i e u1 t x i e u1 rxie spi1 i e spf 1 i e t 3 i e t 2 i e o c2 ie ic2ie ? t 1i e o c 1 ie i c 1i e i n t 0i e 0000 ie c 1 0 0 9 6 u 2 t x ie u2 r x ie i n t 2 ie t 5 i e t 4 i e oc 4i e oc3ie ? ? ? ? i nt 1 i e cni e cm i e m i 2 c1 ie si 2 c1 i e 0000 i e c 2 00 98 ? ?p m pie ? ? ?o c 5ie ? i c5 i e ic4 i e i c3 ie ? ? ? spi 2 i e spf2 i e 0000 ie c3 009a ?r t cie ? ? ? ? ? ? ? ? ? ? ? m i2c 2 ie s i2c2ie ? 0000 i ec4 009c ? ? ? ? ? ? ?l v die ? ? ? ? c rcie u 2 e ri e u 1erie ? 0000 ip c 0 00 a 4 ? t 1 i p2 t1 i p 1 t 1ip0 ? o c1 ip2 o c1 ip1 o c1ip0 ? i c1 i p 2 i c1 ip1 i c1ip0 ? i nt 0 i p2 i n t 0 ip1 i nt 0 i p0 4444 ip c 1 00 a 6 ? t 2 i p2 t2 i p 1 t 2ip0 ? o c2 ip2 o c2 ip1 o c2ip0 ? i c2 i p 2 i c2 ip1 i c2ip0 ? ? ? ? 4444 ip c 2 00 a 8 ? u 1 r xi p2 u 1 rxi p 1 u 1rxip0 ? spi 1 i p2 spi 1 i p1 spi 1ip0 ? spf1 i p2 spf1 i p1 spf1 i p0 ? t 3 i p2 t3 i p 1 t 3 i p0 4444 ip c 3 00 a a ? ? ? ? ? ? ? ? ? a d1 ip2 a d1 i p 1 a d1 ip0 ? u 1 t x i p2 u1 t x i p 1 u 1 t xi p0 4444 ip c 4 0 0ac ? c nip2 cni p1 cni p 0 ? c mi p 2 c m ip 1 c mip0 ? m i2 c1p 2 m i 2 c 1p 1 m i2c1p0 ? s i 2 c1 p2 si 2 c 1 p 1 s i 2 c1 p0 4444 ip c 5 00 a e ? ? ? ? ? ? ? ? ? ? ? ? ? i nt 1 i p2 i n t 1 ip1 i nt 1 i p0 4444 ip c 6 00 b 0 ? t 4 i p2 t4 i p 1 t 4ip0 ? o c4 ip2 o c4 ip1 o c4ip0 ? o c3 ip2 o c3 ip1 o c3 ip0 ? ? ? ? 4444 ip c 7 00 b 2 ? u 2 t xi p 2 u2 txi p 1 u 2txip0 ? u 2 r xi p2 u2 rxi p 1 u 2rxip0 ? i n t 2i p 2 i n t2 ip 1 i nt2ip0 ? t 5 i p2 t5 i p 1 t 5 i p0 4444 ip c 8 00 b 4 ? ? ? ? ? ? ? ? ? spi 2 i p2 spi 2 i p1 spi 2ip0 ? spf 2 i p2 spf2 i p1 spf2 i p0 4444 ip c 9 00 b 6 ? i c5 ip2 i c5 i p 1 i c5ip0 ? i c4 i p 2 i c4 ip1 i c4 ip0 ? i c3 i p 2 i c3 ip1 i c3ip0 ? ? ? ? 4444 ip c 1 0 0 0b8 ? ? ? ? ? ? ? ? ? o c5 ip2 o c5 ip1 o c5 ip0 ? ? ? ? 4444 ip c 1 1 0 0ba ? ? ? ? ? ? ? ? ? p mp i p 2 p mp i p 1 p mpip0 ? ? ? ? 4444 ip c 1 2 0 0b c ? ? ? ? ? m i2 c 2 p 2 m i 2c 2p 1 m i2c2p0 ? s i 2 c2 p2 si 2 c 2 p 1 s i2c2p0 ? ? ? ? 4444 ip c 1 5 0 0c 2 ? ? ? ? ? r tc i p 2 r tc i p 1 r tcip0 ? ? ? ? ? ? ? ? 4444 ip c 1 6 0 0c 4 ? crci p2 crcip1 cr cip0 ? u 2 e ri p2 u2 eri p 1 u 2erip0 ? u 1 e rip2 u1 erip1 u 1erip0 ? ? ? ? 4444 ip c 1 8 0 0c 8 ? ? ? ? ? ? ? ? ? ? ? ? ? l vdi p 2 l vdi p 1 l vdi p 0 4444 le ge nd: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39881d-page 37 pic24fj64ga004 family t a ble 4 - 6 : t i m e r regis t er map f ile nam e ad d r bit 15 bi t 1 4 bit 13 bit 12 bit 1 1 bit 10 bit 9 b it 8 b it 7 b it 6 b i t 5 b it 4 b it 3 b it 2 b it 1 b i t 0 all r e set s t m r 1 010 0 t i me r1 re g i st er 0000 p r 1 010 2 t i m er1 p eri o d r e gi st e r ffff t 1 c o n 010 4 t on ?t sidl ? ? ? ? ? ? tgate tckps1 tckps0 ? tsync tcs ? 0000 t m r 2 010 6 t i me r2 r e g i s t er 0000 t m r 3 h l d 010 8 t i m e r 3 h o l d i n g r e gi ste r ( f or 32 - b i t ti me r o per ati o ns o n l y ) 0000 tmr 3 01 0a t i me r3 r e g i s t er 0000 pr2 0 1 0 c t i m er2 p eri o d r e gi s t e r ffff pr3 0 1 0 e tim e r3 p eri o d r e gi st e r ffff t2 c o n 0 1 1 0 t o n ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 t3 c o n 0 1 1 2 t o n ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 tmr 4 0 1 14 t i me r4 r e g i s t er 0000 t m r 5 h l d 0 1 1 6 t i m er 5 h o l d i n g r e g i ster (f or 32- bi t o p e r ati o ns o n l y ) 0000 tmr 5 0 1 18 t i me r5 r e g i s t er 0000 pr4 0 1 1 a t i m er4 p e ri o d r e gi st e r ffff pr5 0 1 1 c t i m er5 p eri o d r e gi st e r ffff t4 c o n 0 1 1 e t o n ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 t5con 0120 ton ?t sidl ? ? ? ? ? ? t g a te tckps1 tckps0 ? ?tcs ? 0000 le ge nd: ? = u n i m pl e m en t e d , r e ad as ? 0 ?. reset values are shown in hexadecimal. t a ble 4 - 7 : inp u t cap ture regis t er m a p f ile na m e ad d r bit 15 bit 14 bi t 1 3 bit 12 bit 1 1 bit 10 bit 9 b i t 8 b it 7 b it 6 b it 5 b i t 4 b it 3 b it 2 b it 1 b i t 0 all r e set s i c 1b u f 0 140 in put 1 c a ptu r e r e g i ster ffff i c 1c on 0142 ? ?icsidl ? ? ? ? ? i ct mr ici1 i c i0 i c ov ic b n e i cm2 i cm 1 i cm 0 0000 i c 2b u f 0 144 in put 2 c a ptu r e r e g i ster ffff i c 2c on 0146 ? ?icsidl ? ? ? ? ? i ct mr ici1 i c i0 i c ov ic b n e i cm2 i cm 1 i cm 0 0000 i c 3b u f 0 148 in put 3 c a ptu r e r e g i ster ffff i c 3c on 014a ? ?icsidl ? ? ? ? ? i ct mr ici1 i c i0 i c ov ic b n e i cm2 i cm 1 i cm 0 0000 ic 4 b u f 01 4c in put 4 c a ptu r e r e g i ster ffff i c 4c on 014e ? ?icsidl ? ? ? ? ? i ct mr ici1 i c i0 i c ov ic b n e i cm2 i cm 1 i cm 0 0000 i c 5b u f 0 150 in put 5 c a ptu r e r e g i ster ffff i c 5c on 0152 ? ?icsidl ? ? ? ? ? i ct mr ici1 i c i0 i c ov ic b n e i cm2 i cm 1 i cm 0 0000 le ge nd: ? = u n i m pl e m en t e d , r e ad as ? 0 ?. reset values are shown in hexadecimal.
pic24fj64ga004 family ds39881d-page 38 ? 2010 microchip technology inc. t a ble 4 - 8 : output com p are re g i ste r map f ile na m e ad d r bit 15 bit 1 4 bi t 1 3 bi t 1 2 bit 1 1 bit 10 bit 9 b it 8 b it 7 b it 6 b it 5 b it 4 b i t 3 b i t 2 b it 1 b it 0 all r e set s o c 1r s 018 0 out put c o m p a r e 1 s e co nd ary r e g i s t er ffff o c 1r 018 2 o u t p ut co mp ar e 1 re g i st er ffff o c 1c o n 018 4 ? ?o csidl ? ? ? ? ? ? ? ? o cf l t o c t s e l o c m2 ocm 1 ocm0 0000 o c 2r s 018 6 out put c o m p a r e 2 s e co nd ary r e g i s t er ffff o c 2r 018 8 o u t p ut c o mp ar e 2 r e g i s t er ffff oc 2 con 018a ? ?o csidl ? ? ? ? ? ? ? ? o cf l t o c t s e l o c m2 ocm 1 ocm0 0000 oc 3 r s 0 18 c out put c o m p a r e 3 s e co nd ary r e g i s t er ffff oc 3 r 01 8e o u t p ut c o mp ar e 3 r e g i s t er ffff o c 3con 0190 ? ?o csidl ? ? ? ? ? ? ? ? o cf l t o c t s e l o c m2 ocm 1 ocm0 0000 o c 4r s 019 2 out put c o m p a r e 4 s e co nd ary r e g i s t er ffff o c 4r 019 4 o u t p ut c o mp ar e 4 r e g i s t er ffff o c 4con 0196 ? ?o csidl ? ? ? ? ? ? ? ? o cf l t o c t s e l o c m2 ocm 1 ocm0 0000 o c 5r s 019 8 out put c o m p a r e 5 s e co nd ary r e g i s t er ffff oc 5 r 01 9a o u t p ut c o mp ar e 5 r e g i s t er ffff o c 5con 019c ? ?o csidl ? ? ? ? ? ? ? ? o cf l t o c t s e l o c m2 ocm 1 ocm0 0000 le ge nd: ? = u nimplemented, read as ? 0 ?. reset values are shown in hexadecimal. t a b l e 4- 9: i 2 c? regis t er map f ile na m e ad d r bit 15 bit 14 bit 13 bit 1 2 bit 1 1 bi t 1 0 bi t 9 b i t 8 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b i t 1 b it 0 al l re s e t s i 2 c1 rc v 0 2 0 0 ? ? ? ? ? ? ? ? r e c eive reg i ster 1 000 0 i2 c 1 t r n 0 2 0 2 ? ? ? ? ? ? ? ? t ra nsm i t r e g i ster 1 00f f i2 c 1 b r g 0 2 0 4 ? ? ? ? ? ? ? b aud r a t e g ene rat o r r egi st er 1 000 0 i 2 c1 co n 0 2 0 6 i 2 c en ? i 2 c s i dl s c l r el i p m i en a 1 0 m di ssl w s m e n g cen s tren ackdt a cken rcen p e n rs en sen 100 0 i 2 c1 st a t 0 2 0 8 ackst a t trstat ? ? ? b cl gcst a t a dd1 0 i wcol i2 co v d/a psr/w rbf t bf 000 0 i 2c 1 a d d 0 20a ? ? ? ? ? ? a ddr ess r egi s t er 1 000 0 i 2 c 1 msk 020c ? ? ? ? ? ? a m sk9 a m sk8 a m sk7 am sk 6 a m s k5 am s k4 am sk3 am sk2 am sk1 ams k0 000 0 i 2 c2 rc v 0 2 1 0 ? ? ? ? ? ? ? ? r e c eive reg i ster 2 000 0 i2 c 2 t r n 0212 ? ? ? ? ? ? ? ? t ra nsm i t r e g i ster 2 00f f i2 c 2 b r g 0214 ? ? ? ? ? ? ? b aud r a t e g ene rat o r r egi st er 2 000 0 i 2 c2 co n 0 2 1 6 i 2 c en ? i 2 c s i dl s c l r el i p m i en a 1 0 m di ssl w s m e n g cen s tren ackdt a cken rcen p e n rs en sen 100 0 i 2 c2 st a t 0 2 1 8 a c kst a t trst a t ? ? ? b cl gcst a t a dd1 0 i wcol i2 co v d / a psr/w rbf t bf 000 0 i 2 c 2a d d 0 21a ? ? ? ? ? ? a ddr ess r egi s t er 2 000 0 i 2c 2m sk 021 c ? ? ? ? ? ? am sk9 a m sk8 a m sk7 am sk 6 am s k5 am s k4 amsk3 am sk2 amsk1 am s k0 000 0 le ge nd: ? = u n i m pl e m en t e d , r e ad as ? 0 ? . re set val u e s ar e sh ow n in h e xa dec i m al .
? 2010 microchip technology inc. ds39881d-page 39 pic24fj64ga004 family t a ble 4 - 1 0 : uart re giste r m a p fi l e na m e ad d r bi t 15 bit 1 4 bit 1 3 bit 12 bi t 1 1 b it 10 bit 9 b i t 8 b it 7 b it 6 b i t 5 b it 4 b it 3 b it 2 b i t 1 b i t 0 al l re s e t s u 1 m o de 0 2 2 0 uart en ? u si dl i r en rtsmd ? u en1 u en0 w ake l pback abaud r xi nv brg h pd s e l 1 pdsel 0 s tse l 0000 u 1 st a 0 2 2 2 u txi sel 1 utxinv utxisel0 ? u txbrk u t xen utx b f t rm t u r x i sel 1 u r x i sel 0 a d d en r i dl e p e r r f err o err u r x da 0110 u1 t x r e g 0224 ? ? ? ? ? ? ? u tx8 u tx7 u tx6 u t x 5 u tx 4 u tx3 u tx2 u t x 1 u tx 0 0000 u 1 rxreg 0226 ? ? ? ? ? ? ? urx8 urx7 urx6 u r x 5 urx4 urx3 urx2 u r x 1 urx0 0000 u1 b r g 0 2 2 8 b a ud ra te ge ne ra to r p r e sca ler re gist er 0000 u 2 m o de 0 2 3 0 uart en ? u si dl i r en rtsmd ? u en1 u en0 w ake l pback abaud r xi nv brg h pd s e l 1 pdsel 0 s tse l 0000 u 2 st a 0 2 3 2 u txi sel 1 utxinv utxisel0 ? u t xbrk u t xen ut x b f t rm t urci sel 1 urci sel 0 a d d en r i dl e p e r r f err o err u r x da 0110 u2 t x r e g 0234 ? ? ? ? ? ? ? u tx8 u tx7 u tx6 u t x 5 u tx 4 u tx3 u tx2 u t x 1 u tx 0 0000 u 2 rxreg 0236 ? ? ? ? ? ? ? urx8 urx7 urx6 u r x 5 urx4 urx3 urx2 u r x 1 urx0 0000 u2 b r g 0 2 3 8 b a ud r a te g e ne rat o r p r e s ca l e r 0000 le ge nd: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. t a ble 4 - 1 1 : s p i re giste r m a p f ile na m e a d d r b i t 15 bi t 14 bi t 1 3 b i t 12 bi t 1 1 bi t 10 b i t 9 b it 8 b it 7 b i t 6 b it 5 b it 4 b it 3 b i t 2 b i t 1 b it 0 al l r eset s spi 1 st a t 0 2 4 0 spi en ? spi si dl ? ? spi bec2 spi bec1 spi bec0 s r m pt spi ro v s rxm p t s i sel 2 s i sel 1 s i sel 0 spi t b f spi rbf 0000 spi 1 c o n 1 0 242 ? ? ? d i ssck d i ssdo m o d e1 6 s m p cke ssen c k p m st en spre2 spre1 spre0 ppr e 1 ppre0 0000 spi 1 c o n 2 0 2 4 4 f rm en spi f s d spi fpo l ? ? ? ? ? ? ? ? ? ? ? spi fe spi b e n 0000 s p i 1b u f 02 48 s p i1 t r an sm it/r ece i ve b u ffer 0000 spi2s t a t 0 2 6 0 spi en ? spisidl ? ? spi bec2 spi bec1 spi bec0 s r m pt spi ro v s rxm p t s i sel 2 s i sel 1 s i sel 0 spi t b f spi rbf 0000 spi 2 c on1 0262 ? ? ? d i ssck d i ssdo m o d e1 6 s m p cke ssen c k p m st en spre2 spre1 spre0 ppr e 1 ppre0 0000 spi 2 c o n 2 0 2 6 4 f rm en spi f s d spifpol ? ? ? ? ? ? ? ? ? ? ? spi fe spi b e n 0000 s p i 2b u f 02 68 s p i2 t r an sm it/r ece i ve b u ffer 0000 le ge nd: ? = u n i m pl e m en t e d , r e ad as ? 0 ? . re set val u e s ar e sh ow n in h e xa dec i m al .
pic24fj64ga004 family ds39881d-page 40 ? 2010 microchip technology inc. t a b l e 4- 12 : p or t a regi st er ma p f ile na m e ad d r bit 1 5 bit 14 b i t 13 b i t 12 bit 1 1 bit 10 bit 9 b it 8 b it 7 b i t 6 b it 5 b it 4 b it 3 b it 2 b i t 1 b i t 0 al l re s e t s tr i s a 0 2 c 0 ? ? ? ? ? trisa10 (1) trisa9 (1) trisa8 (1) trisa7 (1) ? ? t ri sa4 tri sa3 (2 ) t r i sa2 (3 ) tri sa1 t r i sa0 079f porta 02c2 ? ? ? ? ?ra10 (1) ra9 (1) ra8 (1) ra7 (1) ? ?r a 4 r a 3 (2 ) ra2 (3 ) ra1 r a0 0000 lata 02c4 ? ? ? ? ?lata10 (1) lata9 (1) lata8 (1) lata7 (1) ? ?l a t a 4 l a t a 3 (2 ) la t a 2 (3 ) la t a 1 l a t a 0 0000 odca 02c6 ? ? ? ? ?oda10 (1) oda9 (1) oda8 (1) oda7 (1) ? ? o da4 o da3 (2 ) od a 2 (3 ) o d a1 o d a0 0000 le ge nd: ? = u n i m pl e m en t e d , r e ad as ? 0 ? . r e set val u e s ar e sh ow n i n h e xa dec i m al . no t e 1 : b i ts ar e n o t a v ai l a bl e o n 2 8 - p i n d e vi ce s; r ead as ? 0 ?. 2: bits a r e a v a ila b l e o n ly wh e n th e p r im a r y o s cilla to r is d i sa b l e d ( p oscm d<1 : 0 > = 00 ); o t he rw i s e re ad as ? 0 ?. 3: bits are available only when the primary oscillator is disabled or ec mode is selected (poscmd<1:0> = 00 or 11 ) and clko is disabled (osciofnc = 0 ); otherwise, read as ? 0 ?. t a b l e 4- 13 : p or t b r e gi st e r ma p f ile name ad d r bi t 1 5 bit 14 bit 13 bit 12 bit 1 1 bi t 1 0 bi t 9 b it 8 b it 7 b it 6 b it 5 b it 4 b i t 3 b it 2 b it 1 b it 0 all r ese t s tri s b 0 2 c 8 t ri sb1 5 t ri sb1 4 t ri sb1 3 t r i sb 1 2 t r i s b 1 1 t ri sb1 0 t ri sb9 tr i sb8 tri sb7 tri s b 6 t r i s b5 t r i sb4 tri sb3 tri sb2 tri sb1 t r i s b 0 ffff po r t b 0 2 c a r b1 5 r b 1 4 r b1 3 r b1 2 r b1 1 r b1 0 r b9 rb8 r b 7 rb6 r b5 rb4 r b3 rb 2 r b1 rb0 0000 l a t b 02 c c la t b 15 l a t b 14 l a t b 13 la t b 1 2 la tb 1 1 la tb 10 la tb 9 l a t b 8 l a t b 7 l a t b 6 la tb 5 l a t b 4 la t b 3 l a t b 2 l a t b 1 l a t b 0 0000 o dcb 0 2 ce o d b1 5 o db1 4 o d b13 o db1 2 o d b1 1 o db 1 0 o d b 9 o d b8 o d b7 o d b6 o d b5 o d b 4 o d b3 o d b2 o d b1 o d b0 0000 le ge nd: ? = u n i m pl e m en t e d , r e ad as ? 0 ? . re set val u e s ar e sh ow n in h e xa dec i m al . tabl e 4- 14 : p or t c r e gi st e r ma p f ile na m e ad d r bit 15 bit 14 b i t 1 3 bi t 12 bit 1 1 bit 10 bit 9 b it 8 b i t 7 b it 6 b i t 5 b it 4 b it 3 b it 2 b it 1 b it 0 a ll re s e t s tr i s c (1 ) 02 d 0 ? ? ? ? ? ? t ri sc9 t ri sc8 t r i sc7 t ri sc6 t ri sc5 t ri sc4 t ri sc3 t ri sc2 t ri sc1 t ri s c 0 03ff po r t c (1) 02d2 ? ? ? ? ? ? rc9 rc 8 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 0000 la tc (1 ) 02d4 ? ? ? ? ? ? l a t c9 l a t c8 l a t c 7 l a t c6 l a t c5 l a t c4 l a t c3 l a t c2 l a t c1 l a t c0 0000 o dcc (1 ) 02d6 ? ? ? ? ? ? o dc9 o s c8 odc7 o dc6 o dc5 odc4 odc3 o dc2 odc1 o dc0 0000 le ge nd: ? = u n i m pl e m en t e d , r e ad as ? 0 ? . r e set val u e s ar e sh ow n i n h e xa dec i m al . no t e 1 : b i ts ar e not available on 28-pin devices; read as ? 0 ?. t a ble 4 - 1 5 : p ad config uration re giste r m a p f ile na m e ad d r bit 1 5 bit 14 bit 13 bit 1 2 bit 1 1 bit 10 bit 9 b it 8 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 al l re s e t s pa d c f g 1 0 2 f c ? ? ? ? ? ? ? ? ? ? ? ? ? ? r t secsel pm pt tl 0000 le ge nd: ? = u n i m plemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39881d-page 41 pic24fj64ga004 family t a ble 4 - 1 6 : adc re gis t e r m a p fi l e na m e ad d r bit 15 bi t 1 4 bit 13 bi t 1 2 bi t 1 1 bi t 10 bit 9 b i t 8 b it 7 b i t 6 b it 5 b i t 4 b it 3 b it 2 b it 1 b it 0 all re s e t s ad c1 buf0 0 3 0 0 adc da ta bu f f e r 0 x xxx ad c1 buf1 0 3 0 2 adc da ta bu f f e r 1 x xxx ad c1 buf2 0 3 0 4 adc da ta bu f f e r 2 x xxx ad c1 buf3 0 3 0 6 adc da ta bu f f e r 3 x xxx ad c1 buf4 0 3 0 8 adc da ta bu f f e r 4 x xxx ad c1 buf5 0 3 0 a adc da ta bu f f e r 5 x xxx ad c1 buf6 0 3 0 c adc da ta bu f f e r 6 x xxx ad c1 buf7 0 3 0 e adc da ta bu f f e r 7 x xxx ad c1 buf8 0 3 1 0 adc da ta bu f f e r 8 x xxx ad c1 buf9 0 3 1 2 adc da ta bu f f e r 9 x xxx ad c1 buf a 0 3 1 4 adc da t a bu f f e r 1 0 x xxx ad c1 bufb 0 3 1 6 ad c da t a bu f f e r 1 1 x xxx ad c1 bufc 0 3 1 8 adc da t a bu f f e r 1 2 x xxx ad c1 bufd 0 3 1 a adc da t a bu f f e r 1 3 x xxx ad c1 bufe 0 3 1 c adc da t a bu f f e r 1 4 x xxx ad c1 buff 0 3 1 e adc da t a bu f f e r 1 5 x xxx ad 1 c o n 1 0 3 2 0 a do n ?adsidl ? ? ? f o r m 1 fo r m 0 ssrc2 ssrc 1 ssrc0 ? ? a sam sam p d o n e 0 000 a d 1 c on 2 0322 vcfg2 vcfg1 vcfg0 ? ?cscna ? ?bufs ? sm pi 3 smpi 2 sm pi 1 sm pi 0 bufm al t s 0 000 ad 1 c o n 3 0 3 2 4 ad r c ? ? samc4 samc3 samc2 samc1 samc0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 ad cs0 0 000 ad 1 chs 0 3 2 8 ch0nb ? ? ? ch0 sb3 ch 0 sb2 ch0 sb1 c h 0 sb0 ch0 na ? ? ? ch0 sa3 ch0 s a 2 c h 0 sa1 ch0 sa0 0 000 a d 1p c f g 0 32 c p c f g15 ? ? p cf g1 2 p cf g1 1 p cf g 1 0 p cf g 9 pcf g 8 (1 ) pcfg 7 (1 ) pcfg 6 (1 ) pcfg 5 p cfg 4 pcfg 3 p c f g 2 pcfg 1 p c f g 0 0 000 ad 1 c ssl 0 3 3 0 c ssl 1 5 ? ? c ssl 1 2 cssl 1 1 cssl 1 0 c ssl 9 c ssl 8 (1 ) cssl 7 (1 ) cssl 6 (1 ) cssl 5 c ssl 4 c ssl 3 c ssl 2 c ssl 1 c ssl 0 0 000 leg e nd : ? = u n i m pl e m en t e d , r ead as ? 0 ? . r e set val u e s ar e sh ow n i n h e xa dec i m al . no t e 1 : b i ts ar e n o t a v ai l a bl e o n 2 8 - p i n d e vi ce s; r ead as ? 0 ?. t a bl e 4 - 1 7 : p ar al l e l m a st e r /s la ve po rt r e g i s t e r m a p fi l e na m e ad d r bi t 1 5 bi t 1 4 bit 13 bit 12 bi t 1 1 bit 10 bit 9 b it 8 b it 7 b it 6 b it 5 b it 4 b i t 3 b it 2 b it 1 b it 0 all r e set s pm co n 0 6 0 0 pmpen ? psi dl a d r m u x 1 a d r m u x 0 p t been pt wr e n ptrden csf1 csf0 alp ? c s1 p bep wrsp rdsp 0000 pm m o de 0 6 0 2 busy i r q m 1 i rq m 0 i ncm 1 i ncm 0 m o d e 1 6 m o d e 1 m o de0 w ai t b1 w ai tb0 w ai tm 3 w ai tm 2 w ai tm 1 w ai tm0 w ai t e1 w a i t e0 0000 p m a d d r 06 04 ?c s 1 ? ? ? a ddr 1 0 addr9 addr8 ad dr7 ad dr6 add r 5 a ddr 4 a ddr3 addr2 addr1 addr0 0000 pm dout 1 pa r a lle l po r t da t a o u t re g i ste r 1 ( b u f fe r s 0 a n d 1 ) 0000 pm dout 2 0 6 0 6 p a r a lle l po r t da t a o u t re g i ste r 2 ( b u f fe r s 2 a n d 3 ) 0000 p m d i n 1 0 6 0 8 p a r a l l e l p o rt d a t a in r e gi s t er 1 (b u f f e r s 0 an d 1) 0000 p m d i n 2 0 6 0 a p a r a l l e l p ort data in register 2 (buffers 2 and 3) 0000 pmaen 060c ?p t e n14 ? ? ? pten1 0 p t en9 pten8 pten7 pten6 pte n5 pten4 p t e n 3 pt en 2 p t e n1 pten0 0000 pm st a t 0 6 0 e i bf i bo v ? ? i b3 f i b2 f i b1 f i b0 f o be o b uf ? ? o b3 e o b2 e o b1 e o b0 e 0000 le ge nd: ? = u n i m pl e m en t e d , r ead as ? 0 ?. reset values are shown in hexadecimal.
pic24fj64ga004 family ds39881d-page 42 ? 2010 microchip technology inc. t a ble 4 - 1 8 : r ea l- t i me clock and calen dar re giste r ma p f ile na m e a d d r bi t 15 bit 14 bit 13 bi t 12 bit 1 1 bit 1 0 bit 9 b it 8 b it 7 b it 6 b it 5 b it 4 b it 3 b i t 2 b i t 1 b it 0 all re s e t s a l r m v a l 0 6 2 0 a l a r m v a l u e r e gi ste r w i nd ow b a se d on a l r m p t r < 1 : 0 > xx xx al cfg r pt 0 6 2 2 al rm en chi m e am ask3 am ask2 am ask1 am a sk0 al rm ptr1 al rm pt r 0 arpt 7 a rpt6 arpt5 a rpt4 arpt3 a rpt2 arpt1 a rpt0 00 00 rt cv al 0 6 2 4 r t cc v a lu e re g i st e r win d o w ba se d o n r t cpt r <1 : 0 > xx xx rc f g c a l 0 6 2 6 r t c e n ? r tcwren r t csync h al fsec r t co e r tcptr1 r t c p t r 0 c al 7 c al 6 c al 5 c al 4 c al 3 c al 2 c al 1 c al 0 00 00 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. t a ble 4 - 1 9 : dual com p arator re giste r m a p fi l e name ad d r bi t 15 b i t 14 bi t 1 3 bi t 1 2 bi t 1 1 bi t 1 0 bi t 9 b i t 8 b it 7 b i t 6 b it 5 b i t 4 b it 3 b it 2 b it 1 b it 0 al l r ese t s cm con 0 6 3 0 cm idl ? c 2 evt c1 evt c 2 en c1 en c 2 ou t e n c 1 o u t en c2 out c 1 o ut c2 inv c 1 i nv c2 neg c 2 p os c1 neg c 1 p os 0 000 cvrcon 0632 ? ? ? ? ? ? ? ? c v r en cvro e c vrr c vrs s cvr3 cvr2 cvr1 cv r0 0 000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. t a ble 4 - 2 0 : crc r e gis t e r m a p fi l e name a d d r b i t 15 bit 14 bit 1 3 bi t 12 bi t 1 1 bit 1 0 bit 9 b it 8 b it 7 b i t 6 b it 5 b it 4 b it 3 b it 2 b i t 1 b i t 0 all re s e t s cr ccon 0 6 4 0 ? ? csidl vword4 vword3 vword2 vword1 vword0 crcful crcmpt ? crcg o p l e n 3 p l en2 p l e n1 pl en0 0040 crcxor 0642 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 ? 0000 cr cda t 0 6 4 4 crc d a ta i n p u t re g i st e r 0000 cr cwda t 0 6 4 6 cr c re su lt re g i s t e r 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39881d-page 43 pic24fj64ga004 family t a bl e 4 - 2 1 : p e r ip her a l pin se l e ct r e g i s t er m a p f ile na m e ad d r bit 1 5 bi t 1 4 bit 13 b i t 12 bit 1 1 bi t 10 b i t 9 b it 8 b it 7 b it 6 b i t 5 b i t 4 b it 3 b i t 2 b it 1 b it 0 al l re s e t s rpi nr0 0 6 8 0 ? ? ? i nt 1 r4 i nt 1 r3 i nt 1 r 2 i nt 1 r 1 int 1 r0 ? ? ? ? ? ? ? ? 1f00 rpi nr1 0 6 8 2 ? ? ? ? ? ? ? ? ? ? ? i nt 2 r4 i nt 2 r 3 i nt 2 r 2 i nt 2 r 1 i n t 2 r0 001f rpi nr3 0 6 8 6 ? ? ? t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3ckr0 ? ? ? t 2 c kr4 t 2 c kr3 t 2 c kr 2 t 2 c kr1 t 2 c kr0 1f1f rpi nr4 0 6 8 8 ? ? ? t5ckr4 t5ckr3 t5ckr2 t5ckr1 t5ckr0 ? ? ? t 4 c kr4 t 4 c kr3 t 4 c kr 2 t 4 c kr1 t 4 c kr0 1f1f rpi nr7 0 6 8 e ? ? ? ic2r4 ic2r3 ic2r2 ic2r1 ic2r0 ? ? ? i c1 r4 i c 1 r 3 i c1 r2 ic 1 r 1 i c1 r0 1f1f rpi nr8 0 6 9 0 ? ? ? ic4r4 ic4r3 ic4r2 ic4r1 ic4r0 ? ? ? i c3 r4 i c 3 r 3 i c3 r2 ic 3 r 1 i c3 r0 1f1f rpi nr9 0 6 9 2 ? ? ? ? ? ? ? ? ? ? ? i c5 r4 i c 5 r 3 i c5 r2 ic 5 r 1 i c5 r0 001f rpi nr1 1 0 696 ? ? ? ocfbr4 ocfbr3 ocfbr2 ocfbr1 ocfbr0 ? ? ? o cf ar 4 o cf ar3 o cf ar2 o cf ar1 o c f ar0 1f1f rpi nr1 8 0 6a4 ? ? ? u 1 c t s r4 u1 ct sr3 u 1 c t s r2 u1 ct sr1 u 1 c t s r0 ? ? ? u 1 r xr4 u 1 r xr3 u 1 r xr2 u 1 r xr1 u 1 r xr 0 1f1f rpi nr1 9 0 6a6 ? ? ? u 2 c t s r4 u2 ct sr3 u 2 c t s r2 u2 ct sr1 u 2 c t s r0 ? ? ? u 2 r xr4 u 2 r xr3 u 2 r xr2 u 2 r xr1 u 2 r xr 0 1f1f rpi nr2 0 0 6a8 ? ? ? sck1r4 sck1r3 sck1r2 sck1r1 sck1r0 ? ? ? s di1 r 4 s di 1 r 3 s di1 r 2 s di 1 r 1 s di1 r 0 1f1f rpi nr2 1 0 6aa ? ? ? ? ? ? ? ? ? ? ? ss1 r4 ss1 r3 ss1 r 2 ss1 r1 ss1 r0 001f rpi nr2 2 0 6ac ? ? ? sck2r4 sck2r3 sck2r2 sck2r1 sck2r0 ? ? ? s di2 r 4 s di 2 r 3 s di2 r 2 s di 2 r 1 s di2 r 0 1f1f rpi nr2 3 0 6ae ? ? ? ? ? ? ? ? ? ? ? ss2 r4 ss2 r3 ss2 r 2 ss2 r1 ss2 r0 001f r p o r 0 06c0 ? ? ? rp1r4 rp1r3 rp1r2 rp1r1 rp1r0 ? ? ? r p0 r4 rp0 r 3 r p0 r2 rp0 r 1 r p0 r0 0000 r p o r 1 06c2 ? ? ? rp3r4 rp3r3 rp3r2 rp3r1 rp3r0 ? ? ? r p2 r4 rp2 r 3 r p2 r2 rp2 r 1 r p2 r0 0000 r p o r 2 06c4 ? ? ? rp5r4 rp5r3 rp5r2 rp5r1 rp5r0 ? ? ? r p4 r4 rp4 r 3 r p4 r2 rp4 r 1 r p4 r0 0000 r p o r 3 06c6 ? ? ? rp7r4 rp7r3 rp7r2 rp7r1 rp7r0 ? ? ? r p6 r4 rp6 r 3 r p6 r2 rp6 r 1 r p6 r0 0000 r p o r 4 06c8 ? ? ? rp9r4 rp9r3 rp9r2 rp9r1 rp9r0 ? ? ? r p8 r4 rp8 r 3 r p8 r2 rp8 r 1 r p8 r0 0000 rpo r 5 0 6ca ? ? ? rp11r4 rp11r3 rp11r2 rp11r1 rp11r0 ? ? ? r p1 0 r 4 r p1 0 r 3 r p1 0 r 2 r p1 0 r 1 r p1 0 r 0 0000 r p o r 6 06cc ? ? ? rp13r4 rp13r3 rp13r2 rp13r1 rp13r0 ? ? ? r p1 2 r 4 r p1 2 r 3 r p1 2 r 2 r p1 2 r 1 r p1 2 r 0 0000 rpo r 7 0 6ce ? ? ? rp15r4 rp15r3 rp15r2 rp15r1 rp15r0 ? ? ? r p1 4 r 4 r p1 4 r 3 r p1 4 r 2 r p1 4 r 1 r p1 4 r 0 0000 r p o r 8 06d0 ? ? ?r p 1 7 r 4 (1 ) r p 17r 3 (1 ) r p 17r 2 (1 ) rp 1 7 r1 (1 ) r p 17r 0 (1 ) ? ? ?r p 1 6 r 4 (1 ) r p 16r 3 (1 ) r p 16r 2 (1 ) rp 1 6 r1 (1 ) r p 16r 0 (1 ) 0000 r p o r 9 06d2 ? ? ?r p 1 9 r 4 (1 ) r p 19r 3 (1 ) r p 19r 2 (1 ) rp 1 9 r1 (1 ) r p 19r 0 (1 ) ? ? ?r p 1 8 r 4 (1 ) r p 18r 3 (1 ) r p 18r 2 (1 ) rp 1 8 r1 (1 ) r p 18r 0 (1 ) 0000 r p o r 10 06d4 ? ? ?r p 2 1 r 4 (1 ) r p 21r 3 (1 ) r p 21r 2 (1 ) rp 2 1 r1 (1 ) r p 21r 0 (1 ) ? ? ?r p 2 0 r 4 (1 ) r p 20r 3 (1 ) r p 20r 2 (1 ) rp 2 0 r1 (1 ) r p 20r 0 (1 ) 0000 r p o r 11 06d6 ? ? ?r p 2 3 r 4 (1 ) r p 23r 3 (1 ) r p 23r 2 (1 ) rp 2 3 r1 (1 ) r p 23r 0 (1 ) ? ? ?r p 2 2 r 4 (1 ) r p 22r 3 (1 ) r p 22r 2 (1 ) rp 2 2 r1 (1 ) r p 22r 0 (1 ) 0000 r p o r 12 06d8 ? ? ?r p 2 5 r 4 (1 ) r p 25r 3 (1 ) r p 25r 2 (1 ) rp 2 5 r1 (1 ) r p 25r 0 (1 ) ? ? ?r p 2 4 r 4 (1 ) r p 24r 3 (1 ) r p 24r 2 (1 ) rp 2 4 r1 (1 ) r p 24r 0 (1 ) 0000 le ge nd: ? = u n i m pl e m en t e d , r e ad as ? 0 ? . r e set val u e s ar e sh ow n i n h e xa dec i m al . no t e 1 : b i t s are only available on the 44-pin devices; otherwise, they read as ? 0 ?.
pic24fj64ga004 family ds39881d-page 44 ? 2010 microchip technology inc. t a ble 4 - 2 2 : c lock control re g i ste r map f ile na m e a d d r bi t 1 5 bi t 1 4 bi t 1 3 bi t 1 2 b i t 1 1 b i t 1 0 b i t 9 b i t 8 b i t 7 b i t 6 b i t 5 b i t 4 b it 3 b it 2 b it 1 b it 0 all re s e t s r c on 07 40 tr a p r i o p u w r ? ? ? ? c m v reg s ext r s wr swdten wdt o sl eep i d l e bo r p o r (n o t e 1 ) o s cco n 0742 ? cosc2 cosc1 cosc0 ? n os c 2 nos c 1 n os c 0 clk l oc k i o l o c k lock ?c f ? s o s cen o swen (n o t e 2 ) c l kdi v 0744 roi doze2 doze1 doze0 dozen rcdiv2 rcdiv1 rcdiv0 ? ? ? ? ? ? ? ? 3 140 o s ct un 0748 ? ? ? ? ? ? ? ? ? ? t un5 t un4 t un3 t un2 t un1 t un0 0 000 leg e nd : ? = u n i m pl e m en t e d , r ead as ? 0 ? . r e se t v a l u es ar e s h o w n i n he xad e c i ma l . no t e 1 : r c on re gi s t er r e se t v a l u es ar e de pe nd en t o n typ e o f r e se t. 2: osccon register reset values are dependent on configuration fuses and by type of reset. t a bl e 4 - 2 3 : n vm re g i st e r map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 al l r ese t s n v mc on 0760 w r w r e n w r e r r ? ? ? ? ? ? erase ? ? n v m o p 3n v m o p 2n v m o p 1 n v m o p 0 000 0 (1 ) nvmkey 0766 ? ? ? ? ? ? ? ? n vm k ey<7 : 0 > 000 0 legend: ? = un i m p l eme n ted , r ead as ? 0 ? . r e s e t val ues ar e s how n i n h e xa deci m al . note 1: reset value shown is for por only. value on other reset states is dependent on the state of memory write or erase operations at the time of reset. t a b l e 4- 24 : p md r e gi s t er m a p file nameaddrbit 15bit 14bit 13bit 12bit 11bit 10bit 9bit 8bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 al l r eset s p md 1 07 70 t5md t4md t3md t2md t1md ? ? ? i2c1md u2md u1md spi2md spi1md ? ?a d c 1 m d 00 00 pmd2 0772 ? ? ? ic5md ic4md ic3md ic2md ic1md ? ? ? o c5 m d o c4 m d o c3 m d o c2 m d o c1 m d 00 00 pmd 3 07 74 ? ? ? ? ? cmpmd rtccmd pmpmd crcpmd ? ? ? ? ?i2c2md ? 00 00 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39881d-page 45 pic24fj64 ga004 family 4 . 2. 5 s of tw ar e s t ac k in a ddi tio n t o it s u s e as a w o r k in g regi st er , the w1 5 re gis t er in pi c 24f d e v i c e s is al so use d a s a sof t w a re s t ac k po int e r . th e poi nte r a l w a y s po in t s to th e firs t a v ai la ble free w o rd an d gro w s fro m lo w e r to h i gh er ad d r es se s. it pr e - d e c r em en ts f o r sta ck p ops a n d po s t - i n c r e me nts fo r s t a c k p u s h es , as sh o w n in fi gu re 4- 4. n o te th at f o r a pc pus h duri ng any call i n s t ruc t io n, the m sb o f t he pc i s ze ro-ex t e nde d b e fo re th e p u s h , e n s u rin g th at t he msb i s alw a ys cl ear . th e s t a c k poi n te r li mi t v a lu e re gis t er (splim ), a s s o c i - a t ed w i th the s t a c k poi n te r , s e t s an up per add res s b oun dary for t he s t ac k. splim is uni nit i al iz ed a t r e se t. as is the cas e f o r the s t ac k po inte r , spl im< 0 > i s fo rce d to ? 0 ? b e c a us e al l s t a c k op er a t io n s mu st be w o rd-al i gn ed . wh ene ve r a n ea is ge ner ated u s in g w 15 a s a so urc e o r de sti nati o n poi nte r , th e re su ltin g a ddre s s is c o m p are d w i th t he v a lu e in spl im. if th e c ont ent s of th e s t ac k poi n te r (w15 ) a nd th e spli m re gis t er are eq ua l, and a pus h ope rati on is p e rfo r me d, a st ack e rror t r ap w i ll not oc cu r . th e s t a c k erro r tra p w i l l o c c u r o n a su bs equ ent pus h ope rati on. thu s , for e x am pl e, if i t is de si rabl e to c aus e a st ack e rror tra p w h en th e st a c k gro w s bey on d ad dres s 2 000 h in r a m , i n it ial i z e th e spl im w i th the va lue , 1f feh. si m i larl y , a s t ac k po int e r un de rflow (s t a c k erro r) tra p i s g ene rate d w h en the s t ac k p o in ter add res s i s fou nd to b e les s t han 0 80 0h. th is prev en t s th e st ac k fro m in ter f eri ng w i th th e s pec ia l fu nct i on r egi ste r (sfr ) spac e . a w r i t e to the splim re gis t er sho u ld no t be im me dia t el y fo ll ow ed by an ind i re ct re ad ope rati on us ing w15 . f i g ure 4- 4: call s t ack fram e 4. 3 i nter faci ng progra m and dat a memory s p aces th e pic 2 4 f a r ch ite c tu re us es a 24 -bi t w i de pro g ram s p ac e an d 1 6 -bi t w i de da t a sp ac e. the arc h i t ec ture i s al so a m odi fie d h a rv ard s c h e m e , m ean in g tha t dat a c an a l s o be p r es ent i n the prog ram sp ace . t o use thi s d a ta su cc es sf u l l y , it mu st b e ac ce ss ed i n a wa y t h a t pr ese r ve s the ali gnm en t of in form ati on in b oth sp ac es . a s i d e f r om no r m a l ex ec ut i on , t he p i c 24 f ar c hi t ec t ur e pr ovi de s tw o m eth od s by w hic h pr ogra m s p ac e c an b e ac c e s s ed du ring op erat ion : ? u s i ng t ab l e ins t ru cti ons to ac ce ss in div i d ual by tes or w o rds a n yw h e re in the prog ram s p ac e ? r em ap pin g a po rtio n of the pro g ram s p a c e int o th e d at a sp ac e (pr ogra m s p a c e vi si bil i ty ) t abl e in stru ct ion s al low a n ap pli c a t ion to rea d or w r i t e t o s m a l l ar e a s of t h e p r og r a m me mo r y . t h is m a k e s t h e m e th od i dea l for ac c e ss in g da t a t a ble s th at ne ed to b e up da ted from t i m e t o t i m e . i t a l s o a llo w s ac ces s to al l by te s of t he p r ogra m w or d. th e rem a p pin g me tho d al lo w s an a pp lic ati on to ac ces s a larg e bl ock of d at a o n a re ad -onl y ba si s, w h ic h is ide al f or lo ok u p s from a l arge t a ble o f s t at ic da t a. it ca n o nl y acc es s the l eas t si g n i f ic an t wo r d of t h e p r og r a m wo r d . 4 . 3. 1 a d d r e ssi n g p r ogr am s p ac e si nce the a ddr ess ran ges for th e da t a an d pro g ram s p ac es are 1 6 an d 24 b i t s , res pecti vel y , a m e th od i s ne ed ed to cr eate a 2 3 -bi t or 24-b i t pro g ram a d d r es s fro m 16 -bit da t a regi st ers. th e sol u ti on de pen ds on th e i n terf ac e m e th od t o b e us ed . for t abl e operations , the 8-bit t able memo r y page address reg i ster ( t blp a g ) is used to defin e a 3 2 k w ord region w i thi n the program sp ac e. this i s conc atenated w i th a 16-bit ea to arr i v e at a full 2 4 - b it program sp ace addres s. in this format, the mo st signific ant b i t of tblp ag i s used to determ i ne if the operation occ u rs in the user mem o r y (tblp a g < 7> = 0 ) or the co nfiguration me mor y ( t b l p a g<7 > = 1 ). fo r re ma ppi ng op era t ion s , th e 8-bi t pro g ra m s p ac e v i s i bi lity pa ge add r es s regi s t e r (psvp ag) i s us e d to d ef i ne a 16 k w or d pag e i n t he pr o g r am spac e. w h en th e m o s t sign ifi c a n t b i t of the ea is ? 1 ?, psv p a g is co n- c a te nate d w i th th e l o w e r 15 bi t s of th e ea to fo rm a 23 -bi t pro g ram s p ac e a ddre s s . u n l i k e t a b l e ope rati ons , th is lim it s re ma ppi ng ope rati ons s t ric t ly to the us er me mo r y a r ea . t abl e 4 -25 and fig u re 4-5 sho w ho w the prog ram ea i s c r eat ed for t abl e o pera t io ns and rem a p p in g a c c e s s e s fro m the da t a ea. h e re , p< 23: 0> r e fers t o a pro g ram s p ac e w o rd, w h e r eas d < 15 :0> r e fers to a dat a sp ac e wo rd . note : a p c p u s h d u r i ng ex ce pt i o n pr o c e s s i ng w i ll co nc aten ate th e sr l re gi ste r to th e msb of the pc prior to the push. pc<15:0> 000000000 0 15 w15 (before call ) w15 (after call ) s t a ck g r o w s t o wa r d s hi gher a ddre s s 0000h pc<2 2: 16> p op : [- -w1 5] pu sh : [w15++]
pic24fj64ga004 family ds39881d-page 46 ? 2010 microchip technology inc. t a ble 4 - 2 5 : p rogram s p ac e a d dres s construc t i o n figure 4-5: dat a acce ss from program s p ace addr es s ge ner a tio n a c ces s t yp e a cce ss s p ace pr og r a m s p a ce a d dr ess < 23> <22 : 16> <15 > <1 4:1> <0> in str u ct ion a c c e s s (c o de e x ec uti o n ) use r 0 pc<22 : 1> 0 0xx x xxx xxxx xxxx xxx x xxx0 tblrd /tblwt (by t e/ w o rd rea d /w rit e ) u s er tblp ag <7:0 > d at a ea<1 5 :0> 0xxx xx xx xxxx x xxx xxxx xxxx c o nf i gu r at i o n t b l p a g < 7 : 0> d a t a e a < 15 : 0 > 1xxx xx xx xxxx x xxx xxxx xxxx p r og r a m s pac e vi si bi li t y (bl o ck re m a p / re a d ) use r 0 p svp ag<7 :0> d at a ea<14 :0> (1 ) 0 xxxx xxxx xxx xxxx xxxx xxxx note 1 : d a ta e a < 1 5 > i s a l w a y s ? 1 ? in t his ca se , but i s n ot us ed in c alc ul ati ng th e pro gra m s p ac e a ddre s s . bit 1 5 of th e a ddre s s is psvp ag<0> . 0 p r ogra m c o un ter 23 bit s 1 psvp a g 8 bi t s ea 15 bits p r og ram coun t e r (1 ) select tbl p ag 8 bits ea 16 bit s by te se le c t 0 0 1/0 user/config u rat i on table operations (2 ) p r og r a m s pac e vi si bi l i t y (1 ) s pac e s e l ec t 24 bits 23 bits (r em ap pi ng) 1/ 0 0 note 1 : the lsb of pro g ram s p a c e ad dres se s is al w a y s f i xe d as ? 0 ? i n ord e r t o m a i n t a in w o rd ali gnm en t o f dat a i n th e pr ogra m a n d dat a s p a c es . 2: t a ble op era t ion s are no t re qui red to be w o rd -ali gne d. t a ble re ad ope rati ons a r e perm i tt ed in the co nfi gura t io n m em ory sp ac e.
? 2010 microchip technology inc. ds39881d-page 47 pic24fj64 ga004 family 4.3 . 2 d ata ac ces s fr om pr og ra m me mo ry usi n g t a bl e ins t ructions the t blrdl a nd tbl wtl instruc t i ons of fer a direct m e thod of r e a d ing or w r iting the low e r w o rd of any add r e s s w i t h in th e program s p ace w i thout going through dat a sp ac e. the tblr dh and t blwth instr u ctio ns ar e the o n ly m e thod to read or w r ite the upper 8 bit s of a program s p ace w o rd as dat a. t h e p c i s i n cr e m e n t e d by t w o fo r e a c h su cc es si ve 2 4 -bi t pro g ram word . th is a l l o ws p r og ram m e m o ry a ddre s s e s to dire ctl y map to dat a s p ac e a d d r es ses . pro g ram m e m o ry c an thus b e re gard ed as tw o 1 6 -b it w o rd-w id e add res s sp ac es, re si din g sid e by s i de , eac h wi th th e s a m e a ddre s s ra nge . tblrdl and tblwtl a c c e s s the s p ac e w h ic h co nt a i ns t he le ast s i gn ifi c a n t d a t a w o rd , and tblr dh a nd tblwth ac ce ss t he sp ac e w h ich c ont a i n s th e u ppe r da t a b y t e . t w o t a b le i n st ruc t io ns a r e pro v i ded t o mo ve b y t e or w o rd-size d (16-b i t) da t a to an d f r om pr ogra m sp ac e. bo th f unc tio n a s e i th er b y te or wo rd o pera tio ns . 1. tblrd l (t ab le r e a d lo w ) : in w o rd m ode , it m a p s the l o w e r w o rd o f the pr ogra m sp ac e lo c a t i on ( p < 1 5: 0 > ) t o a da ta a d d r es s ( d < 1 5 : 0> ) . in by te mod e , eit her the up per or l o w e r by te of th e low e r pro g ra m w o rd is m app ed to the lo w e r b y te of a dat a a ddre s s . t he upp er b y t e i s s e le ct ed w h e n by te se le ct is ? 1 ?; th e lo w e r by te is se le ct e d w h e n i t is ? 0 ?. 2. tblrdh (t a b l e re a d hi g h ): i n w o r d m o d e , i t maps t h e e n ti re u ppe r w o r d of a pr og ra m a d d r e s s ( p <23: 16> ) to a d a t a a ddre s s . n o te th at d < 1 5 :8 >, th e ? pha nto m ? by te, w i ll alw a ys be ? 0 ?. in byte mo de, it m a p s th e up pe r or lo w e r by te of th e p r og ram w o rd to d < 7: 0> of the dat a ad dre s s , a s a bov e. n o te tha t th e d a t a w i l l al w ay s be ? 0 ? w hen the up per ?p han tom ? b y t e i s s e le cte d ( b yt e s e le ct = 1 ). in a sim ila r f a sh ion , t w o t a ble ins t r u c t io ns, t blwt h an d tbl wtl , ar e use d t o w r it e i n di vid ual by te s or w o rd s to a pr og ra m s p a c e ad dr es s . th e d e t a i l s o f th ei r o p e r a t i on ar e e x pl ain ed in se ct io n 5 . 0 ? fl ash pr og ra m me m o ry ? . for all t able operat ions, the area of progr a m memory sp ac e to be acces s ed is de termined by the t a ble mem o r y p age address register (tblp a g ) . tblp ag covers the entire pr ogram memory sp ace of the device, including user and configurat ion sp aces . when tblp ag <7> = 0 , t he t able p age is located in t he user mem o r y s p ace. w hen tblp ag<7> = 1 , the p a ge is located in configur ation sp ace. figure 4-6: acce ss ing p r og r a m m e m o ry w i th t able ins t r uctions note: only ta b l e re ad op era t io ns w i l l ex ec ute i n th e c onfi g u r ati on m e m o ry sp ac e, a n d o n l y th en, in im ple m e n te d a r eas s u c h as th e d e vi ce id . t a b l e w r i t e o p e r a t i o ns ar e no t al lo w ed. 0 8 16 23 00000000 00000000 00000000 00000000 ? p hant om? b yt e tblrdh.b (w n<0> = 0 ) tblrdl.w tblrdl.b (w n<0> = 1 ) tblrdl.b (w n<0> = 0 ) 23 15 0 tblpag 02 000000h 800000h 020000h 030000h progra m s p ace d a t a ea <15: 0> t he address f o r t he t able operat ion is det er mined by t he dat a ea w i t h in t he page def ined by t he t b l p ag regist er . o n ly r ead operat ions are s hown; w r it e oper at ions ar e also valid in t he user mem o ry area.
pic24fj64ga004 family ds39881d-page 48 ? 2010 microchip technology inc. 4.3 . 3 r ea ding d a t a f r o m pr o g ra m me mo ry usin g p r o g r am s pace vi s i b i l i t y th e u ppe r 32 kby t es of d at a sp ac e m ay opt ion all y b e m ap ped in to any 1 6k w or d p age of th e p r ogra m sp ac e. th is p r ov ide s tra ns p are nt ac ce ss o f sto r ed c ons t a nt d a t a from th e d a t a sp ac e wi tho u t th e n e e d to us e s pec ia l i n s t ruc t io ns (i.e ., tblrd l/h ). program sp ac e a cces s t h r ou gh the dat a sp a c e occurs if the mo st s i gnificant bit of the dat a sp ac e e a is ? 1 ?, and program s p ace visi bility is enable d by se tt i ng the psv bit in the c p u c ontrol regis t er (c or c o n < 2>). the loca- tion of the program m e mory sp ac e to be m apped i n to the dat a sp ac e is determined by th e p r ogram s p ace v i sibil- ity page addres s regis t er (p svp ag ) . this 8 - bi t register defin es any one of 256 pos sible p ages of 16k w o rds in program s p ace. in e f fect, p svp ag func tions as the upp er 8 bi t s of the p r og r am mem or y address, w i th the 15 bi t s of the ea func tioning as the low e r bit s . n o te that by increm enting the p c by 2 for eac h pr o gr a m me mory w ord, the low er 15 bit s of d at a sp ace ad dr e sses di r e ctly m ap t o the low e r 15 bit s in the correspon ding program s p ace addres ses. d a t a rea ds to th is a r ea add an ad di tion al cy cl e to th e i ns t ruc t io n bei ng ex ec ute d, si nc e tw o pro gram me mo ry f e t c he s a r e r e qu i r ed . al tho ugh eac h d a t a sp ac e ad dre s s , 80 00h an d hi ghe r , m a p s dir e ct ly in to a co rres p o ndi ng pro g ram me mo ry a ddre s s (see fig u re 4 - 7), o n ly the l o w e r 16 bi t s of th e 24 -bi t prog ram w o rd a r e us ed to co nt ai n th e da t a . th e up pe r 8 bit s of a n y p r og ram s p a c e l o c a ti ons us ed a s da t a s h o u ld be prog ram m e d w i t h ? 1111 1111 ? o r ? 0000 0000 ? to fo rce a nop . t h is p r ev en t s po ss ibl e is su e s sh ou l d t h e ar e a o f c o de e v er be ac ci d e n t al ly ex ec ute d . fo r o pera t io ns tha t u s e psv a n d are ex ec ute d o u t s id e a repeat l oop , th e m ov an d mov.d i n st r u ct i o n s wi ll re qui re one i ns t ruc t io n cy cl e i n add iti on to th e sp eci f ie d ex ec uti o n tim e . al l ot her i n s t ruc t io ns w ill requ ire tw o i n st ruc t ion cy cl es in a ddi tio n to t he s p e c if ied ex ecu t io n ti me . fo r op erat ion s th at u s e psv whi c h are ex e c u t ed ins i d e a rep eat loo p , th ere w i ll b e so me i n s t an ce s th at re qui re tw o i n s t ruc t io n cy cl es in a ddi tio n to th e s pec if ied ex ec utio n t i m e of the in stru cti o n : ? e x e c u ti on i n t he f i rs t ite r ati o n ? e x e c u ti on i n t he l a s t it erat ion ? e x e c u ti on p r io r to exi t in g th e l oop du e to an i n terr upt ? e x e c u ti on u p o n re- ente r in g th e l oop af t e r an i n terr upt is se rvi c ed an y o t he r ite r ati on o f th e repe at lo op w i ll all ow th e i nst ruc t ion ac ce ss ing dat a, us in g psv , to e x e c u t e in a s i ng le cy cl e. figure 4-7: p r ogram s p ac e v i s i bili t y ope ration note : psv ac c e s s is temporarily disabled during table re ad s/ w r i t es . 23 15 0 psv p a g d a t a s p ace progra m s p ac e 0000h 8000h ff ffh 02 000000 h 800000h 010000 h 0 18000h w hen co rco n<2> = 1 and ea<15> = 1 : psv ar e a t he dat a in t he p a g e de signat ed by ps v - p a g is m apped i n t o t he upper h a l f of t he da t a mem o ry s p ace. . . . data ea<14:0> .. .while the lower 15 bit s of t he ea s pecif y an exac t address w i t h in t he p s v are a. this corresponds exactly to the same lower 15 bits of the actual program space address.
? 2010 microchip technology inc. ds39881d-page 49 pic24fj64 ga004 family 5 . 0 f l a sh p r o g r a m me mo ry th e pic 2 4fj 64g a0 04 fa mi ly o f de vic e s co nt a i ns int e r- n a l f l as h p r ogra m m e m o ry for s t o r ing and ex ec utin g a ppl ic atio n c o d e . th e m e m o ry is rea d a b le , w r it abl e an d e r as abl e w h e n o pera t in g w i th v dd ov er 2 . 25 v . fl as h m e m o ry c an b e p r ogr amm e d in thre e w a ys : ? i n - c i rc uit seri al progra m m i n g ? (i c s p ? ) ? r un -t im e se lf-pr ogra m m i n g (r t sp) ? e n han ce d in -c irc u it seri al pr ogra m m i n g (en han ce d ic sp) i c s p al lo w s a p i c 2 4f j 6 4 g a 0 04 f a mi ly de vi ce t o be s e ri all y p r og ram m e d w h i l e in the en d a ppl ic ati on cir c ui t. th is is si mpl y d one w i th tw o li nes for t he p r ogra m m i n g c l o c k an d p r og ram m i ng dat a (w h i c h a r e n a m e d pg c x and pgdx, respectively), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). t h i s a l lo w s c u s t om er s t o m a n u f ac tu r e bo a r ds w i t h u npro gram m ed de vi ce s and th en pro gra m the m i c r o- cont roll er j u s t bef ore s h i ppi ng the prod uc t. th is als o a llo ws the m o s t re c e n t firm ware o r a c u s t o m fi rm wa re to be pro g ram m ed. r t sp i s acc o m p l i s hed us in g t blrd (t abl e re ad ) an d tblwt (t abl e w r ite ) ins t ruc t i ons . wit h r t sp , th e us er m a y w r ite p r og ram m e m o ry da t a i n bl ocks o f 64 ins t ruc - ti ons (1 92 byt es) at a ti me , an d e r as e p r ogra m mem or y i n bl oc ks of 512 in stru ct ion s (1 536 by tes ) a t a t i m e . 5. 1 t abl e i n st ruct ions and flash pro g ramm i n g r e g a rd les s of t he me thod us ed , al l p r og ram m i ng of f l a s h m e m o r y i s do ne w i t h t h e ta bl e r e ad a n d t a b l e w r i t e i n st r u c t io n s . t h es e al l o w di r e ct r e a d an d w r it e ac c e s s t o th e p r ogr am me mo ry sp ace fro m the dat a m e m o ry w h il e the dev ic e is in norm a l ope rati ng m o d e . th e 2 4 -b it t a rg et a ddr ess i n t he prog ram m e m o ry i s fo rme d usi ng the t b lp ag< 7 :0> bi t s an d the ef fect iv e ad dres s (ea) fr om a w regi st er sp ec ifi ed in the t a bl e in s t r u ct i o n, as sh ow n i n f i g u r e 5 - 1 . th e tblrd l and the tblwtl i n s t ruc t io ns are us ed to re ad or w r it e to bi t s < 15:0 > of pro g ra m me mo ry . tblrdl and tblwtl c an acc e s s p r og ram me mo ry i n bo th w o rd a nd by te mo des . th e tblrdh a nd tblwth i n s t ruct io ns a r e us ed to rea d or w r i t e to b i t s <23 : 16 > of pro g ram me mo ry . tblrdh an d tblwth c a n a l s o ac ce ss prog ram me mo ry in w o rd or byt e m ode . figure 5-1: addre ss ing for t able re g i s t er s note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i nten de d to be a com pr ehe nsi v e refer enc e source . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ? s ec tion 4. progra m me mory ? (d s3 971 5). 0 pr ogr am c ounter 24 bit s program tblpag re g 8 bi t s wo r k i n g r e g e a 16 bi t s using byte 24- bi t ea 0 1/ 0 sel e c t t abl e in str u cti o n c o unt er us i n g user/con fi g u r a ti o n s pac e se le c t
pic24fj64ga004 family ds39881d-page 50 ? 2010 microchip technology inc. 5. 2 r tsp o p e r ati o n t h e p i c 2 4 f f l as h p r og r a m me mo r y ar r a y i s o r ga ni z e d i n to ro w s o f 64 i n s t ruc t io ns o r 192 by tes . rt sp a llo w s th e u s e r to e r as e b l oc ks of ei ght row s (512 in stru cti o n s ) a t a t i me a n d to p r ogra m on e row at a tim e . it is als o p oss ib le to p r og ram si ngl e w o rds . t h e 8-r o w e r as e bl oc ks a n d si ng le ro w w r i t e b l o c ks ar e e d g e -a li gn ed , f r om t h e be gi nn in g o f p r o g ra m m e m o ry , o n bo un da r i e s of 15 36 b y t e s an d 19 2 b y t e s, r e sp ec ti ve ly . w hen d at a i s wr i tten t o pro gram me mo ry us in g tblwt i n s t ruct io ns, th e dat a is no t w r i tte n d i re ctl y to m e mo ry . in ste ad , dat a w r it ten u s i ng t abl e w r i t es is sto r ed i n h old ing l atc he s un til th e pro gram m i ng s eq uen ce i s e x ec ut ed. an y n u m ber of tblwt in st ruc t ion s ca n be ex ec ute d an d a w r i t e w i l l b e su cc es sf u l l y pe r f or m e d . h o w e v e r , 64 tblwt i n s t ruc t io ns are re qui red t o wr ite the ful l row of me mo r y . t o e n su re t hat n o d a t a is co rrupt ed d u ri ng a w r ite , an y u nused ad dre s s e s s hou ld be p r ogra m m e d w i th ff ffff h. thi s is be ca use th e hol din g latc he s res e t to a n un kn ow n s t at e, s o i f the ad dres se s a r e l e f t i n th e r e set s t at e, the y m a y o v er w r ite th e loc a t i on s on ro w s wh i c h we re n o t re wri tte n . th e ba si c s equ en ce f o r r t sp p r og ram m i ng i s to s e t u p a t a b l e poin ter , then do a se rie s of tblwt in str u ct ion s t o l o a d t h e bu ffe r s . p r og r a mmi n g i s pe r f or m e d by s e tti ng the co ntro l b i t s in the nvmco n re gis t er . d a t a ca n be l oad ed i n any orde r and t he ho ld ing re gi s- te rs ca n b e w r i tte n to m u l t ipl e tim e s be fore pe rform i n g a w r i t e op erat ion . subs eq uen t w r ite s , ho w e v e r , w i l l w i pe o u t a n y pre v i ous wr it es . al l of the t abl e w r ite o p e r atio ns a r e si ng le-w o r d w r ite s (2 ins t ruc t i on c y c l e s ), b e c aus e on ly the buf fers are w r it- te n. a pro g ram m i ng c y c l e i s req u i r ed fo r p r ogra m m i n g ea c h r o w . 5 . 3 e n h a n c ed in - c ir c u it s e r i a l pro g ramm i n g en han ce d in-c i r cu it seri al pro g ra mm in g us es a n on -bo a rd b ootl o a der , kn ow n a s th e pr ogra m e x e c ut iv e, to m ana ge the prog ram m i n g pro c es s . u s ing an spi da t a f r am e fo rma t, th e pro g ra m e x ec ut ive ca n e r as e, pr ogra m and v e rif y prog ram m e m o ry . for mo re i n form at ion on en han ce d ic sp , se e th e dev i c e pr ogra m m i n g s pec if ica t io n. 5. 4 c ont rol regi ster s th ere are tw o sf r s us ed to read an d w r it e th e pr ogra m f l as h mem o r y : n v m c o n and nv m key . th e nvm c on re gi s te r (re g is ter 5 -1) c ont rols w h ic h bl oc ks are to be eras ed , w h ic h m e m o ry typ e is to b e pr ogra m m e d an d w h e n th e p r ogra m m i n g c y c l e st art s . n v mkey is a w r ite-only regis t er that is used for w r ite protecti on. t o st art a pr ogram ming or erase sequ ence, the use r mus t c onsec utively w r ite 55h and aa h to the nvmkey regis t er . refer to section 5 . 5 ? p r ogramming o p er ations? fo r further det ail s . 5. 5 p ro gramm i ng oper ati ons a co mp le t e pr o g r a mm in g se qu e n c e i s n e ce ss ar y fo r pr ogra m m i n g o r era s i ng the int e rna l f l as h i n r t sp m ode . d u ri ng a p r ogra m m i n g or era s e o p e r atio n, th e pr oce s s o r s t a lls (w ai t s ) unti l th e o pera t io n is fi nis h e d . se ttin g the wr bit (n vmc o n < 15 >) st art s the ope r a- ti on a nd th e wr bi t is a u to ma tic a ll y c l ea red w h en th e op era t io n is fi nis h e d . c on f ig urat ion w o rd va lu es a r e s t ore d in t he l as t tw o lo c a t i on s o f p r og r a m me mo r y . p e r f or mi n g a pa ge er a s e o p e r at i o n o n t h e l a s t pa ge of p r og r a m me mo r y c le a rs th es e va lu es a n d ena ble s c ode pro t ec tio n . as a res u l t , av oi d p e rfo r mi ng p a ge eras e ope rati ons o n t he las t p age of prog ram me mo ry . note: writing to a location multiple times wi tho ut e r as ing it is not rec o m m e nde d.
? 2010 microchip technology inc. ds39881d-page 51 pic24fj64 ga004 family reg i s t er 5- 1: nvm c o n : f l a sh me mory contro l regis t er r/so-0 r/w - 0 r /w -0 u-0 u -0 u-0 u -0 u-0 wr wren wrerr ? ? ? ? ? bi t 15 bi t 8 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ?erase ? ?n v m o p 3 (1 ) nvmo p2 (1 ) nvmop1 (1 ) nvmop0 (1 ) bi t 7 bi t 0 le gen d : so = set only bi t r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 wr : w r ite c ontr o l b i t 1 = i nit i ate s a fla s h m e mo ry pro g ram or e r as e ope rati on. the o pera t io n i s se lf-t im ed and th e bit is c l e ared by ha rdw a re on ce op erat ion is co mp le te. 0 = p r ogra m o r era s e op erat ion is co mp le te a nd i na c ti ve bi t 14 wr e n : w r ite enab le bit 1 = e n a b l e f l as h p r og ram/ era s e ope rati ons 0 = i nhi bit fla s h pro g ram / e r ase op erat ion s bi t 13 w r err: w r i t e sequ enc e e rror fl ag bi t 1 = a n im prop er pro g ra m or e r as e se que nc e att e m p t or te rmi nat ion has oc cu rred (b it is se t a uto ma tic all y on a ny se t a ttem pt of th e w r bit ) 0 = t he prog ram or e r as e o pera t io n c o m p l e ted no rma lly bi t 12 - 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6 erase: eras e/pro g ram en abl e b i t 1 = p e r form th e e r as e o pera t io n s pecifi e d by nv mo p3 :n vmo p 0 on t he next wr com m and 0 = p e r form th e p r ogr am ope rati on spe c i f ie d b y nv m o p3:n vm op 0 on the ne xt wr c o m m a n d bi t 5- 4 un im pl e m e n te d : r ead as ? 0 ? bi t 3- 0 nvm o p3:nvm o p 0: n v m o pera t io n se lec t b i t s (1 ) 11 11 = m e m o ry bu lk era s e ope rati on (erase = 1 ) or n o o pera t io n (erase = 0 ) (2 ) 00 11 = m e m o ry word pro g ram o pera t io n (erase = 0 ) o r no ope rati on (erase = 1 ) 00 10 = m e m o ry p a ge eras e ope rati on ( e r a se = 1 ) or no op erat ion (erase = 0 ) 00 01 = m e m o ry row prog ram op erat ion (erase = 0 ) or n o o pera t io n (erase = 1 ) note 1 : al l o t her co mb ina t io ns of n v m o p3:n vm o p 0 ar e un im ple m e n te d. 2: a v a ila ble in icsp? m o d e on ly . refer to d e v i c e pr ogra m m i n g s pec if ica t io n.
pic24fj64ga004 family ds39881d-page 52 ? 2010 microchip technology inc. 5.5 . 1 p rogra m m i ng al g o ri t h m for fl as h pr ogr a m m e m o r y t h e us er ca n p r o g ra m on e ro w o f fl as h pro g ra m mem o ry at a t i m e. t o do t h is , i t i s ne ce ssa r y t o e r a s e th e 8 - ro w e r as e b l o c k c o n t ai ni ng th e de si re d ro w . th e g e n e ra l pr oc es s is : 1 . r e a d ei gh t ro w s o f pr og ra m m e mo ry (5 12 i n st ru ct ion s ) a nd st or e in d a t a r a m. 2. u p d a t e t h e pr o g r a m da ta i n r a m w i t h t h e d e si red ne w dat a. 3. e r as e t h e b l o c k ( s e e e x am pl e 5 - 1 ) : a ) se t t he n v m o p bi t s (n vm c o n < 3:0 > ) to ? 0010 ? to con f ig ure f o r bloc k era s e . set th e erase ( n vm con<6> ) and wren (n vm c o n < 14> ) bi t s . b ) w r ite th e s t ar ting ad dre s s of the bl oc k to b e e r as ed i n to the tbl p ag an d w reg i s t ers . c ) w r ite 55 h to nv m key . d ) w r ite aah to nvm key . e) s e t t h e w r b i t ( n v m c o n < 15 > ) . t h e er a s e c y c l e beg ins an d the c p u s t a l l s f o r t h e d u r a - tion of t he e r ase cycle. when th e er ase is done, t h e w r b i t i s c l e a r e d a u t o m a t i c a l l y . 4. w r ite th e f i rs t 64 in st ruc t ion s from d a t a r a m in to th e prog ram m e m o ry b u f f ers (s ee ex am pl e 5 -1 ). 5. w r ite the pro g ra m b l oc k to f l as h m e m o ry : a) se t th e n v m o p bi t s to ? 0001 ? to c onf igu r e fo r row pro g ram m i ng . clea r the erase b i t an d s e t the wren bi t. b) w r ite 55 h to nv mke y . c ) w r ite aah to nvm key . d) se t th e wr b i t. the p r ogr a mm in g cy cl e be gi ns an d the c p u s t al ls fo r th e dura t io n of th e w r i t e c y c l e . w hen the w r i t e t o fl as h m e m o ry is d one , th e wr bi t i s cl eared au tom a t ica ll y . 6. r e p e a t st eps 4 an d 5, us in g t h e n e x t ava il a b le 6 4 i n s t r u c t i ons f r om t he bl oc k in da t a r a m by i n c r em e n ti ng the va lu e in tbl p a g , un til al l 51 2 i nst r uc t i o n s a r e w r it t e n ba ck t o f l ash me mor y . fo r pro t ec tio n a gai ns t a c c i de nt a l o pera t io ns , th e w r i t e i n iti a te s e qu enc e f o r nvm key m u s t be us ed to all o w an y era s e o r p r ogra m op era t ion t o proc ee d. af te r th e pr ogra m m i n g co mm an d ha s b een ex ec uted , the us er mu st w a it f o r t h e pr o g r a m mi ng ti me un t i l pr o g r am mi ng i s co mp let e. the t w o ins t ruc t i ons foll ow in g the s t a r t of th e p r og ram m i ng se que nce s hou ld be nop s, as s h ow n i n ex am ple 5 -3 . ex amp l e 5- 1: era s ing a program me mory block ; set up nvmcon for block erase operation mov #0x4042, w0 ; mov w0, nvmcon ; initialize nvmcon ; init pointer to r ow to be erased mov #tblpage(prog_addr), w0 ; mov w0, tblpag ; initialize pm page bo undary sfr mov #tbloffset(prog_addr ) , w0 ; initialize in-page ea [15:0] pointer tblwtl w0, [w0] ; set base address of e rase block disi #5 ; block all interrupts with priority <7 ; for next 5 instructio ns mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase seque nce nop ; insert two nops after the erase nop ; command is asserted
? 2010 microchip technology inc. ds39881d-page 53 pic24fj64 ga004 family e x am ple 5 - 2 : lo a d ing the w r ite buffe r s example 5-3: initiating a programming sequence ; set up nvmcon for row programming operations mov #0x4 001, w0 ; mov w0, nvmcon ; initialize nvmcon ; set up a pointer to the first program memory location to be writte n ; program memory se lected, and writes enabled mov #0x0 000, w0 ; mov w0, tblpag ; initialize pm page bo undary sfr mov #0x6 000, w0 ; an example program me mory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low _word_0, w2 ; mov #hig h_byte_0, w3 ; tblwtl w2, [w0] ; write pm low word int o program latch tblwth w3, [w0++] ; write pm high byte in to program latch ; 1st_program_word mov #low _word_1, w2 ; mov #hig h_byte_1, w3 ; tblwtl w2, [w0] ; write pm low word int o program latch tblwth w3, [w0++] ; write pm high byte in to program latch ; 2nd_program_word mov #low _word_2, w2 ; mov #hig h_byte_2, w3 ; tblwtl w2, [w0] ; write pm low word int o program latch tblwth w3, [w0++] ; write pm high byte in to program latch ? ? ? ; 63rd_program_word mov #low _word_31, w2 ; mov #hig h_byte_31, w3 ; tblwtl w2, [w0] ; write pm low word int o program latch tblwth w3, [w0] ; write pm high byte into program latch disi #5 ; block all interrupts with priority <7 ; for next 5 instructi ons mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequ ence nop ; 2 nops required afte r setting wr nop ; btsc nvmcon, #15 ; wait for the sequenc e t o be completed bra $-2 ;
pic24fj64ga004 family ds39881d-page 54 ? 2010 microchip technology inc. 5.5 . 2 p rogra m m i ng a s i ngle w o rd of fl a s h progra m m e m o ry if a fl as h loc ati on h as be en er ase d, it c an be p r o- g r am me d us ing t abl e w r ite ins t ruc t io ns to w r ite a n i n s t ruc t io n w o rd (2 4-b i t) into th e w r ite la tch . th e tb lp ag reg i s t er is l o a ded w i th the 8 m o s t sign ifi c a n t b y t e s o f t h e f l as h a d d r e ss. t h e tblwtl and tblwth in s t r u ct i o ns w r i t e t h e de si r e d da ta i n t o t h e w r i t e la t c h e s an d s pec ify the low e r 1 6 bi t s o f the prog ram mem o r y a d d r es s t o w r it e t o . t o co nf i g ur e t h e n v mc o n r e gi s t e r fo r a wo rd wri t e , se t th e nvm o p b i t s (nvmcon<3 : 0 > ) to ? 001 1 ? . th e w r i t e i s pe r f or m ed by ex ec ut i ng t he un lo ck s equ enc e and s etti ng the wr bit (se e ex am ple 5 -4 ). ex amp l e 5- 4: pro g ram ming a sin g l e w o rd of flas h pr o g ram me mory ; setup a point er to data program memory mov #tblpage(prog_ad dr), w0 ; mov w0, tblpag ;initialize pm pag e boundary sfr mov #tbloffset(prog_ addr), w0 ;initialize a regi ster with program memory address mov #low_word_n, w2 ; mov #high_byte_n, w3 ; tblwtl w2, [w0] ; write pm low wor d into program latch tblwth w3, [w0++] ; write pm high by te into program latch ; setup nvmcon for programming one word to data program memory mov #0x4003, w0 ; mov w0, nvmcon ; set nvmop bits t o 0011 disi #5 ; disable interrupts while the key sequence is written mov #0x55, w0 ; write the key se quence mov w0, nvmkey mov #0xaa, w0 mov w0, nvmkey bset nvmcon, #wr ; start the write cycle nop ; 2 nops required after setting wr nop ;
? 2010 microchip technology inc. ds39881d-page 55 pic24fj64 ga004 family 6 . 0 r es et s th e r e set mo dul e c o m b in es all r e s e t s o u r ces an d controls the device master reset signal, sysrst . th e fo ll ow in g is a lis t o f de vi ce r e s e t s o u r ce s: ? p or: po we r-o n re se t ?mclr : pi n re se t ?s w r : reset in s t r u ct i o n ? w d t : w a tch d o g t i m e r res e t ? b o r : bro w n-ou t r e s e t ? c m : c o n f ig urat ion mi sm at ch r e se t ? t r apr : t r ap c onf lic t r e s e t ? i opuwr: il l e g a l op co d e re se t ? u wr : u n in iti a li ze d w r egi ste r r e s e t a s i m p l i f i e d bl oc k di a g r a m of t h e r e se t mo d u l e is sh o w n i n f i gu r e 6 - 1. any active source of reset will make the sysrst s i gn al ac tiv e . m any regi ste r s as so ci ate d w i th the c p u an d pe riph era l s a r e forc ed t o a kn ow n r e s e t s t at e. m o s t re gis t er s are una f f e c t ed by a r e s e t; the i r st a t us i s un kn ow n on p o r a nd unc ha nge d b y a ll othe r r es et s . all ty pes of d e v i ce r e s e t w i l l s e t a c o rre sp ond in g st atu s bi t in the rco n regi ste r t o ind i c a te th e typ e of res e t (s ee r e g i s t er 6-1). a pow e r-on r e se t w i ll c l e a r all bit s ex c ept fo r the bo r an d po r b i t s (r c o n < 1 :0> ) w h ic h ar e se t. th e us er m ay s et o r cle ar an y b i t at a n y tim e du rin g c ode ex ec utio n. t he r c o n bi t s onl y s e rv e a s sta t us bi ts. s e t t i ng a pa r t i c ul ar r e s e t sta t us bi t in so ft war e wil l n o t c a u s e a de vi ce re se t t o oc cu r . th e r c o n re gis t er al so ha s o t he r bi t s as so ci ate d w i th th e w a tch dog t i m er and de vi ce pow e r-sa v i ng st a t es . th e fun c ti on of th es e b i t s is di sc us se d in oth er se cti o n s of thi s m a n u a l . figure 6-1: res e t sy ste m block diagram note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 7. reset? (ds39712). note: r e f e r to th e s p e c i f ic pe riph era l o r c p u s e c t ion o f this ma nua l for regi st er r e se t sta t es . note : the status bit s i n the r c o n regi st er s hou ld be c l e a red a f ter th ey are re ad s o th at t he nex t r c o n re gis t er va lue af ter a de vi ce re s e t w i ll be m e a n i ngfu l . mclr v dd v dd ri s e detec t por sl eep or i dl e b r own-out r e se t enable v olt age regulat or reset i n st ruct ion wdt module gl itch filter bor trap conflict illegal opcode uninitializ ed w regis t er sysrst c onf iguration mismatch
pic24fj64ga004 family ds39881d-page 56 ? 2010 microchip technology inc. regis t er 6-1: rcon: re se t control regis t er (1 ) r/w -0 r /w -0 u-0 u -0 u-0 u -0 r/w -0 r /w -0 tr ap r i o p u w r ? ? ? ?c m v regs bit 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 r/w - 1 r /w -1 ext r s w r swdten (2 ) w d to sleep idle bor p or bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = un im pl em ent ed b i t, rea d as ? 0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bit is cl eare d x = bit is unk no w n bi t 15 trapr: t r ap re s e t f l ag bi t 1 = a t r ap c o nfl i c t re s e t h a s oc cu rred 0 = a t r ap c o nfl i c t re s e t h a s no t oc cu rred bi t 14 io puw r : i l le ga l op co de or un in i t ia li z e d w a c ce ss r e s e t f l a g b i t 1 = a n ill ega l op co de de tec t io n, an i l l ega l add res s m ode o r uni nit i al iz ed w re gis t er u s ed a s an addre s s poi n te r ca us ed a r e s e t 0 = a n il le gal op cod e o r un ini t ia liz ed w r e se t has n ot o c c urre d bi t 13 - 1 0 u n i m pl e m en t e d: rea d as ? 0 ? bi t 9 cm : co nfig ura t io n w ord mi sm atc h r e se t fl ag b i t 1 = a c o nfi gura t io n w o rd mi sm atch r e se t ha s occu rre d 0 = a c o nfi gura t io n w o rd mi sm atc h r e se t ha s not oc curr ed bi t 8 vreg s : v o lt age re g u la tor s t a ndb y en ab le b i t 1 = r e g u l a tor rem a in s act i v e du rin g sl eep 0 = r e g u l a tor goe s to s t an dby d u rin g sl eep bi t 7 extr: ex tern al re se t (m clr) pi n bi t 1 = a m a s t er clea r (pi n ) re s e t ha s o c c u rre d 0 = a m a s t er clea r (pi n ) re s e t ha s n o t o c c u rre d bi t 6 swr : sof t w a re re s e t (in s t r uc tion ) fl ag bit 1 = a re set in stru ct ion has b een ex ec ute d 0 = a re set in stru ct ion has n o t b een ex ec ute d bi t 5 swdten : so f t w a re ena b le /d is abl e o f wd t bit (2 ) 1 = w d t is en abl ed 0 = w d t is di sa ble d bi t 4 wdt o : w a t c hd og t i me r t i me - o ut f l a g b i t 1 = w d t tim e -o ut h a s oc c u rred 0 = w d t tim e -o ut h a s no t oc cu rred bi t 3 sleep : w a ke from sl eep fla g b i t 1 = d e v i c e has be en in sl ee p m ode 0 = d e v i c e has no t be en in slee p m o d e bi t 2 idle : w a ke- up f r om idl e f l ag bi t 1 = d e v i c e has be en in i d le m ode 0 = d e v i c e has no t be en in idle m ode bi t 1 bo r : b r ow n - ou t re se t f l ag bi t 1 = a br ow n-o u t r e set ha s o c c u rre d. n o te th at bor i s als o s e t af te r a p o w e r-o n r e s e t . 0 = a br ow n-o u t r e set ha s n o t o c c u rre d bi t 0 po r : p o we r-o n re se t fl a g b i t 1 = a po w e r-u p r e s e t has oc c u rred 0 = a po w e r-u p r e s e t has no t o c c u rred note 1 : al l o f t he r e s e t s t a t us bi t s m a y be s e t or c l e a re d i n s o f t w a re. set t in g o ne of the s e bi t s in s o f t w a re d o e s not c aus e a de vi ce re s e t. 2: if the fwd t en c onfi g u r ati on b i t i s ? 1 ? (unprogr am med ) , th e w d t is al w a y s e nab le d, re gardl es s of t h e sw d t en bi t se tti ng.
? 2010 microchip technology inc. ds39881d-page 57 pic24fj64 ga004 family t able 6 - 1 : res e t fl a g bit ope ration 6. 1 c l o ck sour ce select io n at reset if clock s w itc h ing is enabled, the s ystem c l ock source at dev ice r es et is chos en as show n i n t abl e 6-2. if clo c k s w itc h ing is disab led, the s ystem c lock sou r c e i s alw a ys selected according to the osci llator c onfiguration bit s . refer to section 8 .0 ?o scillato r configur ation? for further det ails . t able 6 - 2 : oscillator s e le ction vs . t y p e of re se t (clock sw itchin g enab l e d) 6. 2 d evi ce res e t t i mes th e r e s e t tim e s for va r i ou s t y pe s o f de vi ce r e s e t a r e s u m m a r iz ed in t abl e 6 -3. n o te th at the s y s t e m r e s e t s i gn al , sysrst , i s r e l e a s ed a fte r t h e p o r an d p w r t de la y ti me s exp i r e . t he ti me th a t t h e de v i c e ac t ua l ly b e gi n s to ex ec ut e c ode w i l l als o dep end on th e s y s t em o s c i l l at or d ela ys , w h i c h inc l u de th e o s c ill ato r s t art-u p t i m e r (o st) an d th e pll loc k t i m e . th e o s t an d pll l o c k ti me s o c c u r i n p a r al lel with the ap pli c a b le sysrst d e l a y tim e s . th e fsc m d e l a y d e ter m i n es the ti me at w h ic h th e fsc m beg in s to m on i tor t he s y s t em cl ock so urc e af t er th e sysrst signal is released. flag bit s e tting e vent c lea r ing even t trapr (rc o n<1 5 >) t r a p con f li c t ev ent por io pu wr ( r c o n < 1 4 >) il leg a l op co de or u n i n i t ial i z ed w r e g i s t er a cces s po r c m (r c o n < 9>) c on fig u rat i on m i sm at ch r e s e t p o r ext r (rco n<7 > ) m cl r re se t p or sw r (rco n<6 > ) reset i n st r u ct i o n p or w d t o (rcon < 4 > ) w dt t i me -o u t pwrsav in st ruc t ion , po r sl eep (rcon < 3>) pwrsav #sleep in str u ct ion p o r idl e (rco n < 2>) pwrsav #idle in str u cti o n p o r bor (rcon<1 > ) p or, bor ? por (rcon<0 > ) p or ? note: all reset flag bits may be set or cleared by the user software. reset type clock sourc e dete rmina n t p o r f n o s co nf i g u r at i o n b i ts (cw2 <10 :8>) bor mc l r cosc contro l b i t s (o sc c o n < 14: 12> ) wd to swr
pic24fj64ga004 family ds39881d-page 58 ? 2010 microchip technology inc. t a ble 6 - 3 : res e t delay t i me s for v ari o u s de v i ce res e t s res e t t y pe clo ck source sysrst dela y sy stem c l oc k de l a y fscm de la y note s po r e c, frc, frcdiv , l p rc t po r + t st ar t u p + t rs t ?? 1, 2, 3 ecpl l, frcpll t po r + t st ar t u p + t rs t t lo ck t fs c m 1, 2, 3 , 5 , 6 xt , hs, so s c t po r + t st ar t u p + t rs t t os t t fs c m 1, 2, 3 , 4 , 6 xt pll, hspll t po r + t st ar t u p + t rs t t os t + t lo ck t fs c m 1, 2, 3 , 4 , 5, 6 bo r e c, frc, frcdiv , l p rc t st ar t u p + t rs t ?? 2, 3 ecpl l, frcpll t st ar t u p + t rs t t lo ck t fs c m 2, 3, 5 , 6 xt , hs, so s c t st ar t u p + t rs t t os t t fs c m 2, 3, 4 , 6 xt pll, hspll t st ar t u p + t rs t t os t + t lo ck t fs c m 2, 3, 4 , 5 , 6 mclr an y c l oc k t rs t ?? 3 wdt a n y c l oc k t rs t ?? 3 sof t wa re an y c l o c k t rs t ?? 3 ille ga l o pc ode an y c l oc k t rs t ?? 3 u n in itia li ze d w a n y c l oc k t rs t ?? 3 t r ap c o nfl i c t an y c l oc k t rs t ?? 3 no t e 1 : t po r = power-o n re s e t de lay (10 ? s nom in al). 2: t st ar t u p = t vr eg (10 ? s n o m i na l) if on -ch i p regu lat o r i s e nab led or t pw r t (64 ms no mi nal ) if on-ch i p regu lat o r i s d i s abl ed. 3: t rs t = i n tern al st ate r e se t ti me . 4: t os t = os ci lla tor s t a r t-up t i m e r . a 10 -bi t c oun ter c o u n t s 10 24 osc i l l at or p e rio d s be fore releas ing th e osc i l l at or c l o c k to the sy ste m . 5: t lo ck = pl l l o ck ti me (2 m s no mi nal ). 6: t fs c m = fai l -saf e c l o c k m oni tor del ay .
? 2010 microchip technology inc. ds39881d-page 59 pic24fj64 ga004 family 6.2 . 1 p or a nd long o s cil l ator st a r t - u p t i m e s th e os ci lla tor st art-u p ci rcui try a nd it s as soc i a t ed d ela y time rs are not lin ke d to the de vi ce r e s e t d e la ys th at o c c u r at powe r-up . so m e c r y s t a l c i rc ui t s (es p e c ia ll y l o w - fre que nc y c r ys t a l s ) w ill ha ve a rel a ti ve ly lon g s t art - up tim e . th ere f ore , o ne or m o re of th e foll ow in g c ond iti ons i s p o s s ib le af t e r sysrst is rel eas ed: ? t h e o s c i l l ato r c i rc uit has no t b egu n to os ci lla te. ? t h e os c ill ato r s t art - up t i m e r ha s not ex pi red (i f a c r ys t a l os c ill ato r is us ed) . ? t he pll has not achie v ed a loc k (if p l l i s used). th e de vic e w i l l no t b egi n to ex ec ute c od e unt il a v ali d c l o c k s ou r ce has bee n rel ea s ed to th e sy s t em . the r e- fo re, the oscillator and pll s t art - up del ay s m u s t b e c ons id ere d w h e n th e r e set del ay tim e mu st b e k n o w n . 6 . 2. 2 f a i l- saf e c l o c k mo n i to r (f s c m) a nd d e v i ce res e t s if the f s c m i s e nab led , it w i ll beg in t o m oni tor th e s y s t em c l oc k s o u r c e wh en sysrst is re lea s e d . if a v al i d c l oc k s ou r ce is not a v a ila ble at th is tim e, th e d evi ce w i ll a uto ma tic all y s w itc h to th e frc os cil l a t or a nd th e us er ca n sw it ch to the de si red c r ys t a l os cil l a t or i n th e t r a p se rvi c e r outi n e . 6.2 . 2.1 f scm del a y fo r c r y s t al and pll cl ock s our c e s wh en t he s y s t em cl oc k s ourc e is prov i ded b y a c r y s t a l os c ill ato r a nd/ or the pll , a sm all d el ay , t fs c m , wil l au tom a t i ca ll y be i n s e rted af te r t h e po r a n d pw r t de la y tim e s . the f s c m w i l l not b e gi n to m oni tor th e sy st e m c l oc k s o ur c e un t i l t h is d e l a y ex pi r e s. t h e f s c m de la y ti me is no mi nal ly 100 ? s a nd prov id es add iti o na l ti me fo r th e o s c i l l ato r a nd/o r pl l t o s t ab il iz e. i n m o s t c a s e s , the fsc m d e l a y w i ll prev en t an o s c i l l at or fa ilu re tra p a t a dev ic e r e set when the pwr t is d i sa bl ed. 6. 3 s pecia l functi on r e gist er reset s t ates mo st of t h e s p e c i a l fu nc ti o n r e gi st er s ( s f r s ) ass o c i - a t ed w i t h th e pi c 2 4 f c p u an d p e ri ph era l s ar e re se t to a p a rt ic ul ar va lu e at a de vi ce r e se t. th e s f r s ar e g r ou pe d by t h e i r pe rip h e r al o r c p u fu nc ti on a n d th ei r r e se t v al ue s ar e s pe c i f ie d i n ea c h s ec t io n o f th is m a nu al . th e r e s e t va lue for ea ch sfr do es n o t de pen d on th e ty pe of r e s e t , w i th the ex c epti on of fo ur r egi ste r s. th e re se t va l u e fo r th e re s e t co n t ro l re g i ste r , rcon, wi l l de pe nd on the ty pe of d ev i c e r e set . th e r e se t v alu e fo r th e os ci l l a t o r co n t ro l re g i s t e r , osccon, wi l l de pe nd on the ty pe of r e se t an d t he prog ram m e d v a lu es of th e fn o s c bi t s i n th e c w 2 r egi ste r (se e t abl e 6 -2). the r c f g c al a nd n v mc o n re gis t ers a r e on ly af fec t ed by a por .
pic24fj64ga004 family ds39881d-page 60 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 61 pic24fj64 ga004 family 7.0 i nter rup t co n t roller th e pi c 24f int e rrup t c ont roll er re duc es th e n u me rou s p e rip hera l in terru pt req ues t si gna ls t o a si ngl e in terru pt re que st sig nal to the p i c 24f c p u . it h a s the foll ow in g fe atu r es : ? u p t o 8 p r oc es so r ex ce p t i o ns an d s o ft w a r e t r a p s ? 7 us er-s ele c t abl e p r iori ty lev e l s ? i n t erru pt v e c t or t a b l e ( i vt) w i th u p to 1 18 ve cto r s ? a u n i que ve cto r fo r eac h inte rrup t or ex cep t io n s our ce ? f i x e d p r iori ty w i th in a s pec ifi ed us er p r iori ty lev e l ? a l tern a te inte rrup t v e c to r t a ble (aivt) for d e b ug s upp ort ? fi x e d i n te rrupt ent ry a nd retu rn l a ten c i e s 7. 1 i nter rupt v e c t or t a bl e th e in terru pt v e ct or t abl e (ivt ) is sh ow n i n f i gu re 7 - 1. t h e i v t r e s i d e s in pr o g r a m me m o r y , s t ar t i ng at lo ca t i on 0 000 04h . th e ivt c on t ai ns 126 ve cto r s, con s i s ti ng of 8 non -ma s k ab l e trap v ec t ors , p l us u p t o 1 1 8 s ou r ce s of i n ter r upt. i n ge nera l , ea ch i n te rrup t s o u r ce has it s ow n v e c t or . ea ch in terru pt ve cto r c o n t ai ns a 24 -bit w i d e a ddre s s . th e va lue prog ram m e d i n to e a c h in terru pt v e c t or l o c a tio n is th e st arti ng a ddre s s of th e a s s o c i ate d in terru pt s e rv i c e rou t ine (isr). in terru pt ve cto r s are pri o ri tiz ed in te rms o f t hei r na tura l p r iori ty ; t his i s li nk ed to th eir p osi tio n in th e ve cto r t abl e. al l o t her thi ngs be ing eq ual , lo w e r a ddre s s e s ha ve a h i gh er n a tu ral pri o rity . fo r ex am pl e, t he int e rrup t a s s o - c i a t ed w i th v e c t or 0 w i l l t a ke pri o rit y o v er int e rrup t s at a n y oth e r v e c t or a ddr ess. pic 2 4fj 6 4 g a0 04 fam i l y de vi ces im ple m e n t non-m a s k a b l e tra p s an d u n iq ue in terru pt s . th es e a r e s u m m a r iz ed in t a b l e 7 -1 and t a ble 7 -2 . 7.1 . 1 a l t erna te interr upt v e ctor ta b l e th e alt e rna t e in terr upt v e ct or t abl e (aivt ) is loc a te d af ter the ivt , as s h o w n i n fi gu re 7- 1. ac c e ss t o th e aivt is p r ov id ed by th e al t i vt c o n t rol b i t (in t c o n 2 < 15> ). if th e al tivt bit is s e t , all in terru pt an d exc ep t io n p r oc es ses w i ll us e t he alte rna t e v e c t or s i n st ead of t he defa u lt ve cto r s. the al tern ate vec t o r s a r e or gan iz ed in t he s a m e m a n n e r as the de faul t v e c t ors . th e aivt s u p port s em ul ati on an d de bug gi ng ef for t s b y pr ovi d i ng a mea n s to s w itc h betw e en an ap pl ica t io n an d a s u p por t env iro n m e nt w i tho u t re qui rin g the int e r- ru pt v e ct ors t o be re pro g ram m ed. t h is fea t ure a l s o en ab les s w itc h i ng be tw een a ppl ic ati ons f o r e v a l ua tio n of di f f e r ent so f t w a re a l go rithms at run tim e . if t h e aivt i s n o t n eed ed, the aivt s h o u ld be prog ram m e d w i th th e s a m e a ddre s s e s us ed in the ivt . 7. 2 r eset sequ ence a dev ic e r es et is no t a t r ue ex ce pti on bec au se th e i n terr upt c o n t rol l er is not inv o l v ed in the r e se t pr oce s s . t h e p i c2 4f de vi ce s cl e a r th e i r r e g i st e r s i n r e sp on se t o a res e t wh ic h f o rce s the pc to z e ro. the m i c r o- c ont roll er the n be gin s pro g ram ex ec utio n at l o ca tio n 00 00 00h. the us er p r ogram s a g oto in str u cti o n at th e r e s e t ad dres s, w h i c h red i rect s p r ogra m ex ec utio n to th e a ppro p ria t e st a r t-up rou t in e. note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 8. interrupts? (ds39707). note: any unimplemented or unused vector locations i n the ivt a nd aivt s h ou ld be pr ogra m m ed w i th th e add r es s o f a def aul t in terr upt han dl er ro uti ne tha t c ont ain s a reset i n st r u ct io n .
pic24fj64ga004 family ds39881d-page 62 ? 2010 microchip technology inc. figure 7-1: pi c24f i n t e rrup t v e cto r t a ble t a ble 7 - 1 : t rap v e cto r det a ils v e c t or num b er ivt add r e s s a ivt addres s t rap so urce 0 0 0 000 4h 0 001 04 h r es erv e d 1 00 000 6h 0 001 06 h o sc ill ato r fa ilu re 2 0 0 000 8h 0 001 08 h a dd res s erro r 3 0 0 000 ah 000 10ah s t a c k erro r 4 0 0 000 c h 000 10c h m a t h error 5 0 0 000 eh 000 10eh r es erv e d 6 0 0 001 0h 000 1 10h r e s e rv ed 7 0 0 001 2h 0 0 0 1 1 72h r e s e rv ed res e t ? goto i n st ruct ion 0 00000h res e t ? goto addres s 0 00002h res e rved 000004h o s cill a t or f a i l t r ap v e ct or addr ess err o r t r ap v e c t or s t ack er ror t r ap v e c t or m a t h erro r t r ap v e ct or res e rv ed res e rv ed res e rv ed i n t e rr upt v e ct or 0 0 00014h i n t e rr upt v e ct or 1 ? ? ? i n t e rrupt v e ct or 52 00007ch i n t e rrupt v e ct or 53 00007e h i n t e rrupt v e ct or 54 000080h ? ? ? i n t e rrupt v e ct or 1 1 6 0 000f ch i n t e rrupt v e ct or 1 1 7 0 000f eh res e rved 000100h res e rved 000102h res e rv ed o s cill a t or f a i l t r ap v e ct or addr ess err o r t r ap v e c t or s t ack er ror t r ap v e c t or m a t h erro r t r ap v e ct or res e rv ed res e rv ed res e rv ed i n t e rr upt v e ct or 0 0 001 14h i n t e rr upt v e ct or 1 ? ? ? i n t e rrupt v e ct or 52 00017ch i n t e rrupt v e ct or 53 00017e h i n t e rrupt v e ct or 54 000180h ? ? ? i n t e rrupt v e ct or 1 1 6 i n t e rrupt v e ct or 1 1 7 0 001f eh s t art of code 000200h dec r easing natural order priority inte r r u pt v e c t o r t a b l e ( i vt ) (1 ) al tern ate i n terru p t v ecto r t a b l e (ai v t ) (1 ) not e 1: see t able 7 - 2 f o r t he i n t e rru pt vect or l i st .
? 2010 microchip technology inc. ds39881d-page 63 pic24fj64 ga004 family t able 7 - 2 : imp l em ente d inte rrup t v e c t ors interrupt source v ecto r nu mb er iv t a d dr e s s aiv t a d d r ess int e r r u pt b i t loc a t i ons fl a g ena b le p r io r i t y a dc1 convers i on done 13 00002 eh 00 012eh i f s 0<13> i e c0<13> i p c3<6: 4 > c o mp ara t or ev ent 18 000038h 000138h i f s 1 <2> i ec1<2> i p c4<10: 8> c rc g enera t or 67 00009 ah 00 019ah i f s 4<3> i e c4<3> i p c 16<14: 12> e xt e rnal i n t e rrupt 0 0 000014h 0001 14h i f s 0<0> i e c0<0> i pc0<2: 0> e xt e rnal i n t e rrupt 1 2 0 0 0003ch 00013ch i f s 1<4> i e c1<4> i pc5<2: 0> e xt e rnal i n t e rrupt 2 2 9 00004 eh 00 014eh i f s 1<13> i e c1<13> i p c7<6: 4 > i 2 c1 mas t er ev ent 17 000036h 000136h i f s 1 <1> i ec1<1> i p c4<6: 4 > i 2 c1 slave ev ent 16 000034h 000034h i f s 1 <0> i ec1<0> i p c4<2: 0 > i 2 c2 mas t er ev ent 50 000078h 000178h i f s 3 <2> i ec3<2> i p c12<10: 8> i 2 c2 slave ev ent 49 000076h 000176h i f s 3 <1> i ec3<1> i p c12<6: 4> i nput capt ure 1 1 000016h 0001 16h i f s 0<1> i e c0<1> i pc0<6: 4> i nput capt ure 2 5 00001 eh 0001 1e h i f s 0<5> i e c0<5> i pc1<6: 4> i nput capt ure 3 3 7 00005 eh 00 015eh i f s 2<5> i e c2<5> i pc9<6: 4> i nput capt ure 4 38 000060h 000160h i f s 2<6> i ec2<6> i p c9<10: 8> i nput capt ure 5 39 000062h 000162h i f s 2<7> i ec2<7> i p c9<14: 12> i nput change not i f i cat i on 19 00003 ah 00 013ah i f s 1<3> i e c1<3> i pc4<14: 12> o ut put com p are 1 2 000018h 0001 18h i f s 0<2> i e c0<2> i p c 0<10: 8 > o ut put com p are 2 6 000020h 000120h i f s 0<6> i ec0<6> i p c1<10: 8> o ut put com p are 3 25 000046h 000146h i f s 1<9> i ec1<9> i p c6<6: 4> o ut put com p are 4 26 000048h 000148h i f s1<10> i e c1<10> i p c6<10: 8> o ut put com p are 5 41 000066h 000166h i f s 2<9> i ec2<9> i p c10<6: 4> p a rallel m a st er p o rt 45 00006 eh 00 016eh i f s 2<13> i e c2<13> i p c1 1<6: 4> r eal - t ime clock/ calendar 62 000090h 000190h i f s3<14> i e c3<13> i p c15<10: 8> s p i 1 e rror 9 000026h 000126h i f s 0 <9> i ec0<9> i p c2<6: 4 > s p i 1 e vent 10 000028h 000128h i f s0<10> i e c0<10> i p c2<10: 8> s p i 2 e rror 3 2 000054h 000154h i f s 2 <0> i ec0<0> i p c8<2: 0 > s p i 2 e vent 33 000056h 000156h i f s 2<1> i ec2<1> i p c8<6: 4> t i m e r1 3 00001 ah 0001 1a h i f s 0<3> i e c0<3> i pc0<14: 12> t i m er2 7 000022h 000122h i f s 0<7> i ec0<7> i p c1<14: 12> t i m e r3 8 000024h 000124h i f s 0 <8> i ec0<8> i p c2<2: 0 > t i m e r4 27 00004 ah 00 014ah i f s 1<1 1 > i ec1<1 1 > i pc6<14: 12> t i m er5 28 0 0004ch 00014ch i f s 1<12> i e c1<12> i p c7<2: 0> u a r t 1 e rror 65 000096h 000196h i f s 4 <1> i ec4<1> i p c16<6: 4> u a r t 1 rec e iver 1 1 00002 ah 00 012ah i f s 0<1 1 > i ec0<1 1 > i pc2<14: 12> u a r t 1 t r ansm i t t er 12 0 0002ch 00012ch i f s 0<12> i e c0<12> i p c3<2: 0> u a r t 2 e rror 66 000098h 000198h i f s 4 <2> i ec4<2> i p c16<10: 8> u a r t 2 rec eiver 30 000050h 000150h i f s1<14> i e c1<14> i p c7<10: 8> u a r t 2 t r ansm i t t er 31 000052h 000152h i f s1<15> i e c1<15> i p c7<14: 12> l v d low -v olt age det e ct 72 0000a 4h 000124h i f s 4 <8> i ec4<8> i p c17<2: 0>
pic24fj64ga004 family ds39881d-page 64 ? 2010 microchip technology inc. 7. 3 i nter rupt cont rol a nd s t atus regi ste r s th e pic 24 f j 64g a00 4 fam i l y of de vi ce s im pl em ent s a to t a l of 28 regi ste r s for th e i n te rrupt co ntro lle r: ? i nt c o n1 ? i nt c o n2 ? i f s 0 th rou gh i fs4 ? i ec 0 thro ug h iec 4 ? i pc 0 thro ug h ipc 1 2, ip c 1 5, ipc 16 and ipc 1 8 g l o bal i n terr upt co ntrol f unc tio n s ar e c o n t roll ed fro m i n tc on 1 a nd in t c o n 2. in tc o n 1 co n t a i ns t h e i nt e r - ru p t ne sti n g di s a b l e (nstdis) b i t, a s we l l a s th e c ont rol a nd s t at us f l ag s fo r the p r oc es sor t r ap s our ces . th e i n t c on 2 reg i st er c ont rols th e e x te rnal in terru pt re que st s i gn al be hav io r a nd th e u s e o f t he alte rna t e in terru pt v e c tor t a b l e. th e i f sx regi st ers ma in t a in al l o f th e i n te rrup t req ues t fl ags . eac h s ourc e of i n te rrupt h a s a s t at us b i t w h i c h i s s e t by th e re sp ec tive peri phe ral s , or ext e rna l si gna l, a nd i s cl eare d v i a so f t w are . th e i e c x re gist er s m a i n t a in a l l of t he inte rrup t en abl e b i t s . th es e c ontro l b i t s are us ed to i ndi vi dua lly en abl e i nter r upt s fr om the per iph eral s o r ex ter nal si gna ls . th e ipcx reg i st ers are u s e d to s e t the i n terr upt pri o rit y le ve l fo r ea c h so u r ce of in t e rr u p t . e a ch us er i n t e r r u p t s our ce ca n be as si gn ed t o on e o f ei gh t pri ority l ev els . th e i n te rrupt so urc e s are as si gne d to the ifsx , i e c x an d ipc x reg i st ers in th e s ame se que nc e tha t the y a r e l i st ed in t abl e 7 - 2 . for ex am ple , th e in t0 (ext erna l in terru pt 0 ) is s how n as ha vi ng a v e ct or n u m ber a n d a na tura l ord e r p r io rity o f 0 . thus , the int 0 if st atu s bit i s fo und i n ifs0< 0 >, th e int0ie en ab le bi t i n iec0<0 > an d the int0 ip<2 :0> pri o rit y bit s in the fi rst po si tio n of ipc 0 (ipc 0< 2:0 > ). al thou gh th ey a r e not s pec ifi c a lly p a rt o f th e in terru pt c ont rol h a rd w a re, tw o of the c p u con t rol reg i s t ers co n- t a in bi t s th at co ntro l inte rrup t f unc tio nal ity . th e alu st a t u s re gis ter (sr ) c o n t ai ns the ipl 2 :ipl 0 bit s ( s r < 7: 5 > ) . t h es e i n d i ca t e t h e c u r r e nt c p u i n t e r r u p t pr iori ty le ve l. the u s e r m a y c h a n ge th e cu rrent c p u pr iori ty lev e l by wr iti n g to t he i p l b i t s . th e c o r c o n regi st er co nt ai ns t he ipl 3 bit , w h ic h to get her w i t h ipl2 :ipl0 , a l s o in dic a te s th e cur r ent c p u pr iori ty lev e l . ipl 3 is a re ad -onl y bit so th at t r ap ev ent s ca n n o t be ma sk ed by th e us er so ft w a r e . a l l in t e r r u p t r e gi st e r s a r e de s c r i be d i n r e gi st e r 7- 1 th rough r e gis t er 7-29, i n th e fo llo w i ng p a ges .
? 2010 microchip technology inc. ds39881d-page 65 pic24fj64 ga004 family regis t er 7-1: s r : a l u st a t us regis t er ( i n cp u) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 ? ? ? ? ? ? ?d c (1 ) bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ipl 2 (2 , 3 ) ipl 1 (2 , 3 ) ip l 0 (2 , 3 ) ra (1 ) n (1 ) ov (1 ) z (1 ) c (1 ) bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 7- 5 ip l 2 : i pl 0 : c p u i n ter r upt prio rity le vel s t atu s bit s (2 , 3 ) 11 1 = c p u i n te rrupt pri o rity l e v e l i s 7 (15 ) . u s er i n te rrupt s d i s abl ed. 11 0 = c p u in t e r r u p t p r io r i t y le ve l is 6 ( 1 4) 10 1 = c p u in t e r r u p t p r io r i t y le ve l is 5 ( 1 3) 10 0 = c p u in t e r r u p t p r io r i t y le ve l is 4 ( 1 2) 01 1 = c p u i n te rrupt pri o rity l e v e l i s 3 (1 1) 01 0 = c p u in t e r r u p t p r io r i t y le ve l is 2 ( 1 0) 00 1 = c p u in t e r r u p t p r io r i t y le ve l is 1 ( 9 ) 00 0 = c p u in t e r r u p t p r io r i t y le ve l is 0 ( 8 ) note 1 : s e e r e gi st e r 3- 1 fo r t h e de sc r i p t i o n of t h e r e m a in in g bi t ( s) t h a t ar e no t de di c a t e d t o i n te r r u pt co n t r o l fu nc tio n s. 2: th e i p l bi t s are co nc aten ate d w i th th e ip l3 b i t ( c o r c o n < 3> ) to form the c p u in terru pt prio rity le ve l. th e v a l ue in p a re nthe se s i n d i ca tes th e interr upt prio rity le ve l i f ipl 3 = 1 . 3: the ipl status bits are read-only when nstdis (intcon1<15>) = 1 . regis t er 7-2: corcon: cp u control regis t er u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 u-0 r/c-0 r/w-0 u-0 u-0 ? ? ? ?ipl3 (2) psv (1) ? ? bi t 7 bi t 0 le gen d : c = cl e a ra b l e b i t r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 3 ip l 3 : c p u inte rrupt prio rity le ve l s t at us bit (2 ) 1 = cpu i n terr upt prio rity le ve l i s g r ea ter th an 7 0 = c p u i n terr upt prio rity le ve l i s 7 or les s note 1 : se e r e g i s t er 3 - 2 f o r th e d e s c ri ptio n o f th e re mai n i ng b i t(s ) th at a r e n o t d e d i ca ted to int e rrup t c ont rol fu nc tio n s. 2: the ipl3 bit is concatenated with the ipl2:ipl0 bits (sr<7:5>) to form the cpu interrupt priority level.
pic24fj64ga004 family ds39881d-page 66 ? 2010 microchip technology inc. regis t er 7-3: intcon1: in t e rrup t control re g i ste r 1 r/w - 0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 nstdis ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 ? ? ? matherr addrerr stkerr oscfail ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 nst d is: in terru pt n e sti ng d i sa ble bi t 1 = in terru pt n e s t in g is d i sa bl ed 0 = in terru pt n e s t in g is e nab led bi t 14 - 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4 ma therr: a r i t hm et i c e r r or t r a p s t a t us bi t 1 = o v e r flo w trap ha s o c c u rre d 0 = o v e r flo w trap ha s n o t o c c u rre d bi t 3 addrerr: ad dres s error t r ap s t a tus bi t 1 = ad dres s error trap has o c c u rred 0 = ad dres s error trap has n o t o c c u rre d bi t 2 st kerr: s t ac k erro r t r ap s t atu s b i t 1 = s t ac k error trap ha s o c c u rre d 0 = s t ac k error trap ha s n o t o c c u rre d bi t 1 oscf ai l: o s c i l l at or fa ilu re t r a p s t a t us bi t 1 = o s c i l l at or fa ilu re t r ap has oc cu rred 0 = o s c i l l at or fa ilu re t r ap has no t oc c u rred bi t 0 un im pl e m e n te d : read as ? 0 ?
? 2010 microchip technology inc. ds39881d-page 67 pic24fj64 ga004 family regis t er 7-4: intcon2: in t e rrup t control re g i ste r 2 r/w - 0 r -0 u-0 u -0 u-0 u -0 u-0 u -0 altivt disi ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? i nt2 e p i nt1 e p i nt0 e p bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 al ti vt : en abl e al tern ate int e rrup t v e cto r t a bl e bi t 1 = u s e al terna t e inte rrupt v e c t or t a ble 0 = u s e s t an dard (de f au lt) v e c t or t a b l e bi t 14 di si: disi i nst ruc t io n s t atu s bit 1 = disi i n st r u ct i o n is ac ti ve 0 = disi i n st r u ct i o n is no t a c ti ve bi t 13 - 3 un im pl e m e n te d : read as ? 0 ? bi t 2 i n t2ep: ex te rnal int e rrup t 2 edge dete ct pola rity se lec t b i t 1 = in terru pt o n n ega tiv e e dge 0 = in terru pt o n p o s i tiv e edg e bi t 1 i n t1ep: ex te rnal int e rrup t 1 edge dete ct pola rity se lec t b i t 1 = in terru pt o n n ega tiv e e dge 0 = in terru pt o n p o s i tiv e edg e bi t 0 i n t0ep: ex te rnal int e rrup t 0 edge dete ct pola rity se lec t b i t 1 = in terru pt o n n ega tiv e e dge 0 = in terru pt o n p o s i tiv e edg e
pic24fj64ga004 family ds39881d-page 68 ? 2010 microchip technology inc. regis t er 7-5: ifs0 : interr upt flag s t atus regis t er 0 u-0 u -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ? ? a d1 if u1 tx if u1 rxif spi1 i f s pf1 i f t3if bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 u -0 r / w - 0 r /w -0 r/w - 0 r /w -0 t 2 if o c 2 i f i c2 if ? t 1 i f o c1 if ic1 i f int0if bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 4 un im pl e m e n te d : read as ? 0 ? bi t 13 ad1 if: a/ d c onv ers i on co m p l e te inte rrup t fl ag s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 12 u1 txif: u a r t 1 t r ans m i tte r int e rrup t fl ag s t atus b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 1 1 u1 rxif: uar t1 rece ive r in terrupt f l ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 10 sp i1if: spi1 even t in terrupt f l ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 9 sp f1if : spi1 fau l t in terru pt f l ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 8 t3 i f : t i m e r3 inte rrup t fla g s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 7 t2 i f : t i m e r2 inte rrup t fla g s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 6 oc2 i f : o u tp ut c o mp are c han nel 2 i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 5 ic 2 i f : inpu t c a p t ure ch a nne l 2 inte rrup t fl ag s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 4 un im pl e m e n te d : read as ? 0 ? bi t 3 t1 i f : t i m e r1 inte rrup t fla g s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 2 oc1 i f : o u tp ut c o mp are c han nel 1 i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 1 ic 1 i f : inpu t c a p t ure ch a nne l 1 inte rrup t fl ag s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 0 in t 0 i f : ext e rna l in terru pt 0 fl ag s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d
? 2010 microchip technology inc. ds39881d-page 69 pic24fj64 ga004 family regis t er 7-6: ifs1 : interr upt flag s t atus regis t er 1 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 u -0 u2txif u2rxif int2if t5if t4if oc4if oc3if ? bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? i n t 1 i f c ni f c m i f m i2 c1 if si2 c 1 i f bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 u2 txif: u a r t 2 t r ans m i tte r int e rrup t fl ag s t atus b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 14 u2 rxif: uar t2 re ce ive r in terru pt f l ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 13 in t 2 i f : ext e rna l in terru pt 2 fl ag s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 12 t5 i f : t i m e r5 inte rrup t fla g s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 1 1 t4 i f : t i m e r4 inte rrup t fla g s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 10 oc4 i f : o u tp ut c o mp are c han nel 4 i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 9 oc3 i f : o u tp ut c o mp are c han nel 3 i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 8- 5 un im pl e m e n te d : read as ? 0 ? bi t 4 in t 1 i f : ext e rna l in terru pt 1 fl ag s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 3 cnif : inp u t c h an ge no tifi ca tio n in terru pt f l ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 2 cmif: c o mp ara t or i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 1 mi 2c 1i f : mas t e r i2c1 eve n t i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 0 si 2c1if : sla v e i2c1 eve n t i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d
pic24fj64ga004 family ds39881d-page 70 ? 2010 microchip technology inc. regis t er 7-7: ifs2 : interr upt flag s t atus regis t er 2 u-0 u -0 r/w - 0 u -0 u-0 u -0 r/w - 0 u -0 ? ?pmpif ? ? ?oc5if ? bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 u -0 u-0 u -0 r/w - 0 r /w -0 ic5if ic4if ic3if ? ? ? spi2 i f spf2i f bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 4 un im pl e m e n te d : r ead as ? 0 ? bi t 13 pm pif : para lle l m a s t er port i n terr upt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 12 - 1 0 un im pl e m e n te d : r ead as ? 0 ? bi t 9 oc5 i f : o u tp ut c o mp are c han nel 5 i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 8 un im pl e m e n te d : r ead as ? 0 ? bi t 7 ic 5 i f : inpu t c a p t ure c h a nne l 5 inte rrup t fl ag s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 6 ic 4 i f : inpu t c a p t ure c h a nne l 4 inte rrup t fl ag s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 5 ic 3 i f : inpu t c a p t ure c h a nne l 3 inte rrup t fl ag s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 4- 2 un im pl e m e n te d : r ead as ? 0 ? bi t 1 sp i2if: spi2 even t in terru pt f l ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 0 sp i2if: spi2 faul t in terru pt f l ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = interrupt request has not occurred
? 2010 microchip technology inc. ds39881d-page 71 pic24fj64 ga004 family regis t er 7-8: ifs3 : interr upt flag s t atus regis t er 3 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ?rtcif ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 ? ? ? ? ?mi2c2ifsi2c2if ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 rt cif: r e a l -t i m e c l oc k / c a le nda r in terru pt fl ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 13 - 3 un im pl e m e n te d : r ead as ? 0 ? bi t 2 mi 2c 2i f : mas t e r i2c2 eve n t i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 1 si 2c 2if : sla v e i2c2 eve n t i n te rrupt fla g s t at us bit 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bit 0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881d-page 72 ? 2010 microchip technology inc. regis t er 7-9: ifs4 : interr upt flag s t atus regis t er 4 u-0 u -0 u-0 u -0 u-0 u -0 u-0 r /w -0 ? ? ? ? ? ? ?l v d i f bi t 15 bi t 8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 ? ? ? ? crcif u2erif u1erif ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 9 un im pl e m e n te d : r ead as ? 0 ? bi t 8 lv d i f : lo w - v o lt age dete ct inte rrup t fla g s t a t us bi t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 7- 4 un im pl e m e n te d : r ead as ? 0 ? bi t 3 crcif : crc ge n e ra to r in t e rru p t fl a g s t a t u s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 2 u2 erif: uar t 2 erro r in terru pt f l ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bi t 1 u1 erif: uar t 1 erro r in terru pt f l ag s t atu s b i t 1 = in terru pt re que st has o c c u rred 0 = in terru pt re que st has n o t o c c u rre d bit 0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39881d-page 73 pic24fj64 ga004 family regis t er 7-10: ie c0: inte rrup t enab l e control re giste r 0 u-0 u -0 r/w - 0 r /w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 ? ? a d1 ie u1 txi e u1 r xi e spi1 i e sp f 1 i e t 3 i e bi t 15 bi t 8 r / w - 0 r /w -0 r/w - 0 u -0 r/w - 0 r / w -0 r/w - 0 r /w -0 t2 ie o c 2 i e i c2 ie ? t 1 i e o c1 ie ic1i e i nt0i e (1) bit 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 4 un im pl e m e n te d : read as ? 0 ? bi t 13 ad1 ie: a/d co nv ers i on co m p le te inte rrupt ena b le bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 12 u1 txie: uar t 1 t r ans mi tter inte rrup t ena b le bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 1 1 u1 rxie: ua r t 1 re ce iv er i n te r r u pt e n ab le b i t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 10 sp i1ie: spi1 t r a n s f er c o mp let e in terru pt en abl e b i t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 9 sp f1ie: spi1 f aul t in terru pt en abl e b i t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 8 t3 i e : t i me r3 i n ter r upt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 7 t2 i e : t i me r2 i n ter r upt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 6 oc2 i e: o u tp ut c o mp are c h ann el 2 in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 5 ic 2 i e : i npu t c a p t ure chan nel 2 inte rrupt ena b le bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 4 un im pl e m e n te d : read as ? 0 ? bi t 3 t1 i e : t i me r1 i n ter r upt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 2 oc1 i e: o u tp ut c o mp are c h ann el 1 in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 1 ic 1 i e : i npu t c a p t ure chan nel 1 inte rrupt ena b le bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 0 in t 0 i e : exte rnal in terru pt 0 ena b le bi t (1 ) 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed note 1 : if intx ie = 1 , t h is e x te r n al in t e r r u p t i n pu t m u s t be co nf i g ur e d t o an av ai l a b l e r p n p i n. se e s e ct i o n 1 0 . 4 ? p eriph e ral pin se lect? f o r m o re inf o rm atio n.
pic24fj64ga004 family ds39881d-page 74 ? 2010 microchip technology inc. regis t er 7-1 1 : i e c 1: inte rrup t enab l e control re giste r 1 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 u -0 u2 txie u2rxie int2 ie (1 ) t5 ie t4 ie o c 4 ie o c3ie ? bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?i n t 1 i e (1 ) cn i e cmie mi2 c 1 i e s i2 c1 ie bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 u2 txie: uar t 2 t r ans mi tter inte rrup t ena b le bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 14 u2 rxie: u a r t 2 r e c e i v e r int e rrup t en abl e bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 13 in t 2 i e : exte rnal in terru pt 2 ena b le bi t (1 ) 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 12 t5 i e : t i me r5 i n ter r upt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 1 1 t4 i e : t i me r4 i n ter r upt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 10 oc4 i e: o u tp ut c o mp are c h ann el 4 in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 9 oc3 i e: o u tp ut c o mp are c h ann el 3 in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 8- 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4 in t 1 i e : exte rnal in terru pt 1 ena b le bi t (1 ) 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 3 cnie: inp u t ch ang e no tifi ca tion int e rru pt en abl e b i t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 2 cmie: c o mp arat or in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 1 mi 2c 1i e : m a s t er i2c1 eve n t in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 0 si 2c 1ie : sla v e i2c1 eve n t in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed note 1: if intxie = 1 , this external interrupt input must be configured to an available rpn pin. see section 10.4 ?peripheral pin select? for more information.
? 2010 microchip technology inc. ds39881d-page 75 pic24fj64 ga004 family regis t er 7-12: ie c2: inte rrup t enab l e control re giste r 2 u-0 u -0 r/w - 0 u -0 u-0 u -0 r/w - 0 u -0 ? ?pmpie ? ? ?oc5ie ? bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 u -0 u-0 u -0 r/w - 0 r /w -0 ic5ie ic4ie ic3ie ? ? ? spi2 i e spf2i e bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 4 un im pl e m e n te d : r ead as ? 0 ? bi t 13 pm pie: paral l el m a s t er po rt in terru pt en ab le b i t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 12 - 1 0 un im pl e m e n te d : r ead as ? 0 ? bi t 9 oc5 i e: o u tp ut c o mp are c h ann el 5 in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 8 un im pl e m e n te d : r ead as ? 0 ? bi t 7 ic 5 i e : i npu t c a p t ure c han nel 5 inte rrupt ena b le bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 6 ic 4 i e : i npu t c a p t ure c han nel 4 inte rrupt ena b le bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 5 ic 3 i e : i npu t c a p t ure c han nel 3 inte rrupt ena b le bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 4- 2 un im pl e m e n te d : r ead as ? 0 ? bi t 1 sp i2ie: spi2 ev en t in terru pt en abl e b i t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 0 sp f2ie: spi2 f aul t in terru pt en abl e b i t 1 = in terru pt re que st ena bl ed 0 = interrupt request not enabled
pic24fj64ga004 family ds39881d-page 76 ? 2010 microchip technology inc. regis t er 7-13: ie c3: inte rrup t enab l e control re giste r 3 u-0 r /w -0 u-0 u -0 u-0 u -0 u-0 u -0 ?rtcie ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 ? ? ? ? ?mi2c2iesi2c2ie ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 rt cie: r e a l -t im e c l oc k/c a le nda r int e rrup t ena b l e bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 13 - 3 un im pl e m e n te d : r ead as ? 0 ? bi t 2 mi 2c 2i e : m a s t er i2c2 eve n t in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 1 si 2c 2ie : sla v e i2c2 eve n t in terru pt enab le bit 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bit 0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39881d-page 77 pic24fj64 ga004 family regis t er 7-14: ie c4: inte rrup t enab l e control re giste r 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?l v d i e bi t 15 bi t 8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 ? ? ? ? crcie u2erie u1erie ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 9 un im pl e m e n te d : r ead as ? 0 ? bi t 8 lv d i e : low -v o l t a ge d e te ct i n ter r upt enab le s t atus b i t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 7- 4 un im pl e m e n te d : r ead as ? 0 ? bi t 3 crcie: c r c ge nera t or inte rrupt ena b le bi t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 2 u2 erie: uar t 2 erro r int e rrup t en abl e b i t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bi t 1 u1 erie: uar t 1 erro r int e rrup t en abl e b i t 1 = in terru pt re que st ena bl ed 0 = in terru pt re que st not en abl ed bit 0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881d-page 78 ? 2010 microchip technology inc. regis t er 7-15: ip c0: inte rrup t pr iori t y control re giste r 0 u-0 r /w -1 r/w - 0 r /w -0 u-0 r /w -1 r/w - 0 r /w -0 ? t1ip2 t1ip1 t1ip0 ? o c1 ip2 o c1 ip1 o c1 ip0 bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic1ip2 ic1ip1 ic1ip0 ? i nt0i p2 int0 ip1 i nt0 i p0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 - 1 2 t 1 ip2 : t1ip0 : t i m e r1 in terru pt pri o ri ty b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 oc1 i p2 :oc1 i p 0: o u tp ut c o mp are c h ann el 1 in terru pt priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 ic 1 i p 2 :i c 1 i p 0: i n pu t c a p t ur e c h an ne l 1 i n te r r u p t p r io r i ty bi ts 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 3 un im pl e m e n te d : r ead as ? 0 ? bi t 2- 0 i n t0ip2 : int0i p 0: ex tern al inte rrup t 0 priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d
? 2010 microchip technology inc. ds39881d-page 79 pic24fj64 ga004 family regis t er 7-16: ip c1: inte rrup t pr iori t y control re giste r 1 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t2ip2 t2ip1 t2ip0 ? o c2 ip2 o c2 ip1 o c2 ip0 bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ic2ip2 ic2ip1 ic2ip0 ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 - 1 2 t 2 ip2 : t2ip0 : t i m e r2 in terru pt pri o ri ty b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 oc2 i p2 :oc2 i p 0: o u tp ut c o mp are c h ann el 2 in terru pt priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 ic 2 i p 2 :i c 2 i p 0: i n pu t c a p t ur e c h an ne l 2 i n te r r u pt p r io r i ty bi ts 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bit 3-0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881d-page 80 ? 2010 microchip technology inc. regis t er 7-17: ip c2: inte rrup t pr iori t y control re giste r 2 u-0 r /w -1 r/w - 0 r /w -0 u-0 r /w -1 r/w - 0 r /w -0 ? u1rxip2 u1rxip1 u1rxip0 ? spi1i p2 spi1 i p1 spi1 i p0 bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spf1ip2 spf1ip1 spf1ip0 ? t 3 i p2 t 3 ip1 t 3ip0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 - 1 2 u1 rxip2 : u1 rxip0 : uar t 1 re ce ive r in terru pt pri o ri ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 sp i1ip2 : spi1ip 0 : spi1 ev ent inte rrupt prio rity bi t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 sp f1ip2 : spf1i p0: spi 1 fa ult inte rrup t prio rity b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 3 un im pl e m e n te d : read as ? 0 ? bi t 2- 0 t 3 ip2 : t3ip0 : t i m e r3 in terru pt pri o ri ty b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d
? 2010 microchip technology inc. ds39881d-page 81 pic24fj64 ga004 family regis t er 7-18: ip c3: inte rrup t pr iori t y control re giste r 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ad1ip2 ad1ip1 ad1ip0 ? u 1 t xip2 u1 txip1 u 1txip0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 ad1 ip2 : ad1 i p 0 : a/ d conv ers i on com p l e te inte rrup t prio rity bi t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 3 un im pl e m e n te d : read as ? 0 ? bi t 2- 0 u1 txip2 : u1 txip0 : uar t 1 t r an sm itt e r in terru pt priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d
pic24fj64ga004 family ds39881d-page 82 ? 2010 microchip technology inc. regis t er 7-19: ip c4: inte rrup t pr iori t y control re giste r 4 u-0 r /w -1 r/w - 0 r /w -0 u-0 r /w -1 r/w - 0 r /w -0 ? cnip2 cnip1 cnip0 ? c m i p2 cm ip1 cmip0 bi t 15 bi t 8 u-0 r /w -1 r/w - 0 r /w -0 u-0 r /w -1 r/w - 0 r /w -0 ? m i2 c 1 p2 mi 2c 1p1 mi2c1p0 ? s i2 c1p2 si 2c1p1 si2c1p0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : read as ? 0 ? bi t 14 - 1 2 cnip2 :cnip0 : inpu t cha n g e not i fic a t i on int e rrup t prio rity b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 1 1 un im pl e m e n te d : read as ? 0 ? bi t 10 - 8 cmip2 : cm ip0 : co mpar a t or i n te r r u pt p r io r i t y bi ts 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7 un im pl e m e n te d : read as ? 0 ? bi t 6- 4 mi 2c 1p 2 : mi 2 c 1p 0 : m a s ter i2c1 eve n t in terr upt priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 3 un im pl e m e n te d : read as ? 0 ? bi t 2- 0 si 2c1p2 : si2c 1 p 0: sl av e i2 c1 ev ent inte rrup t prio rity b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d
? 2010 microchip technology inc. ds39881d-page 83 pic24fj64 ga004 family regis t er 7-20: ip c5: inte rrup t pr iori t y control re giste r 5 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? i nt1i p2 int1 ip1 i nt1 i p0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 3 un im pl e m e n te d : r ead as ? 0 ? bi t 2- 0 i n t1ip2 : int1i p 0: ex tern al inte rrup t 1 priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d
pic24fj64ga004 family ds39881d-page 84 ? 2010 microchip technology inc. regis t er 7-21: ip c6: inte rrup t pr iori t y control re giste r 6 u-0 r /w -1 r/w - 0 r /w -0 u-0 r /w -1 r/w - 0 r /w -0 ? t4ip2 t4ip1 t4ip0 ? o c4 ip2 o c4 ip1 o c4 ip0 bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? oc3ip2 oc3ip1 oc3ip0 ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 - 1 2 t 4 ip2 : t4ip0 : t i m e r4 in terru pt pri o ri ty b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 oc4 i p2 :oc4 i p 0: o u tp ut c o mp are c h ann el 4 in terru pt priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 oc3 i p2 :oc3 i p 0: o u tp ut c o mp are c h ann el 3 in terru pt priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bit 3-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39881d-page 85 pic24fj64 ga004 family regis t er 7-22: ip c7: inte rrup t pr iori t y control re giste r 7 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u2txip2 u2txip1 u2txip0 ? u 2 r xip2 u2rxip1 u 2rxip0 bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? int2ip2 int2ip1 int2ip0 ? t 5 i p2 t 5 ip1 t 5ip0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 - 1 2 u2 txip2 : u2 txip0 : uar t 2 t r an sm itt e r in terru pt priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 u2 rxip2 : u2 rxip0 : uar t 2 re ce ive r in terru pt pri o ri ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 i n t2ip2 : int2i p 0: ex tern al inte rrup t 2 priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 3 un im pl e m e n te d : read as ? 0 ? bi t 2- 0 t 5 ip2 : t5ip0 : t i m e r5 in terru pt pri o ri ty b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d
pic24fj64ga004 family ds39881d-page 86 ? 2010 microchip technology inc. regis t er 7-23: ip c8: inte rrup t pr iori t y control re giste r 8 u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spi2ip2 spi2ip1 spi2ip0 ? spf 2ip2 sp f2ip1 spf2ip 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 sp i2ip2 : spi2ip 0 : spi2 ev ent inte rrupt prio rity bi t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 3 un im pl e m e n te d : r ead as ? 0 ? bi t 2- 0 sp f2ip2 : spf2i p0: spi 2 fa ult inte rrup t prio rity b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d
? 2010 microchip technology inc. ds39881d-page 87 pic24fj64 ga004 family regis t er 7-24: ip c9: inte rrup t pr iori t y control re giste r 9 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic5ip2 ic5ip1 ic5ip0 ? i c4 ip2 i c4 i p 1 i c4 ip0 bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ic3ip2 ic3ip1 ic3ip0 ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 - 1 2 ic 5 i p 2 :i c 5 i p 0: i n pu t c a p t ur e c h an ne l 5 i n te r r u pt p r io r i ty bi ts 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 ic 4 i p 2 :i c 4 i p 0: i n pu t c a p t ur e c h an ne l 4 i n te r r u pt p r io r i ty bi ts 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 ic 3 i p 2 :i c 3 i p 0: i n pu t c a p t ur e c h an ne l 3 i n te r r u pt p r io r i ty bi ts 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bit 3-0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881d-page 88 ? 2010 microchip technology inc. regis t er 7-25: ip c10: inte rrup t pr iority co n t r o l r e gis t e r 1 0 u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? oc5ip2 oc5ip1 oc5ip0 ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 oc5 i p2 :oc5 i p 0: o u tp ut c o mp are c h ann el 5 in terru pt priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bit 3-0 unimplemented: read as ? 0 ? regis t er 7-26: ip c1 1 : interr upt p r iority control regis t er 1 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? pmpip2 pmpip1 pmpip0 ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 pm pip2 :pm p i p 0: pa rall el m a s t e r port int e rrup t pri o rit y b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bit 3-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39881d-page 89 pic24fj64 ga004 family regis t er 7-27: ip c12: inte rrup t pr iority co n t r o l r e gis t e r 1 2 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? m i2 c 2 p2 m i 2 c 2p1 m i 2 c2p0 bi t 15 bi t 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? si2c2p2 si2c2p1 si2c2p0 ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 mi 2c 2p 2 : mi 2 c 2p 0 : m a s ter i2c2 eve n t in terr upt priori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7 un im pl e m e n te d : read as ? 0 ? bi t 6- 4 si 2c2p2 : si2c 2 p 0: sl av e i2 c2 ev ent inte rrup t prio rity b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 3- 0 un im pl e m e n te d : read as ? 0 ?
pic24fj64ga004 family ds39881d-page 90 ? 2010 microchip technology inc. regis t er 7-28: ip c15: inte rrup t pr iority co n t r o l r e gis t e r 1 5 u-0 u -0 u-0 u -0 u-0 r /w -1 r/w -0 r /w -0 ? ? ? ? ? r tcip2 r t c i p 1 r tcip0 bi t 15 bi t 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 rt cip2 :rtcip0 : rea l -t im e cloc k / c a le nda r int e rrup t pri o rit y b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7- 0 un im pl e m e n te d : r ead as ? 0 ?
? 2010 microchip technology inc. ds39881d-page 91 pic24fj64 ga004 family regis t er 7-29: ip c16: inte rrup t pr iority co n t r o l r e gis t e r 1 6 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? crcip2 crcip1 crcip0 ? u 2 erip2 u2 erip1 u 2 erip0 bit 15 bi t 8 u-0 r /w -1 r/w -0 r /w -0 u-0 u -0 u-0 u -0 ? u 1erip2 u1erip1 u1erip0 ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 - 1 2 crcip2 :crcip0 : crc ge n e ra to r err o r in te rru p t pri o ri ty b i t s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 u2 erip2 : u2 erip0 : uar t 2 err o r in terru pt pri o ri ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6- 4 u1 erip2 : u1 erip0 : uar t 1 err o r in terru pt pri o ri ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d bi t 3- 0 unimplemented: read as ? 0 ?
pic24fj64ga004 family ds39881d-page 92 ? 2010 microchip technology inc. regis t er 7-30: ip c18: inte rrup t pr iority co n t r o l r e gis t e r 1 8 u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? l vd i p 2 l vdip1 l vdip0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 3 un im pl e m e n te d : r ead as ? 0 ? bi t 2- 0 l v dip2 :l vdip0: l o w-v o lt a ge de tec t in terru pt pr iori ty bit s 11 1 = in terru pt i s prio rity 7 (hig hes t p r io rity in terru pt) ? ? ? 00 1 = in terru pt i s prio rity 1 00 0 = in terru pt s o u r ce is di sa ble d
? 2010 microchip technology inc. ds39881d-page 93 pic24fj64 ga004 family 7. 4 i nter rupt set up procedur es 7 . 4. 1 i n i ti al i z ati o n t o c o n f igu r e a n i n te rrupt so urc e : 1 . se t t h e nstdis co n t ro l b i t (i ntco n1 <1 5 > ) i f n e st ed inte rrup t s are not des ire d . 2. s e l e ct t h e u s e r - a s s i g ne d pr i o r i t y l e ve l f o r t h e i n ter r upt so urc e b y w r iti ng the co ntro l b i t s i n th e a ppro p ria t e i p c x re gis t er . the pri o rity le ve l w i l l d epe nd on the sp ec ifi c a ppl ic ati on and ty pe of i nter r upt s ou r ce . if m ult ipl e pri orit y le ve ls are n ot desired, t he ipc x re gis t er c ontro l bi t s for al l e nab led i n te rrupt s ourc e s m a y b e prog ram m e d to the s a m e no n-z e ro va lue . 3 . c l ear th e int e rrup t fla g st atu s bi t ass o c i a t ed w i th t h e pe r i ph er a l in th e asso ci at e d i f s x r e gi s t e r . 4 . en abl e th e i n te rrup t s ourc e b y se ttin g th e i n ter r upt en ab le co ntro l bit a s s o c i ate d w i th th e s our ce in the app ropr iate iec x r e g i s t er . 7.4 . 2 i nte rrupt se rvic e routin e t h e me t h od t h at i s us ed t o d e c la r e an i s r a n d in it i a li ze th e ivt w i th the co rrec t v e c t or a ddre s s w i l l d epe nd o n th e p r og ram m i ng lan gua ge (i.e ., ? c ? o r as s e m b le r) an d th e lan gua ge de ve lop m e nt too l s uit e t hat is u s e d to d eve lo p the ap pli c a t io n. in ge nera l , the u s e r m us t c l e ar th e in terru pt fla g in t he ap pro p ria t e ifs x reg i s t er for th e s our ce of th e int e rrup t tha t th e isr han dle s . o t he rw is e, th e isr wi l l be re -ent ered im me dia t el y af t e r ex iti ng th e ro uti ne. if t he isr is co ded in a s s e m b ly lan g u age , it m u s t be te rmi nate d u s i ng a retfie ins t ru cti on to u n st ac k the s a v e d pc v a lu e, sr l v a lu e and o l d c p u p r iori ty lev e l . 7.4 . 3 t rap s e rv ice routine a t r ap ser v ic e r o u t ine (t sr ) i s co ded l i k e a n isr , ex c ept t hat t he a pprop ria t e tr ap s t atu s f l ag in th e in tc o n 1 re gi ste r mu st b e c l ea red to av oi d re -entr y i n to the tsr. 7.4 . 4 i nte rrup t disa b l e al l us er inte rrup t s c an be d i s abl ed u s in g the f o ll ow in g pr oce d u r e: 1. pu sh t he c u rre nt sr v a lu e on to th e s o f t w a re s t ac k usi n g the push in s t r u ct i o n . 2. fo rce the c p u t o pri orit y le ve l 7 b y i nc l us iv e o r in g th e v a lu e o e h w i th sr l. t o e nab le us er i n te rrup t s, the pop i n st r u ct i o n m a y be us ed to res t ore the pre v i ous sr v a lu e. n o t e tha t on ly u s e r int e rru pt s w i th a prio rity le ve l of 7 or le s s ca n be d i sa bl e d . t r ap s o u r ce s ( l ev el 8- 1 5 ) c a n n o t be di sa ble d . th e disi i n s t r u c t i o n pr o v i d es a co nv e n i e n t w a y t o di sa bl e in terru pt s of pri o rit y l e v e ls 1-6 for a fi xe d p e rio d of ti me . l ev el 7 in terru pt sou r ce s are n ot dis ab l ed b y th e disi ins t ru cti on. note: at a device reset, the ipcx reg i st e r s ar e i n iti a l i z ed, s u c h tha t all us er in terru pt s our ces a r e as s i gn ed to p r iori ty lev e l 4.
pic24fj64ga004 family ds39881d-page 94 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 95 pic24fj64 ga004 family 8 . 0 o s c illat o r config u ration th e os cil l a t or sy ste m for pic 2 4fj 64g a0 04 fam i l y d e v ic es ha s t h e f o l l o w i n g f e at u r es : ? a tot a l o f f our ex te rn al an d in ter n a l o s c i ll ato r o p t i o n s as c l o ck so ur c e s, pr o v id in g 1 1 d i ffe r e n t c l o ck mo de s ? o n- c hi p 4x p l l t o bo os t i nt er n al o pe r at in g f r eq ue nc y on sel e c t i n t e r n al a n d ext e r n a l osc i l l a t or sou r ce s ? software - co ntro lla ble sw i t ch in g be tw ee n v ari ous cl o ck s o u r ce s ? s o f tw are - co ntro lla ble po st s c a le r for se lec t iv e cl o cki n g o f cp u f o r sy st em po we r s a vi ng s ? a f a il -safe c l o c k mo nit o r (f sc m) t hat det ect s c l oc k f a il ure a n d p e rm it s s a fe a ppl ic ati on re co ve ry or sh ut d o w n a s i m p l i fi ed dia g ra m o f th e o s c i l l at or s y s t em i s sho w n i n fi gure 8 -1 . f i g ure 8- 1: pi c24f j6 4g a00 4 fam i ly clock diagram note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 6. oscillator? (ds39700). pic24fj64ga004 fami l y s e co n d ar y osc illa to r so scen e nab l e oscillator sosco sosc i clo ck s o u r ce option for other modules osci osco pr im a r y os cilla to r x t , hs , e c cpu p e ri ph era l s postscaler clkdiv<10:8> wdt , pwr t 8 mh z f rcd iv 31 khz ( n om i nal ) frc oscillator lpr c oscilla to r sosc lprc postscaler c l ock cont ro l l ogi c f a il- sa fe clo ck mo ni tor clkdiv<14:12> frc clko (n omi nal ) 4 x p l l xtpl l , hspl l e c p l l, f r c p ll 8 mhz 4 mhz
pic24fj64ga004 family ds39881d-page 96 ? 2010 microchip technology inc. 8. 1 c pu cl ocki ng sche m e th e s y s t em cl ock so urc e ca n be p r ov ide d by one of fo ur s o u r ce s: ? p ri m a ry os c i lla tor (po s c) on t he o s ci a n d o s c o pi ns ? s e c o nda ry o s ci lla tor ( s osc ) on t he s o sc i and sosco pi ns ? f a s t inte rna l rc (frc) o s ci lla tor ? l ow-powe r int e rna l rc (l prc) os c ill ato r th e prim ar y osc i l l a t or and fr c so urc es ha ve th e o p tio n o f us in g the in tern al 4 x pl l. t he f r equ ency of th e fr c cl oc k s ourc e c an o pti ona lly be re duc ed by th e p r ogra m m a b le cl oc k d iv ide r . the se lec t e d c loc k so urc e g ene rate s the p r oc ess o r an d peri p h e ral c l o c k s our ces . th e pro c e s s or cl ock so urc e is di vi ded b y tw o to p r o- d u ce th e i n te r nal i n st r u c t ion c y c le cl oc k, f cy . in thi s d o cu me nt, the in str u cti o n cy cl e c l o c k is al so de note d by f os c / 2 . th e i n t e r n al i n s t r u c t i o n c ycl e cl oc k, f os c /2 , c an be prov id ed o n t he o s c o i/o p i n for s o m e o pera t in g m ode s of th e p r im ary os ci lla tor . 8. 2 i nit i al c o n f i gurat ion on po r th e os cil l at or sou r ce ( a n d op er at ing mod e ) th at i s use d at a de vice po w e r - o n r e se t ev ent is se lec t e d usi n g c o nf ig ur at ion bi t se tt in gs. th e o scil l a t o r c o nfi g - ur at io n bit set t i ngs a r e l o ca te d in th e c onf ig ur at io n r egi ste r s in t he pr og ra m memo ry (r ef er t o s ect i o n 2 4. 1 ?c on fi g u r a t i on b i t s ? fo r f u r t h e r de t a ils ). t he p r i m ar y oscil l at or c o nfi g u r a t i on bi t s , p o sc md 1: p o sc md 0 ( c on fi gur at io n w or d 2 < 1 : 0 > ) , an d t h e in it ial osci ll ato r se le ct c o nf igu r at ion bi t s , fno s c2 :f no sc0 (c on fi gu ra ti o n w o rd 2 < 10 :8 >) , se l e c t t h e o s c i l l a t o r s o ur c e t h a t is us ed at a p o w e r - o n r es et . the fr c prim ary os ci ll ator w i th p os t sc al er (frcdiv) i s th e d e f a u l t (u n p ro g r a mme d ) se l e cti o n . th e sec on dar y osc i l l at or , or one o f th e int erna l os c ill ato r s, m ay b e c hos en b y pro gra mm ing thes e b i t lo c a t i on s. th e c on f igu r ati on b i t s all ow us ers t o ch oos e b etw ee n th e v a ri ous cloc k mo des , s how n in t a ble 8 -1 . 8.2 . 1 c lock s w itchi ng mode configura tio n bit s t he f c k s m c o nf i gu r a t i o n bi ts ( c on f i g u r at i on w o rd 2<7 : 6> ) are us ed to joi n tl y con f ig ure de vic e cl oc k s w itc h in g and th e f a il -safe c l o c k m o n i tor (fsc m ) . c l o c k sw it ch ing i s en abl ed o nly w h en fc ksm 1 i s pr ogra m m e d (? 0 ?). the fsc m i s en abl ed on ly w h e n f c k s m 1 : f c k s m 0 a r e b o t h pr o g r am me d ( ? 00 ?). t a ble 8 - 1 : configuration bi t v a lues for clock s e le ction o s c illa tor m ode o s c illa tor sourc e poscm d 1: poscm d 0 fno s c2 : fno s c0 no te f a s t rc o sci l l a t or wi t h p o stsc a l e r (f r cdiv ) in tern al 11 111 1, 2 ( r es e r v e d) i nt e r na l xx 110 1 l o w-po we r rc os ci l l a t o r (l prc) in te rn a l 11 101 1 se c o nda ry (t i m e r 1) os c i lla tor (sosc) s ec o nd ar y 00 100 1 p r i m a r y o s ci lla tor ( x t) wi t h p l l mo du l e ( x t p ll ) pri m a r y 01 011 pri m a r y os ci lla tor (ec) with pll mo du l e ( e cp l l ) pri m a r y 00 011 pri m a r y os c i lla tor (hs) pri m a r y 10 010 p r i m a r y o s ci lla tor ( x t) p r i m a r y 01 010 p r i m a r y o s ci lla tor ( e c ) p r i m a r y 00 010 fa st rc os c ill ato r wi th pll mo dul e (f r c pl l) in tern al 11 001 1 fa s t rc o sci l l a t o r (frc) in te rn a l 11 000 1 note 1 : o s c o pi n func tion is de term in ed by the os c i ofc n c onfi g u r atio n b i t. 2: th is is th e de fau l t o s c i l l at or m ode fo r an unp rogr am med (era se d) d e v i c e .
? 2010 microchip technology inc. ds39881d-page 97 pic24fj64 ga004 family 8. 3 c ont rol regi ste r s th e ope rati on of the o s c ill ato r i s co ntro lle d b y thre e s p e c ia l f unc tio n r e gis t er s: ? o sccon ?c l k d i v ?o s c t u n th e o s c c o n re gis t er ( r e g i s te r 8 -1 ) is t he m a i n co n- tro l reg i st er for the o s c ill ato r . it co ntrol s c l oc k so urc e s w itc h i ng a nd all o w s the mo ni tori ng o f c l oc k so urc e s. th e c l oc k d i v i de r re gi ste r (r eg is ter 8 -2) co ntro ls th e f e a t ur e s a s so ci at e d w i t h d o z e m o de , as w e l l as t h e p o s t s c a l er f o r t h e f r c os ci l l a t or . th e fr c os ci ll ato r t u ne re gis t er (r e g is ter 8 -3) al lo w s th e u s e r to fi ne tun e t he frc o s c ill ato r o v er a rang e of ap pro x i m a t ely 1 2%. ea ch bi t i n c r em ent or de cre m e n t c han ges t he fac t ory c a l i bra t ed fre q ue nc y of the fr c os c ill ato r by a f i x ed a m o unt . re gi ste r 8 - 1 : os ccon : os cillator control regis t er u-0 r -0 r-0 r -0 u-0 r /w -x (1 ) r/w - x (1 ) r/w-x (1) ? c osc2 co sc1 cosc0 ? n osc2 n o sc1 nosc0 bi t 15 bi t 8 r/so-0 r/w - 0 r -0 (3 ) u - 0r / c o - 0u - 0 r / w - 0 r / w - 0 cl kloc k i olock (2 ) lo c k ?c f ? s o s c e n o swen bi t 7 bi t 0 le gen d : co = cl ea r on ly bi t s o = set on ly bi t r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 - 1 2 cosc2 : cosc0 : c u rren t o s c i l l at or se lec t io n b i t s 11 1 = f a s t rc os ci l l a t o r wi th po st sc a l e r (frcdiv) 11 0 = r es er v ed 10 1 = l ow -po w e r r c o s c i l l at or (l pr c ) 10 0 = s e c o nda ry os ci ll ator (sos c ) 01 1 = p r i ma ry os ci ll ator wi th pll mo dul e (xt p ll, hspll, ec pll ) 01 0 = p r i ma ry o s ci ll ator (xt , hs, ec) 00 1 = f as t r c o s c i l l ato r wi th pos t s c a l er and pll mo dul e (f r c p ll) 00 0 = f a s t rc o sci l l a t o r (frc) bi t 1 1 un im pl e m e n te d : read as ? 0 ? bi t 10 - 8 nosc2 : nosc0 : n e w o s c i l l at or se lec t io n b i t s (1 ) 11 1 = f a s t rc os ci l l a t o r wi th po st sc a l e r (frcdiv) 11 0 = r es er v ed 10 1 = l ow -po w e r rc o s c i l l at or (l pr c ) 10 0 = s e c o nda ry os ci ll ator (sos c ) 01 1 = p r i ma ry os ci ll ator wi th pll mo dul e (xt p ll, hspll, ec pll ) 01 0 = p r i ma ry o s ci ll ator (xt , hs, ec) 00 1 = f as t r c o s c i l l ato r wi th pos t s c a l er and pll mo dul e (f r c p ll) 00 0 = f a s t rc o sci l l a t o r (frc) note 1 : r e s e t va lue s f o r th es e b i t s are de term in ed b y t he fn osc c onfi gur atio n b i t s . 2: th e s t at e o f the io lo c k bi t c an onl y b e c ha nge d o nce an un loc k i ng se que nc e ha s bee n e x ec ut ed. in a ddi tio n , i f th e io l1 w a y c o nfi gur atio n b i t i s ? 1 ? o n c e th e i o l o ck b i t is se t, i t ca nno t b e c l ea red. 3: al so res e t s to ? 0 ? duri ng any v ali d c l o c k sw i t ch or w hen ev er a non -pll cl oc k mo de i s se lec t ed .
pic24fj64ga004 family ds39881d-page 98 ? 2010 microchip technology inc. bi t 7 cl klo ck: c l oc k s e le cti on loc k enab led bi t i f fsc m is en abl ed (fc ksm 1 = 1 ): 1 = c l o c k a nd pll sel e c t io ns are loc k e d 0 = c l oc k a nd pll sel ec t io ns are not loc k ed a nd ma y b e m od i fi ed b y set t in g th e o s wen b i t if fscm is di sa ble d (f c ksm1 = 0 ): c l oc k a nd pll sel e c t io ns are nev er loc k e d a nd may b e m odi fie d b y s e tt ing the o s wen bi t. bi t 6 i o l o ck: i / o loc k enab le bit (2 ) 1 = i/o l o c k i s a c t i ve 0 = i/o l o c k i s n o t act i v e bi t 5 l o ck: p ll l o c k s t a t us bi t (3 ) 1 = p l l m o d u le is in lo ck or pll m o d u l e s t art- up t i m e r i s s a ti sfi e d 0 = p l l m o d u le is ou t of lo ck , pll s t art-u p ti me r is ru nni ng or pl l is d i sa bl ed bi t 4 un im pl e m e n te d : r ead as ? 0 ? bi t 3 cf : cloc k fai l de tec t bi t 1 = f s c m ha s d e t e ct e d a cl oc k f a il u r e 0 = n o cl oc k f a il ure has be en det ec ted bi t 2 un im pl e m e n te d : r ead as ? 0 ? bi t 1 soscen: 3 2 k h z s e co nda ry os ci ll ator (so s c ) enab le bit 1 = e na bl e se co nd a r y o sci l l a t or 0 = d i s a b le se co nda ry osc il lat or bi t 0 osw en: os c ill ato r sw itc h en abl e b i t 1 = i nit i ate an os ci lla tor sw it ch to c l o c k so urc e s p e c i f ied by n o sc 2:n o sc 0 b i t s 0 = o s c i lla tor sw it ch is co mp lete regis t er 8-1: osccon : os cillato r control regis t er ( c o n ti nued ) note 1 : r e s e t va lue s f o r th es e b i t s are de term in ed b y t he fn osc c onfi gur atio n b i t s . 2: th e s t at e o f the io lo c k bi t c an onl y b e c ha nge d o nce an un loc k i ng se que nc e ha s bee n e x ec ut ed. in a ddi tio n , i f th e io l1 w a y c o nfi gur atio n b i t i s ? 1 ? o n c e th e i o l o ck bit is se t, it ca nno t b e c l ea red. 3: al so res e t s to ? 0 ? duri n g any v a li d c l o c k sw i t ch or w hen ev er a non -pll cl oc k mo de is se lec t ed .
? 2010 microchip technology inc. ds39881d-page 99 pic24fj64 ga004 family regis t er 8-2: clkdiv : clock d i vid e r re gis t e r r/w - 0 r /w -0 r/w - 1 r /w -1 r / w - 0 r /w -0 r/w - 0 r /w -1 roi d oze2 do ze 1 d o z e0 do z e n (1 ) rcd i v 2 rcdiv1 rcdiv0 bi t 15 bi t 8 u-0 u -1 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 roi: re co ve r on inte rrup t bi t 1 = i nter rupt s c l e a r th e d o zen b i t a nd res e t th e c p u p e ri phe ral cl ock ra tio to 1 : 1 0 = i nter rupt s h a v e no ef fec t o n th e d o zen b i t bi t 14 - 1 2 doze2 : do z e 0 : c p u pe rip hera l c l ock r a t i o sele ct bit s 11 1 = 1 :12 8 11 0 = 1 :64 10 1 = 1 :32 10 0 = 1 :16 01 1 = 1 :8 01 0 = 1 :4 00 1 = 1 :2 00 0 = 1 :1 bi t 1 1 dozen: d o ze enab le bit (1 ) 1 = d o z e2 :d o z e0 b i t s s pec ify th e c p u p e rip her al c l o c k rat i o 0 = c pu p e ri phe ral cl ock ra tio se t to 1:1 bi t 10 - 8 rcdiv2 :rcdiv0 : f r c pos t sc al er se lec t b i t s 11 1 = 31.25 k h z (d iv ide by 25 6) 11 0 = 125 k h z (div id e b y 6 4) 10 1 = 250 k h z (div id e b y 3 2) 10 0 = 500 k h z (div id e b y 1 6) 01 1 = 1 m h z (di v i de by 8) 01 0 = 2 m h z (di v i de by 4) 00 1 = 4 m h z (di v i de by 2) 00 0 = 8 m h z (di v i de by 1) bi t 7 un im pl e m e n te d : read as ? 0 ? bi t 6 un im pl e m e n te d : read as ? 1 ? bi t 5- 0 un im pl e m e n te d : read as ? 0 ? note 1 : th is bi t is au tom a ti ca ll y c l e a red when th e ro i bi t i s s e t and an int e rrup t oc c u rs .
pic24fj64ga004 family ds39881d-page 100 ? 2010 microchip technology inc. 8. 4 c l o ck swi t chi ng ope r ati o n w i th few lim it a t io ns , a ppl ic atio ns are fre e t o s w itc h b e tw ee n an y o f the f our c l o c k so urc e s (po s c , so sc , fr c an d lpr c ) un der s o f t w a re co ntro l an d at an y ti me . t o l i m i t the po ss ibl e sid e e f f e ct s that c oul d re su lt fro m th is f l ex ib ili ty , pic 2 4 f de vic e s hav e a s a fe gua rd l o c k b u il t in to t he swit chi n g pro c es s . 8.4 . 1 e n a b l ing cl o c k s w itching t o e nab le c l o c k sw i t ch in g, th e fc ksm 1 c o nfi gura t io n bi t in fla s h c o nfi gura t io n w o rd 2 m u s t be prog ram m e d to ? 0 ? . (r ef er t o sec t ion 24. 1 ? c onfig uratio n b i t s ? fo r fu rthe r det ail s .) i f the fc ksm1 c onf igu r ati on b i t i s un pro g ram m ed (? 1 ? ) , t h e c l o c k swi t ch i n g f u n c t i on a n d fa il- safe c l ock mo nit o r fun c ti on a r e di sab l e d . thi s i s th e d e fau l t set t in g. th e n o s c x co ntro l bit s (o sc c o n < 1 0 :8 >) do n o t c ont rol the c l oc k se le cti on w hen c l oc k s w i t c h in g i s dis - a b l e d . ho we ve r , th e co scx b i t s (o sccon<1 4 :1 2 > ) w i l l re fle c t t he clo c k s ourc e s e l e c t ed by the fn o s c x c on f ig urat ion bi t s . th e o s wen co ntro l bit (o sc c o n <0> ) h a s n o ef fec t w h en cl oc k s w it c h i n g i s d is a b l ed . it i s h e l d a t ? 0 ? a t al l ti me s. reg i s t er 8- 3: o s ct un: f r c os cill at o r t u n e reg i st er u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? t un5 (1 ) tu n 4 (1 ) tun3 (1 ) tun2 (1 ) tun1 (1 ) tun0 (1 ) bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 6 un im pl e m e n te d : r ead as ? 0 ? bi t 5- 0 t un5 :tun0 : fr c o s c ill ato r t u n i ng bi t s 01 1111 = m ax i m um fre que nc y d ev i at ion 01 1110 = ? ? ? 00 0001 = 00 0000 = c e nte r freq uen cy , os ci lla tor is runn in g at fac t ory c a li bra t ed freq uen cy 11 1111 = ? ? ? 10 0001 = 10 0000 = m i n i m um freq ue ncy d evi ati on note 1 : in cre m e n t s or dec rem e n t s of tu n 5 :tu n 0 m a y n o t c h a nge the fr c fre que nc y i n e qua l s t ep s ove r th e fr c t uni ng rang e, a nd ma y n ot b e m on oto nic . note : th e pri m a r y os c ill ator mo d e ha s th ree di ffe r e nt su bm od e s ( x t , h s a nd e c ) w h i c h are d e te rmi ned by the p o sc m d x c o n f ig ura t ion bit s . wh il e an a ppl ic ati o n c an sw it ch t o an d fro m p r im ary os cilla tor m o d e in sof t w a re , it c ann ot s w itc h b e tw ee n th e d i f f ere n t p r im ary su bm ode s w i thou t re prog ram m i ng the dev ic e.
? 2010 microchip technology inc. ds39881d-page 101 pic24fj64 ga004 family 8.4 . 2 o scil la to r sw itching se q u en ce at a m i n i m um , pe rform i n g a c l oc k sw i t ch req uir es thi s b a si c seq u e n ce : 1. if de sir ed, read th e c o sc x bit s (o sc c o n <14 :12> ), to d e te rmi ne t he c u rre nt os ci l l a t or s o u r ce . 2 . pe rform the unloc k s e q uen ce to al low a wr ite to th e o s c c o n reg i st er h i gh by te. 3. w r i t e t h e ap pr o p r ia t e v a lu e to t h e n o s c x b i t s (o scco n<10 :8>) for the ne w os ci lla tor so urc e . 4 . pe rform the unloc k s e q uen ce to al low a wr ite to th e osccon re g i s t e r l o w b y te . 5 . se t t he o s wen b i t to in iti a te th e os cil l a t or swi t ch . o n c e the ba si c se quenc e i s co mp let ed, th e s y s t e m c l o c k har dw are res pon ds au tom a ti ca lly as fo llo w s : 1 . th e c l o c k s w itc h i ng hard w are co mp ares th e c o sc x b i t s w i th the new v a l ue o f th e n o sc x bit s . i f t hey a r e the s a m e , the n the c l o c k s w itc h i s a re du nda nt ope rati on. in thi s ca se , th e o s wen bi t is c l e a re d aut om atic al ly a nd th e c l oc k sw i t ch is ab orte d. 2 . if a va lid cl ock sw i t c h has be en i n it iate d, th e l o ck (o sccon<5 > ) a n d cf (oscco n<3 > ) bit s are cl ear ed. 3 . th e n e w os ci lla tor i s tu rne d on by t he h a rdw a re i f it is no t cu rrent ly ru nni ng . if a c r ys t a l os cil l a t or m u s t be tu rned on , th e h a rdw a re w i ll w a it unti l th e o s t exp i re s. if th e new s ourc e is usi n g th e pl l, th en th e ha rdw a re wa it s un til a pll l o c k i s de t e ct ed ( l o c k = 1 ). 4 . th e ha rdw a r e w a it s fo r 10 c l oc k c y c l e s fro m th e n ew c l oc k so urc e an d t hen pe rform s the cl oc k swi t ch . 5. th e h a r d w a r e cl ea r s th e os w e n b i t to in di cat e a su cce ssf u l c l o ck t r an si ti on . in a d d i t i o n , t h e n o sc x bi t va lu es a r e t r an sf erre d to t h e c o sc x bi t s . 6. t h e ol d cl oc k s o u r c e i s t u r n e d off at t h i s ti me , w i t h t h e e xce p t io n o f lp r c ( i f wd t or fs c m a r e en abl ed ) or so sc (if sos c en r e m a in s se t ) . a r e co mm en d e d co de s e q u en c e fo r a cl oc k swi t ch i n cl ud es the fol l ow i ng: 1. d i s a b l e int e rrup t s du ring th e o s c c o n reg i st er un lo ck an d w r it e s equ en ce. 2. ex ec ute t he un lo ck seq uen ce for th e o s c c o n hi gh by te by w r iti ng 78h an d 9 a h to o s c c o n < 15: 8> in tw o bac k - to-bac k in s t r u ct i o ns . 3. w r ite ne w os ci lla tor so urc e to th e n o sc x bit s i n th e i n s t ruc t io n i m m e d i at ely fo ll ow in g th e unl o c k s equ enc e. 4. exec ute the unlock seq uence for the o s c c on low byte by w r iting 46h an d 57h to os c c o n <7:0> in two back- to- bac k instr u ctio ns. 5 . se t th e os wen b i t in the i n s t ru ct io n i m m e di ate l y fo ll ow i n g t he un lo ck s e que nc e . 6. c on t in ue to e x e c u t e c od e th at i s not cl oc k s ens iti v e (op t io nal ). 7. in vo ke an app ropri ate am ou nt o f so f t w a re de la y (c yc le co un ting ) to al lo w the s ele cte d osc i l l at or a nd / or p l l t o s t ar t an d stab i l i z e . 8. c h e c k to se e i f o s wen i s ? 0 ?. i f it is , th e s w itch was suc c e ss fu l. if o s w e n is sti ll s e t, the n c hec k the lo c k bi t to de term in e th e c aus e of fa ilu re. th e co re se que nc e for un loc k i ng th e o s c c o n reg i st er an d i nit iat i ng a c l o c k sw i t c h is s how n in exa m p l e 8-1. ex amp l e 8-1: bas ic code s e que nce for clock s w itch ing note 1 : t h e pr o c e ssor will continue to ex ec ut e c ode th roug hou t th e clo c k s w itc h in g s equ en ce. t i m i ng se nsi t iv e c o d e sh oul d n o t b e e x ec ut ed d u ri ng t h is ti me . 2: d i rect c l o c k sw it ch es b e tw ee n an y p r im ary os ci lla tor m o d e w i th pl l an d f r c p ll m o d e a r e no t p e r m it t e d. t h is a ppl ies to cl ock s w i t c hes in eit her d i re c- ti on. in th es e i ns t an ce s, the a ppl ic atio n mu st sw i t ch t o f r c mo de as a t r an si t i on c l oc k s o u r ce betw e en t he tw o pl l mo de s . ;pla ce the new oscillator selection in w0 ;osc conh (high byte) unlock sequence mov #oscc onh, w1 mov #0x78 , w2 mov #0x9a , w3 mov. b w2, [ w1] mov. b w3, [ w1] ;set new oscillator selection mov. b wreg, oscconh ;osc conl (low byte) unlock sequence mov #oscc onl, w 1 mov #0x46 , w2 mov #0x57 , w3 mov. b w2, [ w1] mov. b w3, [ w1] ;sta rt oscillator switch operation bset osccon,#0
pic24fj64ga004 family ds39881d-page 102 ? 2010 microchip technology inc. 8.4 . 3 s e c onda ry o s cill ator l o w- pow e r op er ati o n th e se con d a r y o s c i l l at or (so s c ) ca n op era t e in tw o d i s t inc t l ev els of pow e r c ons um pti on bas ed on dev ic e c onf igu r ati on. i n lo w - pow e r m ode , the os cil l a t or o pera t es i n a l o w - ga in, lo w - pow e r s t ate . b y d e fa ult , th e o s c ill ato r u s e s a hi ghe r gai n se ttin g , an d the r efo r e, r e q u i r e s mo r e po w e r . t h e s e c o nd ar y os ci l l a t or mo de se lec t io n bi t s , soscsel< 1 :0 > (cw2< 12:1 1 >), d e ter m i ne t he os c i l l at or ? s pow e r m ode . wh e n lo w - p o w e r mo de i s us ed , ca r e mu st be ta ke n in th e de si gn and lay o u t of t he so sc c i rc uit t o en su re th at th e os ci lla tor w i l l st art up a nd os c ill ate p r ope rly . th e l ow er gai n o f th is mo de ma ke s the so sc mo re s ensit iv e to noise an d re qui res a l ong er s t a r t-up tim e . 8.4 . 4 o sci lla t o r la yo ut o n low pin co un t de vi ce s, su ch as th ose i n th e pic 2 4fj 6 4 g a0 04 fa mi ly , du e to p i no ut li mi t a t i on s, th e so sc is mo re su sc ep tib l e to noi s e than oth e r pic 2 4 f de vi ce s. u n les s p r ope r care is t ak en i n th e des i g n an d l a yo ut o f th e so sc ci rcu i t, i t is po ss ib le f o r i nac cu rac i es to be in trod uc ed into th e o s c i l l ato r ' s pe rio d . in gen eral , the c r y s t a l c i rc uit c o n nec tio n s s h o u ld be a s s hort as p o s s i b le . i t is a l s o goo d p r ac tic e to su rroun d th e c r ys t a l c i rc uit w i th a grou nd loo p o r gro und pl an e. fo r m o re d e t a ile d inf o rm ati on on c r ys t a l c i rc ui t des i g n , pl ea se ref e r t o t he ? pic 2 4 f f a m ily r e fere nc e m a n u al ? , se ction 6 . ?o sc illa tor? (d s397 00 ) an d m i c r oc hi p a p p l ic at i o n n o t e s: an 8 26, ? c r ys t a l o s ci lla tor bas i c s an d c r ys t a l sele cti o n fo r r f pic ? a nd pic m ic ro ? de vi ce s? ( d s 008 26) an d an 849 , ?bas ic pic m ic ro ? o s c i l l at or d e sig n ? (d s0 084 9). note: this fea t ur e i s im pl e m e nt e d on l y on p i c24 f j6 4g a 0 0 4 f a m i l y de vi ce s wit h a m a j o r si lic on rev i si on l e v e l o f b or la ter (d evr ev re gi ste r va lue is 30 42h or g r eat er).
? 2010 microchip technology inc. ds39881d-page 103 pic24fj64 ga004 family 9 . 0 p owe r -s a v ing fe a t ures the p i c 2 4 f j6 4g a0 0 4 fa mi l y of devic es provi des the abi lity to mana ge pow er c onsum ption by s e lectiv ely m anaging clo cking to the c p u and the peripherals. in gen er a l , a low e r clock fr e quency and a reducti on in the num ber of c i rcuit s being c l ocke d cons titutes lo w e r cons umed pow er . a l l pic 24f devic es manag e po w e r c onsum ption in four dif f erent w a ys : ? c l ock fre que nc y ? i n s tr uct i on -bas ed sle ep and idl e m o d e s ? s o f tw are co ntro ll ed d o ze mo de ? s e l ec tiv e peri phe ral co ntro l in s o f t w a re c o mbi n a t ion s of the s e m e tho d s c an be us ed to se le c- ti ve ly t a i l o r an ap pli c a t io n? s pow e r co ns um pti on, w h il e s t il l ma in t a i n in g cri t ic al a ppl ic ati on fe atu r es , su ch a s ti mi ng- sen s i t iv e c o m m u n i c at ion s . 9. 1 c l ock frequency and clock swit chi n g pic 24f d evice s allow for a w i d e rang e of clo c k frequenc ies to be s e lected u nder applic ation control. if the sy stem cloc k configuratio n is not lock ed, u s ers can c hoose low - pow e r or hi gh-precisio n os cillators by sim ply c hanging the n o sc b i t s . th e proc ess of changi ng a s ys- tem cloc k during operation, as w ell a s lim it ations to the proc ess, are dis c uss ed in more det ail in section 8 .0 ?o scillator configur a t ion ? . 9. 2 i nstr ucti on- based power - savi ng modes pic 2 4f de vi ce s hav e tw o s pec ia l pow e r-sa v i ng m ode s th at a r e en tered thro ugh the e x e c ut ion of a s pecia l pwrsa v i n st ruc t ion . slee p mo de st op s c l o c k o per atio n a nd hal t s al l co de ex ec utio n; idl e m od e hal t s the c p u an d c od e e x ec ut ion , bu t al lo w s p erip hera l m od ule s to c ont inu e ope rati on. th e as sem bl y sy nt ax of th e pwrsav ins t ru cti on is sh ow n i n ex am pl e 9 - 1 . sl eep and idl e m o d e s ca n be ex ite d a s a res u lt of a n en ab led in terru pt, wd t tim e -o ut or a dev ic e r e se t. wh en the de vi ce ex it s t h es e mo des , i t i s sai d to ?w ak e-u p ?. 9 . 2. 1 s le ep m o d e sl eep mo de has th es e fe atu r es: ? t he sy st e m cl oc k s o u r ce is sh ut d o wn . i f a n o n - c hi p o s c i l l a t o r is u s ed , i t is tu r n ed off . ? t h e d e v i ce c u rren t c ons um pti on w ill be red u ce d to a m i n i m u m pro v i ded tha t no i/o p i n i s sou r ci ng c u rre nt. ? t h e fa il -safe cl oc k mo nit o r d oes no t op era t e d u r i ng s l ee p m o d e si nc e t h e s y s t em cl oc k s o u r ce i s d i s abl ed. ? t h e l p r c cl oc k w i ll c o n t in ue to ru n i n sl eep m ode if the wd t i s ena ble d . ? t h e w d t , i f en ab led , is au tom ati ca ll y c l e ared pr ior to e n ter i ng sle ep m o d e . ? s o m e devic e f eatu r es or peri phe ral s m a y c ont inu e to op erat e in sle e p mo de. thi s i n c l ud es i t em s su ch as th e i np ut c ha nge n oti fic ati on on the i/o p o rt s , o r per iph e ral s t hat us e an ex tern al clo c k i npu t. an y p e rip her al t hat requ ire s th e s y s t e m c l oc k so urc e fo r it s o pera t io n w i l l b e d i s abl ed i n sl eep mo de. th e d e v i ce w i l l w a k e -u p fr om slee p m o d e o n an y o f th e th es e ev en t s : ? o n an y i n t e r r u p t so ur c e t h at i s i n d i v i du al l y en ab led ? o n a n y for m o f de vi ce r e se t ? o n a wd t tim e -o ut o n w a ke -up from sl eep , th e p r oc es sor w i l l re st a r t w i th th e s a m e cl ock s o u r ce tha t w a s act iv e w h en slee p m ode wa s en tere d. ex amp l e 9- 1: pwrsav ins t ruction s y nt ax note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e s our c e . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ? s ec tion 10. pow e r-sav ing fea t ures ? (ds 39 6 98 ) . a d di t i on al po w e r- s a vi ng t i p s c an a l so be fo und i n appe ndix b: ?a d d i- tio nal g uida nce for pic 2 4fj 64g a 0 0 4 fa mil y app lica t ions? o f th is doc um en t. note : sleep_m ode and idle_mode are con- stants defined in the assembler include file for the sel e c t ed dev ic e. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode
pic24fj64ga004 family ds39881d-page 104 ? 2010 microchip technology inc. 9.2 . 2 i dle mode id le mo de has th ese fea t ure s : ? t he cp u wi l l s t op ex ec u t i n g i ns t r uc t io ns . ? t h e w d t is au tom ati ca ll y c l e ared . ? t he sy st em cl oc k s o u r ce r e m a i n s a c t i v e . b y d efau l t, a ll pe rip hera l mo du les con t in ue to o per ate n orm all y f r om the sy s t em cl oc k s ou r ce , bu t c an a l s o be se le cti v e l y dis ab l ed (s ee se ctio n 9 . 4 ? s ele c tiv e pe r i phera l m odul e cont r o l? ). ? i f the wdt o r fscm is e nab led , th e lprc w i ll al so r e ma in ac t i v e . th e d ev i c e w i l l w a ke from id le m od e o n a ny of t hes e ev e n ts: ? a n y i n te rrupt tha t is i ndi vi dua lly en ab led . ? a ny de vi ce re se t . ? a w d t ti me -out . o n w ak e-up f r om id le, th e cl oc k is re app lie d to the c p u a nd ins t ru cti on ex ecu t io n b eg i ns i m m edi ate l y , st a r tin g w i th the ins t ruct i on fo llo w i ng t he pwrsav in st r u ct i o n o r th e fi rst in stru cti o n in the isr. 9.2 . 3 i nte rrupt s coincid e nt w i th pow e r sa ve ins t ructions an y in terru pt th at c o in ci des w i th t he ex ec uti o n o f a pwrsa v ins t ruc t i on w i ll b e he ld o f f u n ti l en try i n to slee p o r idl e m ode ha s c o m p l e ted . th e de vi ce w ill the n w a ke-u p f r om sle ep o r id le m o d e . 9. 3 d oze mode g e n e ral l y , c han gin g cl oc k sp eed a nd in vo ki ng on e of th e p o w e r-s av in g m ode s are t he prefe rred st rategie s fo r red u c i ng pow e r co ns um ptio n. t here ma y b e c i r- c u m s t ances , how e v e r , w here thi s is not p r ac tica l . for e x am pl e, it ma y b e n e c e s s ar y f o r a n a ppl ic ati on to m a i n t a in uni nte rrupt ed sy nc hro nou s co mm uni ca tio n , e v en w h il e it is d oin g not hin g els e. r ed uc i ng s y s t e m cl oc k sp ee d ma y i n t r o d u c e co mm un ic a t i o n e r r o r s , w h i l e us in g a po w e r - s a vi ng m o d e ma y s t op c om m u nic at ion s c om pl etel y . d o ze m od e is a s i m pl e an d ef fec t i v e a l te rnat iv e m etho d to re du ce po w e r co ns um pti on w h i l e the dev ic e is s t il l e x ec ut ing c ode . i n t h is m o d e , the sy s t em c l oc k co nti n - u es to ope rate fro m the sa me s ourc e and a t th e s am e s pee d. peri ph eral m o d u le s co nti nue t o be cl oc ke d at th e sa me s p e ed w h i l e th e c p u c l o c k s p e ed is redu ce d. sy nc hro n iz ati on bet w een th e tw o c l oc k do ma ins i s ma in tai n ed , al l o w i n g t h e p e r i p h e r al s t o ac ce ss t h e sf r s wh i l e the cp u ex ec ute s c o d e at a s l o w er ra te. d o ze mo de is e nab le d b y se ttin g the d o zen b i t (c l k d i v<1 1 > ) . the rati o betw een periph eral and core c l o c k s pee d is d e te rmi ned b y the d o ze2 : d o z e 0 bit s (c l k d i v<14 :12 > ). t here are ei ght po ss ibl e c onf igu r ati ons , fro m 1 : 1 t o 1:2 56, w i th 1:1 b e i ng th e de f a ul t . it is al so po ss ib le to use d o z e mo de to sel e c t iv el y re duc e po w e r co ns um pti on i n ev ent d r iv en a ppl ic a- ti ons . th is all o w s cl oc k s ens it ive fun c ti on s, s u c h a s s y n c h r ono us co mm un ic ati ons , to c o nt inu e w i tho u t i n terr upti o n w h ile the c p u i d le s, w a itin g fo r som e t h in g to in vo ke an i nterr upt rou t in e. e nab lin g t he aut om ati c re turn to ful l -s pee d c p u ope rati on on in terru pt s i s en ab led b y se ttin g the r o i b i t (c lkd i v< 15> ). b y de fau l t, in terru pt ev en t s ha ve n o ef f ect o n d oze m od e op era t io n. 9. 4 s el ecti ve peri pheral modul e cont rol id le and d o z e m o d e s all o w u s e r s t o s u bs t a ntia ll y re duce p o w e r con s u m p t io n by s l ow i ng or s t op pin g th e c p u cl ock . eve n so , p eri phe ral m odu les sti ll rem ai n c l oc k ed an d thus con s u m e p o w e r . t here m a y b e ca se s w he r e th e ap pli c a t io n ne eds w hat thes e m od es do n ot pr ovi d e : th e all o c a ti on of po w e r re so urc e s to c p u p r o c es si ng w i t h mi n im a l p o w er co ns um pt i o n fr o m t h e pe rip hera l s . pic 2 4f dev ic es ad dres s thi s requ ire m e n t b y all o w i n g pe rip hera l m od ul es to be se lec t i v el y dis ab l ed , re duc in g or el im ina t in g t hei r p ow er co ns ump t io n. thi s ca n b e do ne wi th tw o c o n t rol bi t s : ? t h e pe riph era l en abl e b i t, g ene ric a l l y nam ed , ?xxxen?, loc a t ed i n t he m o d u le ? s m a i n c o nt rol sfr. ? th e pe riph era l m odu le di s abl e (pm d ) bi t, ge ne ric a ll y n a m ed, ?xxxm d ? , lo c a ted in one of th e pm d c ontro l re gi ste r s. bo th b i t s ha ve simil a r f unc tion s in en abli ng or disa blin g its associ ate d modu le. set t i ng th e p m d bi t f or a modul e disa ble s al l c l ock sour ces to t hat mod u le, r e d u cing its pow er co nsump t io n t o a n a b solu te mini mum. in th is st a t e, th e co ntr o l and st a t us reg i st ers associ ate d w i t h th e pe rip her al w i l l al so b e di sable d, so w r i t es to tho s e re gist er s w ill ha ve n o e f fe ct and re ad valu es w i l l b e inva lid. many pe ri pher al mo dule s h a ve a co rr espo ndin g pm d bit . in c o ntra s t , di s a b l i ng a m odu le by c l eari ng it s xxxen bi t di sa ble s i t s f unc tio n a lity , but lea v e s it s re gis t er s av ai la ble to b e re ad a nd w r i tte n to . pow e r co nsu m p t io n i s re du ced , b u t not by as m u c h as the pm d bi t d o es . m os t peri phe ral m od ule s h ave an en abl e bi t; ex c epti on s i nc l ud e c apt ure, co mp are and r t c c . t o ach i e v e mo re se lec t iv e po w e r s a v i n g s, pe rip h era l m odu le s ca n als o be s e l e c t iv ely dis a b l ed w h en th e de vi ce en ters idl e m o d e . t h is i s d one thr oug h th e c ont rol b i t of th e g ene ric nam e f o rm at, ? xxxidl?. b y de fau l t, al l m o d u le s tha t c a n op erat e d u ri ng idl e m o d e w i l l do s o . u s ing the d i sa bl e on id le fe atu r e all o w s f u r- t h e r r e du c t i o n of p o w er c o ns um pt i o n d u r in g i d l e mo de , en ha nci n g p o w e r s a v i n g s f o r ex trem el y c r iti c a l po w e r ap pl ic atio ns .
? 2010 microchip technology inc. ds39881d-page 105 pic24fj64 ga004 family 1 0 .0 i/ o po rt s all of the device pins (except v dd , v ss , mclr an d o s c i/c l k i) are s hare d b e tw ee n th e p e rip h e r als an d th e p a ra ll el i/o p o rt s . all i/o i npu t p o rt s feat ure sch m i t t t r i gge r in put s f or i m pr ove d n ois e imm un i ty . 10.1 par all e l i / o ( p io) por t s a p a ra lle l i/ o port tha t s hare s a pi n w i th a pe riph eral is , i n gen eral , sub s e r vi ent to t he pe riph era l . the p e rip h - e r al? s o utpu t b uf f er da t a and c ont rol si gn als a r e pr o v i d ed t o a pa ir o f mu lt i p le xe r s . t h e m u l t ip l e x e r s s el ect w het her the pe riph eral or the as so ci ate d p ort h a s o w ners h i p of the outp u t da t a a nd c ontro l s i gn als of th e i/o pi n. th e lo gic als o p r ev ent s ?lo op th rou gh?, i n w h ich a p o rt? s dig i t a l o u tp ut c an driv e t he i npu t of a p e rip hera l tha t sh ares the s a m e pin . fig u re 10-1 s h o w s h o w por t s a r e sh are d w i th othe r pe riph eral s a nd th e a s s o c i ate d i / o pin to w h ic h t hey are co nn ect ed. wh en a peri phe ral is e nab led an d the per i ph eral i s ac ti ve ly driv in g a n a s s oc i at ed pin , th e u s e of the pi n a s a ge ner al pur pos e out put pi n is di sa ble d . the i / o pi n m a y be re ad, but the o u tp ut d r iv er fo r the p a ra lle l po rt bi t w i ll b e d i s abl ed. if a pe riph era l is e nab led , bu t th e pe rip hera l i s not ac tiv e l y driv in g a pi n, tha t pi n m a y b e d r i v en by a p or t . al l p o rt pin s ha ve thre e regi ste r s di rec t ly as s o ci ate d w i th t h ei r o pe r at i o n a s di gi tal i / o . t he d a ta d i r e ct i on re gis t er ( t r i sx) dete r mi ne s w h e t he r the pin is an i n p u t or a n ou tput . if the d a t a d i re cti on bi t is a ? 1 ?, th en t h e pi n i s an in put. all p o rt p i n s ar e de fin ed a s i npu t s af te r a r e s e t . r e a d s from th e o u tp ut latc h regi ste r (la t x ) , re ad th e la tc h. w r ite s to the l a tc h, w r i t e th e la tc h. r e a d s f r om th e po rt (p or tx), re ad th e port p i ns , w h il e writ es to t he port pin s , write the la tch . an y b i t and it s a s s o c i a t ed dat a a nd co ntro l re gis t er s th at are not v a l i d f o r a p a r ticu l a r de vi ce w i ll b e di sa bl ed. th at m ea ns t he c orres po ndi ng l a t x an d tr is x re gis t er s a nd the port pin wi l l re ad as zer os. wh en a pin i s s hare d w i th ano the r peri phe ral o r func - ti on t hat is defi n e d as an inp u t o n ly , it i s , n e v e rth e le ss , re gard ed as a d edi ca ted port bec au se the r e i s n o ot her co mpe t in g s o u r ce of o u tp ut s . fig ur e 1 0 -1 : bl o ck d i ag ra m of a t y pi ca l sh ar e d p o rt s t ru ctu re note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 12. i/o ports with peripheral pin select (pps)? (ds39711). q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read por t re a d t r i s 1 0 1 0 wr tri s p e rip her al ou tpu t da t a out put e nab l e peri p her al in pu t d a ta i/ o pe r i p h er al m o d u l e p e rip her al ou tpu t e n a b le pio module o u tp u t mu l t i p l exers out put d ata input data p e ri p her al m odu l e e n abl e read lat
pic24fj64ga004 family ds39881d-page 106 ? 2010 microchip technology inc. 10. 1.1 o pe n-drai n configura t i o n in ad diti on to th e po r t , la t an d tr i s regi st ers for d a t a c ont rol, e a c h port pi n ca n al so be i n d i vi du all y co n- fi gur ed for eit her di git a l or o p e n -dra in ou tpu t. t h is i s c ont roll ed by the o pen -d rai n c o n t rol reg i s t er , o d c x , a s s o c i at ed w i th e a c h po rt. se ttin g a n y of th e b i t s co n- fi gur es the co rres p o ndi ng pin to ac t as a n o pen -drai n o u tpu t. th e ope n-dr ain fe atur e a llo w s the ge ner atio n of o u tpu t s hig her t han v dd (e .g., 5 v ) on any des ire d d i gi t a l o n l y pi ns b y usi ng ex tern al pu ll-u p res i st ors . th e m a x i m u m ope n-d r ain vo lt a ge a llo w ed i s t he s a m e a s t h e ma xi mu m v ih sp eci f ic ati o n . 10. 2 c onf igur ing anal og por t pins th e u s e of the ad 1pc f g an d t r i s reg i s t ers co ntro l th e op era t ion of th e a/d p o rt p i ns . th e po rt pin s t hat a r e d esi red as ana log in put s m us t hav e t hei r co rres pon d- i ng tr is b i t se t (in put) . i f the tr i s b i t is cl eare d (o utp u t), the dig i t a l o u tp ut l e v e l (v oh or v ol ) wil l b e c onvert ed. w hen read ing the por t reg i st er , a ll p i ns c onfi gu r ed a s a nal og in pu t c ha nne ls w i ll rea d as c l e ared ( a low le ve l). pi ns co nfig ure d as di git a l inp u t s w i l l no t co nv ert a n a nal og i npu t. an alo g le ve ls on a ny pin tha t is de fin ed a s a di g ita l in p u t ( i nc l u d in g t h e a n x p i ns ) ma y ca us e t h e in p u t bu ffe r to co ns um e cu r r e nt t h a t e x c e e d s t h e d e vi ce s pec ifi c a t io ns. 10. 2.1 i/o p o r t w r ite/ rea d t i mi ng o n e ins t ru cti on c y c l e is requ ire d be tw een a p o rt d i rec t io n c han ge o r port w r i t e o pera t io n an d a rea d o pera t io n o f t he sa me po rt. t y p i c all y , this i ns t ruc t io n w o uld be a nop . 10. 2.2 a na lo g inp u t p i ns and v o lt age consid era t ions the vo lt age tolerance of pins us ed a s devic e in put s is dep endent on the pin? s i nput f u nction. pins that are used as digit a l o n ly inp u t s are able to handle d c volt age s up to 5.5v , a level typic al for digit al logic circuit s . in contrast, pin s t h at als o h a ve analog input functi ons of an y kind c an onl y tole r a te volt a ges u p to v dd . v o lt age excurs ions bey ond v dd on thes e pins are al w ay s to be av oided. t able 10-1 sum m arize s the input ca p abilities . r e fer to section 27.1 ?d c c h ar acter istics? for more det ail s . t able 1 0 -1: i np ut v o lt ag e le ve ls 10. 3 i nput change noti fi cati o n th e inp u t c han ge no tifi ca tio n fun c ti on of th e i/o port s al lo w s the pi c 24f j64 g a004 f a m ily of de vic e s to ge n- er ate i n te rrup t requ es t s t o the pro c es s o r in res pon se to a ch ang e o f s t ate on s ele cte d i npu t p i ns . t his fe atur e i s c ap a bl e of de tec t in g inp ut ch ang e of s t ate s ev en i n sl eep mo de, w hen the cl oc ks are di sa ble d . d e pen din g on the de vi ce p i n co unt, the r e are up to 2 2 ex te rnal si g- na ls tha t ma y be sel ec t ed ( ena ble d) for g ene rati ng a n i n terr upt requ es t on a c h a nge of st a t e. th ere are f our c o n t rol regi ste r s a s s o c i a t ed w i th th e c n m odu le . the c n e n 1 and c n e n 2 reg i s t ers co nt ai n th e i n terr upt en abl e co ntro l bit s for ea ch o f t he c n i n p u t pi ns . se ttin g a n y of the s e bi t s en abl es a c n in terru pt fo r the c o rres p o ndi ng pin s . ea ch c n p i n als o has a w e ak pu ll-u p con n e c te d t o i t . th e pu ll -up s ac t as a c u rre nt s o u r ce that is co nne cte d to the p i n , and eli m i nat e the nee d fo r ext e rna l res i s t or s w h e n p u s h b u tto n o r k e y p ad de vi ce s a r e c o n nec te d. th e pu ll -up s are en abl ed s e p a rat e ly us in g th e c n p u 1 an d c n p u 2 reg i s t ers , w h ich c ont ain th e c ont rol bit s f o r ea ch o f t he c n p i n s . sett ing a n y of th e co ntro l bit s en ab les th e w e a k p u l l -up s f o r th e c o rre sp ond ing pi ns. wh en th e in tern al pu ll -up is se lec t ed , the p i n p u ll s up to v dd ? 0.7 v (ty p ic al ). m a k e sure th at ther e i s n o e x t e rna l pu ll -up so urc e w h en the i n tern al pu ll-u p s a r e e nab le d, as th e v o l t ag e di f f e r en ce ca n c a us e a c u rren t p a th. exa mple 10-1 : por t w r i t e/ r e a d exa mple po r t o r p i n to l e r a t e d inp ut d esc r i ptio n por t a<4 : 0> v dd on l y v dd in put lev e l s to lera ted . po r t b< 15:12> por t b< 4:0 > po r t c < 2:0> ( 1 ) por t a<1 0 :7 > ( 1 ) 5 . 5v t o le rate s i npu t l e ve ls ab ov e v dd , us efu l for mo st s t a n da r d l o gi c. por t b< 1 1 :5 > po r t c < 9:3> ( 1 ) note 1 : u n a v a ila bl e on 28 -pin de vi ce s. note : pu ll-u p s on ch ang e n o ti fic a ti on p i n s s hou ld alw a ys be dis ab l ed w hen ev er th e po rt p i n is co nfig ure d as a dig i t a l o u tp ut. mov 0xff00, w0 ; configure portb<15:8> as inputs mov w0, trisbb ; and portb<7:0> as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction
? 2010 microchip technology inc. ds39881d-page 107 pic24fj64 ga004 family 10. 4 p er ipher a l pin sel ect a m a j o r c h a lle nge in ge nera l purpo se dev ic es is pro v i d - i ng th e l a rge s t p o s s i b le se t of p e ri phe ral f eatu r es w h il e m i n i m i zi ng the con f li ct of fe atu r es on i / o pin s . t he c h a l - l eng e i s e v e n g r eate r on lo w pi n c oun t d e vi ce s s i m i l a r to th e pi c 2 4fj 6 4 g a fam i l y . in an app li cat i on th at n eed s to us e mo re th an o ne p erip he r al m ul t ip lex ed o n s i n gle pi n, inc on v en ie nt w o rka r oun ds in a ppl ic atio n code or a com p le te r ede si gn m a y be th e on ly op tio n . th e p e rip hera l p i n s e l e ct feat ure p r ov ide s a n al tern a- ti ve to t hes e c hoi ce s b y e nab li ng th e u s e r ? s p erip hera l s e t se le cti on an d the i r pla c e m e n t on a w i d e rang e of i/ o p i ns . by i n c r eas in g th e pi nou t opt ion s av ai lab l e o n a p a r tic u la r de vi ce , us ers c an bett e r t a il or th e m i c r oc ont roll er to th ei r e n ti re ap pli c a t ion , rath er tha n tri m m i n g th e a ppl ic ati on to fi t th e d e v i ce . th e peri phe ral pi n selec t feat ure ope rate s ov er a f i xe d s ubs et o f dig i t a l i/o pin s . u s ers m a y i n d epe nde ntl y m ap the inp ut a nd/ or ou tpu t of any on e of ma ny dig i t a l p e rip hera l s to an y one o f th es e i/ o pi ns. peri ph eral pi n s el ect is pe rfor med i n s of t w a re a nd ge nera lly d oes n ot re qui re th e de vi ce to be repr ogra m m e d . h a rdw a re s a fe gua rds are i n cl ud ed th at pre v e n t ac ci de nt a l or s pur iou s c ha nge s t o th e p erip hera l m ap pin g o nc e i t ha s b een es t ab lis he d. 10. 4.1 a va ila b l e pins th e pe rip hera l pi n se lect fea t ure is u s e d w i th a rang e o f up t o 26 p i n s ; th e nu mb er of ava i l abl e pi ns i s d epe n- d ent on t he p a rti c u l ar d e v i c e an d i t s pin c o unt. pins th at s upp ort the pe riphera l p i n sel e c t fe atu r e i n c l ud e th e d e si gn ation ?r pn? i n thei r f u ll pi n des ig nati o n , w h e r e ?r p? des ig nat es a rem a p p a b l e pe riph era l a nd ?n? is th e r em ap pab l e pi n n um be r . s e e t a bl e 1 - 2 f or pi n ou t op t i on s i n e a ch p a c k a g e offe r i ng . 10. 4.2 a va ila b l e pe rip h era l s th e pe riph era l s m a n age d by t he p e rip hera l pi n se lec t are all d i gi t a l o n l y peri p h e ral s . th es e inc l u de ge neral s e ri al com m uni ca tio n s (u ar t and spi), ge nera l p u r- p ose tim er cl oc k in put s, ti me r re la ted p erip hera l s ( i np ut c apt ure an d ou tpu t c o m p a r e) an d ex terna l in terru pt inpu t s . al so i nc l ud ed are t he ou tpu t s of th e co mp ara t or m o d u le , s i nc e t hes e a r e d i s c re te di gi t a l si gna ls . th e p erip he r al p i n se lec t m od ule is no t ap pli ed to i 2 c ?, ch an ge no tifi ca tion i n p u t s , r t c c a l ar m out put s o r pe riph eral s w i th ana log in put s. a k ey d i f f eren c e b etw e en pi n s ele ct an d no n pi n se lec t pe rip hera l s is t hat pin s e le ct pe riph era l s are no t a s s o - c i at ed w i th a d e fau l t i/o p i n . t he pe riph eral m u s t al w a y s be as s i gn ed to a s pecifi c i/o p i n b e fore i t can b e us ed . in co ntra st, no n pin s e l e c t p e ri phe rals are al w a y s av ai la ble on a de faul t pi n, a s s u m i n g th at th e pe rip h era l i s a c ti ve and no t c onf lic tin g wi th a not her p e ri phe ral. 10. 4.2. 1 p e r i p h e r a l pi n s e le ct f unc ti on pr i o r i ty wh en a pin se le ct a b le p e r ip hera l i s ac tiv e o n a gi ve n i/o pin , i t t a k e s pri o ri ty ov er all ot her di git a l i/o a n d di g- i t al c om m u nic at ion p eri phe rals as so cia t ed w i th th e pi n. pri o rit y is g i v en re gardl es s o f t he ty pe of p e rip h e r al th at i s map p e d . pin se lec t p e ri phe ral s nev er t a k e pri o rit y ov er any an al og f unc tio ns as so ci ated wi th th e pi n. 10. 4.3 c o n t r o lli ng pe rip h era l p i n se le ct periph eral pin s e l e c t f eatu r es are c ontr o ll ed th rough tw o se t s of s p ec ial fu nc tio n r e gis t ers : o ne to ma p pe rip hera l in put s, an d on e to m ap o utpu t s . b eca us e th ey are s e p a rat e ly co ntro lle d, a p a r t ic ula r pe riph eral ? s i npu t a nd ou tpu t (i f the pe rip hera l has both ) c a n b e pl ac ed o n any sel ec t ab le f u nc tion pin w i tho ut c ons tra i nt. th e as so ci ati on of a peri phe ral t o a pe riph eral se lec t - ab le pin is ha nd led in tw o d i f f ere nt w a ys , de pen din g o n i f an inp u t or a n ou tpu t is be in g m app ed. 10. 4.3. 1 i np ut m app ing th e i npu t s o f th e pe rip hera l pi n s el ect opt i on s a r e m app ed o n th e ba si s of the p eri phe ral; t hat is, a co ntro l re gis t er a s s o c i ate d w i th a peri phe ral d i c t ate s th e pin it w i l l be ma ppe d to. the r p in r x reg i s t ers a r e u s e d to c onf igu r e p e rip her al i npu t m a p p in g (s ee r egi ste r 10 -1 th roug h r e gis t er 10-1 4 ). each reg i s t er c o n t ai ns tw o se ts of 5- b i t f i el ds , w i t h e a c h s e t as so ci at e d w i t h o n e o f th e pi n se le ct a ble peri ph eral s . pro gra mm in g a gi ve n pe rip heral ? s bit fie l d w i th an ap propria t e 5 - bi t v a lu e m a p s th e r p n pi n w i th t hat va lue to tha t pe riph era l . f o r an y gi ve n dev ic e, the v al i d ran ge o f v al ues f or any of th e b i t fi el ds co rres pon ds to the ma xim u m n um ber of pe rip hera l p i n sel ec t io ns su ppo rted by the de vi ce.
pic24fj64ga004 family ds39881d-page 108 ? 2010 microchip technology inc. t a b l e 10- 2: selec t a b l e i n put sou r c e s ( m a p s i n p u t t o function) (1) 10. 4.3.2 o utpu t ma ppi ng in c ontra st to inp u t s , th e o u tp ut s of the pe riph eral pi n s e l e ct o p ti ons are m a p ped o n the bas is of the pin . in t h i s ca se , a co nt r o l r e gi st e r a s s o ci at e d wi th a par t i cu la r p i n d i c t ate s t he p e rip h e r al o u tp ut to be ma ppe d. th e r p o r x reg i s t ers a r e us ed to c ontr ol ou tput m ap pin g. l i k e th e r p in r x reg i s t ers , ea ch reg i s t er c o n t ai ns tw o 5 - bit fie l ds ; e a c h fi el d b e in g a s s o c i ate d w i th one r p n p i n (se e r e gist er 10-1 5 t h rou gh r egi st er 1 0 -27 ) . th e v a l ue o f th e bi t fi eld co rres pon ds to o ne of th e p e rip h - e r als a nd tha t p e ri phe ral? s o u tpu t i s ma pp ed to the pi n (s ee t a ble 1 0 - 3). becau s e of the ma pping techniq ue, the lis t of peripher- als for output mappi ng also i ncludes a null v alue of ? 00000 ?. this permit s any given pin to rema in dis c on- nec ted from the output of any of the pin selec t able periphe r a ls. inpu t nam e func tion name regis t er c o nfigu r ation bit s ex tern al inte rrup t 1 i nt1 r pinr0 intr1 < 4:0 > ex tern al inte rrup t 2 i nt2 r pinr1 intr2 r <4:0 > t i m e r 2 exte rn a l cl o c k t 2 c k r pinr3 t2 ckr < 4 : 0 > t i m e r 3 exte rn a l cl o c k t 3 c k r pinr3 t3 ckr < 4 : 0 > t i m e r 4 exte rn a l cl o c k t 4 c k r pinr4 t4 ckr < 4 : 0 > t i m e r 5 exte rn a l cl o c k t 5 c k r pinr4 t5 ckr < 4 : 0 > in put capt ure 1 i c 1 r p in r 7 ic 1 r <4 :0 > in put capt ure 2 i c 2 r p in r 7 ic 2 r <4 :0 > in put capt ure 3 i c 3 r p in r 8 ic 3 r <4 :0 > in put capt ure 4 i c 4 r p in r 8 ic 4 r <4 :0 > in put capt ure 5 i c 5 r p in r 9 ic 5 r <4 :0 > ou tp u t c o m p a r e fa u l t a o cf a r pinr1 1 o cf ar<4 : 0 > ou tp u t c o m p a re fa u l t b o cfb r pinr1 1 o cfbr<4 : 0 > uar t 1 re c e i v e u 1 r x r pinr1 8 u 1 r xr<4 :0 > u a r t 1 c l ear t o send u 1 c t s rpinr1 8 u 1 c tsr<4 : 0 > uar t 2 re c e i v e u 2 r x r pinr1 9 u 2 r xr<4 :0 > u a r t 2 c l ear t o send u2cts rpinr1 9 u 2 c tsr<4 : 0 > spi1 da t a in p u t sd i 1 rpinr2 0 s di1 r <4 :0 > spi1 cl o c k in p u t s ck1 i n r pinr2 0 s ck1 r <4 :0 > spi1 sla v e sel e c t inp u t s s1in rpinr21 ss1r<4 : 0> spi2 da t a in p u t sd i 2 rpinr2 2 s di2 r <4 :0 > spi2 cl o c k in p u t s ck2 i n r pinr2 2 s ck2 r <4 :0 > spi2 sla v e sel e c t inp u t s s 2in r pinr23 ss2r<4 : 0> note 1 : u n l e s s otherwise noted, all inputs use the schmitt trigger input buffers.
? 2010 microchip technology inc. ds39881d-page 109 pic24fj64 ga004 family t able 1 0 -3: s e l ect able output so urc es ( m a p s f u n c t i on to outpu t ) 10. 4.3.3 m ap pi ng l i m i t a ti on s t h e co nt r o l s c h e m a o f t h e pe r i ph er a l pi n s e l e ct is ex t r em el y f l ex ib l e . ot h e r t h an s yst e m a t ic bl o c k s t h a t p r ev ent s i gn al co nte n ti on ca us ed by t w o p h y s i c a l pin s b ein g co nfig ure d as th e sa me fu nc tio nal i npu t or tw o func tio nal o utpu t s c onf igu r ed as th e sa me pi n, the r e a r e n o h a rd w a re enf orce d loc k out s. the fl ex ibi lit y e x te nds to th e po int o f al low i ng a s i n g le inp u t to d r iv e m u l t ipl e peri p h e ral s or a sin g l e f unc tio nal o u tp ut to dr i v e mu l t i p le ou t p ut pi n s . 10. 4.4 c o n t r o llin g con f igu r at io n cha nges be ca use p e ri phe ral rema p p in g ca n be c han ged d u rin g ru n ti m e , s o m e re s t ric t ion s on peri p h e ral rem a p p in g a r e ne ede d to pre v en t ac c i de nt a l co nfi gur atio n c han ge s. pic 2 4f de vi ces in clu de t hree f eat ures to p r ev ent alt e rati on s to th e pe rip heral m a p : ? c on trol reg i s t er l o c k s e q uen ce ? c on tin uou s st a t e m o n i to ring ? c on fig u ra tion bi t rem a p p i ng l o c k 10. 4.4. 1 c on tr ol r egi st er loc k u n d e r norm a l o pera t io n, w r ite s to the r p in r x an d r p o r x regi ste r s are not al low e d. at tem p te d w r i t es w i l l ap pe ar to ex ec ute norm a l l y , b u t t he c o n t en t s of th e re gis t ers wi l l rem a i n un ch ang ed. t o c h a nge thes e re g- i s te rs, t hey m ust be unl oc ked in hard w are. the reg i st er lo c k is c o n t r o l l e d by t h e i o l o c k bi t ( o s c c o n < 6> ) . se ttin g iol o c k pre v e n t s w r i t es t o t he co ntro l r e g i st e r s; cl ea r i ng i o lo c k al lo w s w r i t e s . t o s e t o r cl ear iol o c k , a s pec if ic com m and se que n c e m u s t be ex ec ute d : 1. w r ite 46 h to o s c c o n <7 :0>. 2. w r ite 57h to o s c c o n <7 :0> . 3. c l e a r (o r s e t) i o l o c k a s a s i ng le ope rati on. u nl i k e th e si mi lar s eq uen ce w i th th e os c ill ato r ? s lo c k bi t, io lo c k re ma ins in on e st a t e un til c han ged . thi s al lo w s al l of t he pe rip hera l pi n se le ct s to b e co nfi gure d w i t h a si ngl e u n l o ck s equ en ce fol l ow e d b y a n u pda te to al l c ont rol re gis t e r s, th en l oc k e d w i th a se co nd l oc k s equ enc e. 10. 4.4. 2 c on tin uou s s t ate mon i to r i ng in add iti on t o be ing prot ec ted f r om dire ct w r ites , th e c ont ent s o f the r p in r x and r p o r x re gis t e r s a r e c ons t a ntly mo nit o red in ha rdw a r e by s h a dow reg i s t ers . if an unex pe cte d c han ge i n an y o f the regi st ers oc cur s (s uc h as ce ll d i st urba nc es c a u s e d by esd o r oth e r ex te rnal ev ent s), a c on f ig urat ion mi sm atc h r e se t w i l l be tri gge red. 10. 4.4. 3 c on fig u r a ti on b i t pi n s e l e c t loc k as an ad dit i on al le vel of sa fet y , the d e v i c e c an be co n- fi gure d to prev en t m o re th an on e w r i t e se ss ion to th e rpinrx a n d rporx re g i s t e r s . th e iol 1 w a y (c w2 <4> ) c onf igu r ati on b i t b l oc k s th e io lo c k b i t f r om be i n g cl e a r e d a f t e r i t ha s be en s e t o n c e . i f io lo c k re ma ins se t, th e re gist er unl o c k p r oce d u r e w i l l no t e x e c u t e and th e perip hera l pin sel e c t c o n t rol re g- i s te rs ca nno t be writ ten to . the o n ly w a y to c l e a r the b i t an d re-e nab le per iph e ral re ma ppi ng is to p e rfo r m a de vi ce re s e t. in t he d e fau l t (u npro g ram m e d) s t at e, io l1 w a y is se t, r e s t r i c t in g us er s t o o n e w r i t e se ss io n . p r o g r am mi ng io l1 w a y a llo w s us ers unl im ite d ac ce ss ( w i t h th e pr ope r us e o f th e u n lo ck s e qu enc e ) to th e pe rip h era l pi n sel e c t re gis t ers . f unct i on o u tput function num b e r (1 ) o u tput na me nu l l (2 ) 0 nul l c 1 o u t 1 c o m p ara t or 1 o u tp ut c 2 o u t 2 c o m p ara t or 2 o u tp ut u 1 tx 3 u ar t1 t r an sm it u1 r t s (3 ) 4 u ar t1 r equest t o s end u 2 tx 5 u ar t2 t r an sm it u2rts (3 ) 6 u ar t2 r equest t o s end sdo 1 7 spi1 d a t a o u tpu t s c k 1 o u t 8 spi1 c l oc k o u tput s s 1 o u t 9 s p i 1 sl ave s e lect o u tput sdo 2 10 spi2 d a t a o u tpu t s c k 2 o u t 1 1 spi2 c l oc k o u tput s s 2 o u t 1 2 s pi 2 sl ave s e lect o u tput o c 1 1 8 o ut p u t c o mpar e 1 o c 2 1 9 o ut p u t c o mpar e 2 o c 3 2 0 o ut p u t c o mpar e 3 o c 4 2 1 o ut p u t c o mpar e 4 o c 5 2 2 o ut p u t c o mpar e 5 no t e 1 : v al ue ass i g ned to t he r p n < 4:0 > pi ns co rre- s p on ds t o t h e p er i ph e r al ou t p ut f un c t i on num be r . 2: the null f unc tio n i s a s s i g ned to all r p n outp ut s at de vic e r e se t an d d i s abl es the r p n ou tpu t fu nct i on . 3: irda ? bc lk fu nc tio nal ity us es thi s outp u t.
pic24fj64ga004 family ds39881d-page 110 ? 2010 microchip technology inc. 10. 4.5 c onsi dera tions fo r pe rip h er al pin se le ct io n th e a bil ity to con t rol pe riph eral pi n s ele cti on int r odu ce s s ev eral con s i dera t io ns i nto a ppl ic ati on de si gn th at c oul d b e ov erl ook ed . thi s i s p a rtic ul arl y tru e fo r sev e ra l c om m o n pe riph eral s th at are av ail abl e on ly a s re ma pp a b le pe riph erals . th e ma in co nsi de r ati on is tha t t he peri ph eral pi n s e l e ct s are n o t av ail a b l e on d e fa ult pi ns i n the d e v i c e ? s de f a ul t ( r es et ) s t a t e . s i n c e al l r p i n r x r e gi st e r s r e se t to ? 11111 ? an d al l r p or x re gi ste r s res et to ? 00000 ?, al l perip her al pin se le ct inp ut s a r e ti ed to r p 31 and a l l p e rip her al p i n se lec t outpu t s are dis c onn ec ted . th is s i t uati o n re qui res the u s er to ini t ia lize th e dev ic e w i th th e pr ope r per iph e ral co nfi gura t io n be fore an y o t her a ppl ic ati on c ode i s ex ec ute d . si nce the io lo c k b i t res et s i n the un lo ck ed st ate , i t i s no t n ec es s ar y to e x ec ut e the u nl ock se que nc e af t er the dev ic e ha s c o m e out of r e s e t . fo r a ppl ic ati on sa fet y , h o w e v e r , i t i s b est to se t io lo c k and loc k th e co nfi gur atio n af ter w r i t ing to the co ntro l re gis t er s. be ca use the unl oc k s equ enc e is tim i n g c r iti c a l , it m us t b e ex ecu t ed a s an a s s em bly lan gua ge ro utin e in th e s a m e ma nne r a s ch an ges t o the os ci ll ator c onf igu r a- ti on. if the bul k of the a ppl ic ati on i s w r it ten i n c or a noth er hi gh-l ev el l ang uag e, th e unl oc k se qu enc e s hou ld be perf orm ed by w r iti ng i nli ne as se mb ly . c h oos in g th e c onf igu r ati on requ ire s t he r evi ew o f al l p e rip her al p i n s e le ct s an d th eir p i n a s s i g n me nt s , e s pe ci al ly tho s e tha t w i ll not be us ed in the ap pli c a t io n. in al l c a s e s , u nus ed pin - se le ct a b le pe rip hera l s sh oul d be d i s a bl ed c om pl e te l y . u nu s e d pe r i ph er a l s s ho u l d h a ve th ei r in put s as si gne d t o a n unu se d r p n pi n fu nc tio n. i/ o p i ns w i t h un us ed r p n fun c ti ons s hou ld b e c onf igu r ed wi th the nul l p e ri phe ral outp u t. th e a s s i g n m ent of a p e rip hera l t o a p a r tic u l a r p i n doe s n o t au tom a ti cal l y p e rfo r m a n y ot her c onf igu r ati on of th e p i n? s i/o cir c ui try . in the o ry , thi s me ans a ddi ng a p i n-se l e c t ab le o u tp ut t o a pi n m a y me an ina d v e rte n tl y dr i v i n g an e x i s t i ng p er i p he r al i n pu t w h en t h e o u t p u t is d r iv en. u s ers m u s t be f a m ili ar w i th t he be ha vio r of o t her fix ed p e ri phe rals th at s hare a re ma pp a b l e pi n an d k now w h e n t o e n a b le o r di sa ble t hem . t o be s a fe , f i xe d d i gi t a l peri p h e ral s th at s h a r e th e s a m e pi n s hou ld b e d i s abl ed w h en not in us e. a lo n g t h ese li ne s, c o n f ig ur in g a r e ma ppab le p in fo r a sp eci f ic p e r i ph er al do es n o t au to ma ti ca ll y t u r n t h a t f e a- t u re on . t h e pe ri ph era l m u st be s p e c i f i c a l l y co nf ig ure d f o r op era t i on an d en ab le d, as i f it w e re t i e d t o a fix e d p i n . w h e r e th is h a p p e n s i n th e ap pl ic at ion c o de (i m m e d i a t e ly fo ll o w i n g de vi ce r e se t a n d pe r i p h e r al c o n f ig ur at i on or i ns i d e t he ma in ap pl ic at io n ro ut in e) d ep en ds on th e pe r i p h e r a l a n d i t s use in t h e ap pl ic at io n. a fi nal con s i derat io n is tha t peri phe ral p i n s e l e c t func - ti ons ne ith e r o v e rride an alo g i npu t s , nor rec onf igu r e pi ns wi th ana log fu nc tio n s fo r d i gi t a l i/o . if a pin i s c onf igu r ed as a n a n a l og in pu t o n d e v i c e r e se t, i t m u s t be ex pli c i t ly rec onfi gur ed as di git a l i/o wh e n us ed w i th a peri p h e ral pi n s e le ct. ex am ple 1 0 - 2 s h o w s a c onf igu r ati on for bid i re cti o na l co mm un i c a t io n w i t h f l ow co n t ro l u s in g u a r t 1. t h e fo llo w i ng in put and ou tpu t fu nct i on s a r e u s e d: ? i n p u t fu n c ti o n s : u1 rx, u1 cts ? output functions: u1tx, u1rts e x a mp l e 10- 2 : c o nf ig u r i n g uart1 input and output functions note : in ty ing pe rip hera l p i n sel e c t i npu t s to rp31, rp31 does not have to exist on a device for the registers to be reset to it. //********************************* **** // unlock registers //********************************* **** asm volatile ( "mov #osc con, w1 \n" "mov #0x4 6, w2 \n" "mov #0x5 7, w3 \n" "mov.b w2, [ w1] \n" "mov.b w3, [ w1] \n" "bclr osccon,#6"); //*************************** // configure input functions // (see table 10-2) //*************************** //*************************** // assign u1rx to pin rp0 //*************************** rpinr18bits.u1rxr = 0; //*************************** // assign u1cts to pin rp1 //*************************** rpinr18bits.u1ctsr = 1; //*************************** // configure output functions // (see table 10-3) //*************************** //*************************** // assign u1tx to pin rp2 //*************************** rpor1bits.rp2r = 3; //*************************** // assign u1rts to pin rp3 //*************************** rpor1bits.rp3r = 4; //********************************* **** // lock registers //********************************* **** asm volatile ( "mov #osc con, w1 \n" "mov #0x4 6, w2 \n" "mov #0x5 7, w3 \n" "mov.b w2, [ w1] \n" "mov.b w3, [ w1] \n" "bset oscc on, #6" );
? 2010 microchip technology inc. ds39881d-page 111 pic24fj64 ga004 family 10. 5 p er ipher a l pin sel ect regis t er s th e pic 24 f j 64g a00 4 fam i l y of de vi ce s im pl em ent s a tot a l of 27 reg i s t ers fo r re ma pp a b le p e rip hera l c onf igu r ati on: ? i n put re m app ab le pe rip hera l re gis t ers (1 4) ? o utp u t r e ma pp abl e pe riph eral re g i s t ers (13 ) note : in put and ou tpu t reg i s t er v a l ues c a n o n l y be c han ge d i f o s c c o n < io lo c k > = 0 . se e sec t ion 10. 4.4 . 1 ? c ontr o l r e gis t er lo ck? fo r a s p e c i f ic co mm an d s equ en ce. regis t er 10-1: rpi nr0: p e ri phe ral p i n s e le ct inp u t re g i ste r 0 u-0 u -0 u-0 r /w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? i nt1 r 4 i nt1 r 3 i n t 1 r 2 i nt1 r 1 i nt1 r 0 bi t 15 bi t 8 u-0 u -0 u-0 u -0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 i n t1 r4 :i nt1 r 0 : ass i g n ex tern al inte rrupt 1 (i n t 1) to th e c o rre sp ond in g r p n pin bit s bi t 7- 0 un implemented: read as ? 0 ? regis t er 10-2: rpi nr1: p e ri phe ral p i n s e le ct inp u t re g i ste r 1 u-0 u -0 u-0 u -0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u -0 u-0 r /w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? i nt2 r 4 i nt2 r 3 i n t 2 r 2 i nt2 r 1 i nt2 r 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 i nt2r4:int2r0: assign external interrupt 2 (int2) to the corresponding rpn pin bits
pic24fj64ga004 family ds39881d-page 112 ? 2010 microchip technology inc. regis t er 10-3: rpi nr3: p e ri phe ral p i n s e le ct inp u t re g i s t er 3 u-0 u -0 u-0 r /w -1 r / w - 1 r /w -1 r/w - 1 r /w -1 ? ? ? t 3ckr 4 t 3ckr3 t 3 c kr2 t 3 c kr 1 t 3ckr0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? t 2ckr 4 t 2ckr3 t 2 c kr2 t 2 c kr 1 t 2ckr0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 t 3 ckr4 :t3 ckr 0 : as si gn t i m e r3 exte rnal c l o c k (t3 c k ) t o t he c o rres p o ndi ng r p n pin bi t s bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 t2ckr4:t2ckr0: assign timer2 external clock (t2ck) to the corresponding rpn pin bits regis t er 10-4: rpi nr4: p e ri phe ral p i n s e le ct inp u t re g i s t er 4 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? t 5ckr 4 t 5ckr3 t 5 c kr2 t 5 c kr 1 t 5ckr0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? t 4ckr 4 t 4ckr3 t 4 c kr2 t 4 c kr 1 t 4ckr0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 t 5 ckr4 :t5 ckr 0 : as si gn t i m e r5 exte rnal c l o c k (t5 c k ) t o t he c o rres p o ndi ng r p n pin bi t s bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 t4ckr4:t4ckr0: assign timer4 external clock (t4ck) to the corresponding rpn pin bits
? 2010 microchip technology inc. ds39881d-page 113 pic24fj64 ga004 family regis t er 10-5: rpi nr7: p e ri phe ral p i n s e le ct inp u t re g i ste r 7 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? i c2 r 4 ic2 r 3 i c2 r2 ic2 r 1 i c2 r0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? i c1 r 4 ic1 r 3 i c1 r2 ic1 r 1 i c1 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 i c 2r 4:ic 2 r 0: as si gn inpu t c a p t ure 2 (ic 2 ) to th e c o rre sp ond in g r p n pin b i t s bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 ic1r4:ic1r0: assign input capture 1 (ic1) to the corresponding rpn pin bits regis t er 10-6: rpi nr8: p e ri phe ral p i n s e le ct inp u t re g i ste r 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? i c4 r 4 ic4 r 3 i c4 r2 ic4 r 1 i c4 r0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? i c3 r 4 ic3 r 3 i c3 r2 ic3 r 1 i c3 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 i c 4r 4:ic 4 r 0: as si gn inpu t c a p t ure 4 (ic 4 ) to th e c o rre sp ond in g r p n pin b i t s bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 ic3r4:ic3r0: assign input capture 3 (ic3) to the corresponding rpn pin bits
pic24fj64ga004 family ds39881d-page 114 ? 2010 microchip technology inc. regis t er 10-7: rpi nr9: p e ri phe ral p i n s e le ct inp u t re g i s t er 9 u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? i c5 r 4 ic5 r 3 i c5 r2 ic5 r 1 i c5 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 ic5r4:ic5r0: assign input capture 5 (ic5) to the corresponding rpn pin bits regis t er 10-8: rpi nr1 1: p e r ip her a l pi n se lec t i n pu t regis t er 1 1 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? o c f br4 o cfbr3 o cfbr2 o cfbr1 o cf br 0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? o c f ar4 o cf ar3 o cf ar2 o cf ar1 o cf ar0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 ocfbr4 : o cfbr 0 : a s s i gn ou tp u t c o mpa r e f a ul t b ( o c f b ) t o t h e c o r r e s p on di n g r p n p i n bi ts bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 ocfar4:ocfar0: assign output compare fault a (ocfa) to the corresponding rpn pin bits
? 2010 microchip technology inc. ds39881d-page 115 pic24fj64 ga004 family regis t er 10-9: rpi nr18 : pe riph eral p i n s e l e c t inp u t re giste r 18 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? u 1 c tsr 4 u1 ctsr3 u 1 c tsr2 u1 ct sr 1 u 1 c tsr0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? u 1rxr4 u 1rxr3 u 1rxr2 u 1 r x r 1 u 1 r xr0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bit 12-8 u1ctsr4:u1ctsr0: assign uart1 clear to send (u1cts ) to t he c o rres pon di ng r p n pin bi t s bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 u1rxr4:u1rxr0: assign uart1 receive (u1rx) to the corresponding rpn pin bits regis t er 10-10 : r pi nr19 : pe riph eral p i n s e l e c t inp u t re giste r 19 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? u 2 c tsr 4 u2 ctsr3 u 2 c tsr2 u2 ct sr 1 u 2 c tsr0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? u 2rxr4 u 2rxr3 u 2rxr2 u 2 r x r 1 u 2 r xr0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bit 12-8 u2ctsr4:u2ctsr0: assign uart2 clear to send (u2cts ) to t he c o rres pon di ng r p n pin bi t s bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 u2rxr4:u2rxr0: assign uart2 receive (u2rx) to the corresponding rpn pin bits
pic24fj64ga004 family ds39881d-page 116 ? 2010 microchip technology inc. regis t er 10-1 1 : r pi nr20 : pe riph eral p i n s e l e c t inp u t re giste r 20 u-0 u -0 u-0 r /w -1 r / w - 1 r /w -1 r/w - 1 r /w -1 ? ? ? s ck1 r 4 s ck1 r 3 s ck1 r 2 s ck1 r 1 s ck1 r 0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? sdi1 r 4 sdi1 r 3 sdi 1 r 2 sdi1 r 1 sdi1 r 0 bit 7 bit 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : read as ? 0 ? bi t 12 - 8 sck1 r 4 : s ck1 r0 : ass i g n spi1 cl o c k inp u t (sc k 1in ) to th e c o rre sp ond in g r p n pin bit s bi t 7- 5 un im pl e m e n te d : read as ? 0 ? bi t 4- 0 sdi 1 r4 :sdi1 r 0 : as si gn spi1 d a t a inpu t (sd i 1 ) to the co rres p o ndi ng rp n pi n b i t s regis t er 10-12 : r pi nr21 : pe riph eral p i n s e l e c t inp u t re giste r 21 u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u -0 u-0 r /w -1 r / w -1 r/w-1 r/w-1 r/w-1 ? ? ? ss1r 4 ss1r3 ss1r2 ss1 r 1 ss1 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 ss 1r4:ss1 r 0 : as sign spi1 slave select input (ss1in) to the corresponding rpn pin bits
? 2010 microchip technology inc. ds39881d-page 117 pic24fj64 ga004 family regis t er 10-13 : r pi nr22 : pe riph eral p i n s e l e c t inp u t re giste r 22 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? s ck2 r 4 s ck2 r 3 s ck2 r 2 s ck2 r 1 s ck2 r 0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? sdi2 r 4 sdi2 r 3 sdi 2 r 2 sdi2 r 1 sdi2 r 0 bit 7 bit 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : read as ? 0 ? bi t 12 - 8 sck2 r 4 : s ck2 r0 : ass i g n spi2 cl o c k inp u t (sc k 2in ) to th e c o rre sp ond in g r p n pin bit s bi t 7- 5 un im pl e m e n te d : read as ? 0 ? bi t 4- 0 sdi 2 r4 :sdi2 r 0 : as si gn spi2 d a t a inpu t (sd i 2 ) to the co rres p o ndi ng rp n pi n b i t s r e gi ste r 1 0 - 1 4 : r p i n r 2 3: per i p h e r a l pi n sel ec t i n pu t r e gi s t er 2 3 u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u -0 u-0 r /w -1 r / w -1 r/w-1 r/w-1 r/w-1 ? ? ? ss2r 4 ss2r3 ss2r2 ss2 r 1 ss2 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 ss 2r4:ss2 r 0 : as sign spi2 slave select input (ss2in) to the corresponding rpn pin bits
pic24fj64ga004 family ds39881d-page 118 ? 2010 microchip technology inc. reg i s t er 10- 15 : r po r 0 : pe rip h era l pin se l e ct o u t p ut re gi st e r 0 u-0 u -0 u-0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ? ? ? r p1 r 4 rp1 r 3 r p1 r2 rp1 r 1 r p1 r0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p0 r 4 rp0 r 3 r p0 r2 rp0 r 1 r p0 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp1 r 4 : rp1 r 0 : peri phe ral o u tpu t fu nc tio n is as si gne d to r p 1 ou tput pin bi t s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 rp0r4:rp0r0: peripheral output function is assigned to rp0 output pin bits (see table 10-3 for peripheral function numbers) reg i s t er 10- 16 : r po r 1 : pe rip h era l pin se l e ct o u t p ut re gi st e r 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p3 r 4 rp3 r 3 r p3 r2 rp3 r 1 r p3 r0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p2 r 4 rp2 r 3 r p2 r2 rp2 r 1 r p2 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp3 r 4 : rp3 r 0 : peri phe ral o u tpu t fu nc tio n is as si gne d to r p 3 ou tput pin bi t s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 rp2r4:rp2r0: peripheral output function is assigned to rp2 output pin bits (see table 10-3 for peripheral function numbers)
? 2010 microchip technology inc. ds39881d-page 119 pic24fj64 ga004 family reg i s t er 10- 17 : r po r 2 : pe rip h era l pin se l e ct o u t p ut re gi st e r 2 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p5 r 4 rp5 r 3 r p5 r2 rp5 r 1 r p5 r0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p4 r 4 rp4 r 3 r p4 r2 rp4 r 1 r p4 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp5 r 4 : rp5 r 0 : peri phe ral o u tpu t fu nc tio n is as si gne d to r p 5 ou tput pin bi t s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 rp4r4:rp4r0: peripheral output function is assigned to rp4 output pin bits (see table 10-3 for peripheral function numbers) reg i s t er 10- 18 : r po r 3 : pe rip h era l pin se l e ct o u t p ut re gi st e r 3 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p7 r 4 rp7 r 3 r p7 r2 rp7 r 1 r p7 r0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p6 r 4 rp6 r 3 r p6 r2 rp6 r 1 r p6 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp7 r 4 : rp7 r 0 : peri phe ral o u tpu t fu nc tio n is as si gne d to r p 7 ou tput pin bi t s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 rp6r4:rp6r0: peripheral output function is assigned to rp6 output pin bits (see table 10-3 for peripheral function numbers)
pic24fj64ga004 family ds39881d-page 120 ? 2010 microchip technology inc. reg i s t er 10- 19 : r po r 4 : pe rip h era l pin se l e ct o u t p ut re gi st e r 4 u-0 u -0 u-0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ? ? ? r p9 r 4 rp9 r 3 r p9 r2 rp9 r 1 r p9 r0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p8 r 4 rp8 r 3 r p8 r2 rp8 r 1 r p8 r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp9 r 4 : rp9 r 0 : peri phe ral o u tpu t fu nc tio n is as si gne d to r p 9 ou tput pin bi t s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 rp8r4:rp8r0: peripheral output function is assigned to rp8 output pin bits (see table 10-3 for peripheral function numbers) reg i s t er 10- 20 : r po r 5 : pe rip h era l pin se l e ct o u t p ut re gi st e r 5 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p1 1r4 r p1 1r3 r p1 1r2 r p1 1 r 1 r p1 1 r 0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p1 0r4 r p 10r 3 r p10 r 2 r p10 r 1 r p1 0r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp1 1 r4 : r p 1 1 r 0 : peri phe ral ou tpu t fu nc tion is as si gne d to r p 1 1 o u t put pin bit s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bit 4-0 rp10r4:rp10r0: peripheral output function is assigned to rp10 output pin bits (see table 10-3 for peripheral function numbers)
? 2010 microchip technology inc. ds39881d-page 121 pic24fj64 ga004 family reg i s t er 10- 21 : r po r 6 : pe rip h era l pin se l e ct o u t p ut re gi st e r 6 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p1 3r4 r p 13r 3 r p13 r 2 r p13 r 1 r p1 3r0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p1 2r4 r p 12r 3 r p12 r 2 r p12 r 1 r p1 2r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp1 3 r4 :rp1 3 r 0 : perip he r al ou tput fun c t i on is ass i g ned to r p 13 ou tpu t pin bi t s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 rp1 2 r4 :rp1 2 r 0 : p erip he r al ou tput fun c t i on is ass i g ned to r p 12 ou tpu t pin bi t s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) reg i s t er 10- 22 : r po r 7 : pe rip h era l pin se l e ct o u t p ut re gi st e r 7 u-0 u -0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p1 5r4 r p 15r 3 r p15 r 2 r p15 r 1 r p1 5r0 bi t 15 bi t 8 u-0 u -0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p1 4r4 r p 14r 3 r p14 r 2 r p14 r 1 r p1 4r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp1 5 r4 :rp1 5 r 0 : perip he r al ou tput fun c t i on is ass i g ned to r p 15 ou tpu t pin bi t s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 rp1 4 r4 :rp1 4 r 0 : p erip he r al ou tput fun c t i on is ass i g ned to r p 14 ou tpu t pin bi t s (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers )
pic24fj64ga004 family ds39881d-page 122 ? 2010 microchip technology inc. reg i s t er 10- 23 : r po r 8 : pe rip h era l pin se l e ct o u t p ut re gi st e r 8 u-0 u -0 u-0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ? ? ?r p 1 7 r 4 (1 ) rp1 7 r3 (1 ) rp1 7 r2 (1 ) r p 17r 1 (1 ) rp1 7 r 0 (1 ) bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?r p 1 6 r 4 (1 ) rp1 6 r3 (1 ) rp1 6 r2 (1 ) r p 16r 1 (1 ) rp1 6 r 0 (1 ) bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp1 7 r4 :rp1 7 r 0 : perip h e r al ou tput fun c t i on is ass i g ned to r p 17 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 rp1 6 r4 :rp1 6 r 0 : perip h e r al ou tput fun c t i on is ass i g ned to r p 16 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) note 1: bits are only available on the 44-pin devices; otherwise, they read as ? 0 ?. reg i s t er 10- 24 : r po r 9 : pe rip h era l pin se l e ct o u t p ut re gi st e r 9 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p1 9r4 r p 19r 3 r p19 r 2 r p19 r 1 r p1 9r0 bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r p1 8r4 r p 18r 3 r p18 r 2 r p18 r 1 r p1 8r0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp1 9 r4 :rp1 9 r 0 : perip h e r al ou tput fun c t i on is ass i g ned to r p 19 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 rp1 8 r4 :rp1 8 r 0 : perip h e r al ou tput fun c t i on is ass i g ned to r p 18 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) note 1: bits are only available on the 44-pin devices; otherwise, they read as ? 0 ?.
? 2010 microchip technology inc. ds39881d-page 123 pic24fj64 ga004 family r e gi ste r 1 0 - 2 5 : r p o r 1 0 : pe r i ph er a l pi n se lec t ou t p ut re giste r 1 0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?r p 2 1 r 4 (1 ) rp2 1 r3 (1 ) rp2 1 r2 (1 ) r p 21r 1 (1 ) rp2 1 r 0 (1 ) bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?r p 2 0 r 4 (1 ) rp2 0 r3 (1 ) rp2 0 r2 (1 ) r p 20r 1 (1 ) rp2 0 r 0 (1 ) bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp2 1 r4 :rp2 1 r 0 : perip he r al ou tput fun c t i on is ass i g ned to r p 21 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 rp2 0 r4 :rp2 0 r 0 : p erip he r al ou tput func t i on is ass i g ned to rp 20 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) note 1 : bi t s are onl y a v a ila ble on the 44 -pin de vi ce s; o t he rw is e, th ey rea d a s ? 0 ?. regis t er 10-26 : r por 1 1: per iphe ral p i n s e le ct outpu t regis t er 1 1 u-0 u -0 u-0 r /w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?r p 2 3 r 4 (1 ) rp2 3 r3 (1 ) rp2 3 r2 (1 ) rp2 3 r1 (1 ) rp2 3 r 0 (1 ) bi t 15 bi t 8 u-0 u -0 u-0 r /w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?r p 2 2 r 4 (1 ) rp2 2 r3 (1 ) rp2 2 r2 (1 ) r p 22r 1 (1 ) rp2 2 r 0 (1 ) bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp2 3 r4 :rp2 3 r 0 : perip he r al ou tput fun c t i on is ass i g ned to r p 23 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 rp2 2 r4 :rp2 2 r 0 : p erip he r al ou tput func t i on is ass i g ned to rp 22 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) note 1 : bi t s are onl y a v a ila ble on the 44 -pin de vi ce s; o t he rw is e, th ey rea d a s ? 0 ?.
pic24fj64ga004 family ds39881d-page 124 ? 2010 microchip technology inc. regis t er 10-27 : r por 1 2 : p e r ip he ral pi n se lec t o u t p ut re giste r 1 2 u-0 u -0 u-0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ? ? ?r p 2 5 r 4 (1 ) rp2 5 r3 (1 ) rp2 5 r2 (1 ) r p 25r 1 (1 ) rp2 5 r 0 (1 ) bi t 15 bi t 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?r p 2 4 r 4 (1 ) rp2 4 r3 (1 ) rp2 4 r2 (1 ) r p 24r 1 (1 ) rp2 4 r 0 (1 ) bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : r ead as ? 0 ? bi t 12 - 8 rp2 5 r4 :rp2 5 r 0 : perip h e r al ou tput fun c t i on is ass i g ned to r p 25 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) bi t 7- 5 un im pl e m e n te d : r ead as ? 0 ? bi t 4- 0 rp2 4 r4 :rp2 4 r 0 : perip h e r al ou tput fun c t i on is ass i g ned to r p 24 ou tpu t pin bi t s (1 ) (s ee t a bl e 1 0 - 3 f o r p e rip hera l f unc tio n n u m bers ) note 1: bits are only available on the 44-pin devices; otherwise, they read as ? 0 ?.
? 2010 microchip technology inc. ds39881d-page 125 pic24fj64 ga004 family 11 . 0 t i m e r 1 th e t i m e r1 mo dul e is a 16 -bit tim e r w h i c h c a n serv e a s th e t i m e c o u n ter for the rea l -t im e cloc k (r tc), or o pera t e as a fre e -ru nni ng, i n te rva l tim e r/ co unte r . t i me r1 c an ope rate in thre e m o d e s: ?1 6 - b i t t i m e r ? 1 6-bit syn c h r ono us c oun ter ? 1 6-bit asy n c h ro nou s c o unt er t i me r1 a l so s upp ort s th ese fea t ure s : ? t i m e r g a te op erat ion ? s e l ec t a b l e pres ca ler setti ngs ? t i m e r o pera t io n du rin g c p u id le and sle ep mo de s ? i n t erru pt o n 1 6 -bi t peri od r egi ste r m a tc h o r fa ll ing edge of ext e rna l g a t e sig n a l fi gur e 1 1-1 pres en t s a b l o c k d i a g ram of th e 16 -bit t i m e r m odu le . t o c onf igu r e t i me r1 fo r op era t ion : 1. se t the t o n b i t ( = 1 ). 2. se lec t th e ti me r pres c a le r rati o us in g th e tckps1 :tckps0 bi t s . 3. se t the c l oc k a nd g a t i ng mo des us in g th e tc s an d tg a te b i t s . 4. se t or c l e a r th e tsyn c b i t t o c onf igu r e s y n c hr ono us or a s y n c h ron o u s o pera t io n. 5. lo ad th e tim e r pe rio d val u e i n to th e pr 1 re gis t er . 6. if in terru pt s are req u ire d , se t the in terru pt en abl e bi t, t 1 ie. use the pri o ri ty bit s , t1ip2 : t1 ip0, to s e t t he i n te rrup t pri o rit y . fig u r e 1 1 -1: 1 6 - b i t t i m e r1 m o d u le bloc k di agr a m note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 14. timers? (ds39704). to n sync so sc i sos c o/ pr 1 s e t t 1 if equal comp a r at or tm r 1 re s e t soscen 1 0 tsync q qd ck tc k p s 1 : tc kp s0 prescaler 1, 8, 64, 256 2 tg a te t cy 1 0 t1 c k tc s 1x 01 tg ate 00 ga t e sync
pic24fj64ga004 family ds39881d-page 126 ? 2010 microchip technology inc. regis t er 1 1 - 1 : t 1con: t i mer 1 control re g i ste r r/w - 0 u -0 r/w - 0 u -0 u-0 u -0 u-0 u -0 to n ?tsidl ? ? ? ? ? bi t 15 bi t 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 ? tgate tckps1 tckps0 ?tsynctcs ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 to n : t i m e r1 o n bi t 1 = s t a rt s 16-b i t t i m e r1 0 = s to p s 16- bit t i m e r1 bi t 14 un im pl e m e n te d : r ead as ? 0 ? bi t 13 ts i d l : s t op in idl e m o d e b i t 1 = d i s c onti nue m odu le ope rati on w h en dev ic e e n te rs i d le m ode 0 = c on t in ue mo dul e op era t io n in idl e m od e bit 12 - 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6 tg a t e : t i me r1 g at ed t i me ac cu mul ati on enab le bit w hen tc s = 1 : t h is bi t is ignored. when tcs = 0 : 1 = g at e d t i me ac cu mu l a t i on en a b l e d 0 = g at e d t i me ac cu mu l a t i on di sa b l e d bi t 5- 4 t ckps1:tckps0 : t i m e r1 inp u t cl oc k pre s c a l e sel e c t bi t s 11 = 1 : 256 10 = 1 : 64 01 = 1 : 8 00 = 1 : 1 bi t 3 un im pl e m e n te d : read as ? 0 ? bi t 2 t sync: t i m e r1 ext e rna l cl ock in put syn c h r oni za tio n se lec t b i t w hen tc s = 1 : 1 = syn c hr oni ze ex tern al c l o c k in put 0 = d o not synchronize external clock input when tcs = 0 : t h is bi t i s i gno red . bi t 1 tc s : t i m e r1 cloc k sou r c e sele c t bit 1 = exte rna l c l oc k from t1 ck pin (on the ris i n g e dge ) 0 = inte rnal c l oc k (f os c /2 ) bi t 0 un im pl emented: read as ? 0 ?
? 2010 microchip technology inc. ds39881d-page 127 pic24fj64 ga004 family 12 .0 t i me r2 / 3 and t i me r4 / 5 the t i mer2/3 and t i mer4/5 mo dules are 32-bit timers, w hich c an also be c onfigured as four inde pendent 16-bit tim ers w i t h select a ble operating m odes. as a 32-b i t tim e r , t i m e r2/ 3 a nd t i m e r4/ 5 o pera t e i n th ree mo des : ? t w o in dep en den t 16 -bit tim e rs (t i m e r 2 an d t i m e r 3 ) wi t h al l 1 6 - bi t op e r at i n g mo de s ( e xc ep t as yn ch rono us coun ter mo de) ? s i ngl e 3 2 -bi t ti me r ? s i ngl e 3 2 -bi t s y n c hr ono us counte r th ey al so su ppo rt th es e featu r es: ? t i m e r ga te o perat io n ? s el e c ta bl e p r es ca l e r s e t t i n g s ? t i m e r op erati o n dur ing idl e a nd s l ee p m ode s ? i n t erru pt o n a 32 -bit pe rio d re gis t er m a tc h ? a d c ev en t t r ig ger (t im er4 / 5 o n ly ) in div i d ual ly , a ll fo ur of t he 16 -bi t tim e rs ca n fun c ti on a s s y n c h r ono us ti me rs or c oun ters . the y al so of fe r th e fe atu r es li st ed abo ve , e x c ept fo r th e ad c eve n t t r i gge r; thi s i s im pl em ent ed o n ly w i th t i me r5. th e o perat in g m o d e s an d e nab led fe ature s are de term ine d b y se ttin g the ap pro p ria t e bi t(s) in t he t2c o n , t3c o n , t4 co n a n d t5 con re g i s t e r s. t2 con a n d t4 co n a r e s how n in ge neri c form in r egi st er 1 2 -1; t3c o n an d t5 c o n are sho w n i n r e g i s t er 1 2 -2 . fo r 32-b i t ti me r/c oun ter op era t ion , t i m e r2 a n d t i me r4 ar e t h e l e a s t si gn i f ic an t w o r d ; t im e r 3 an d t i me r 4 ar e th e m o s t s i gn ifi c a n t wo rd o f the 32 -bi t tim e rs . t o c onf igu r e t i me r2/3 or t i me r4/5 for 32-b it ope r ati o n: 1. se t the t3 2 bi t (t2 c o n < 3 > o r t4 c o n < 3> = 1 ). 2. se lec t th e p r es c a l e r r a tio fo r t i m e r2 or t i m e r4 us in g th e t c kps1:tckps0 bi t s . 3. se t the cl oc k a nd g a t i ng mo des us in g the tc s an d tg a t e bit s . if t c s is s e t to ext e rna l cloc k , rpinrx (t xck) m u s t be co nfig ure d to a n av ai l- ab le r p n pin . se e secti on 1 0 .4 ? p e r iphe ral pin sele ct? for mo re i n for m at ion . 4. lo ad th e tim e r p e rio d va lue . pr 3 (or pr 5) w i l l c ont ain th e mo st si gni fic a n t w o rd of the v a lu e w h il e p r 2 ( o r p r 4) co n t a i ns t h e l e a s t si g n i f ic an t wo rd . 5. if in terru pt s are req u ire d , se t the in terru pt en abl e bi t, t3i e o r t 5 ie; us e the p r io rity b i t s , t3 ip2:t 3 ip0 or t5i p 2:t5 ip0, to s e t t he in terru pt pr iori ty . n o te t hat w h il e t i me r2 o r t i m e r4 co n- tro l s t he ti me r , the i n te rrupt a ppe ars as a t i me r3 or t i m e r5 int e rrup t . 6. se t the t o n b i t ( = 1 ). th e tim e r va lue , at any poi nt, is sto r ed in th e reg i st er p a ir , tm r3:t mr2 (or tm r5:t mr4) . tm r3 (tm r 5) al w a y s c ont ain s th e m o st s i g n if ic ant w o rd of t he c o un t, w h i l e tm r 2 (tm r 4 ) c o n t ai ns th e l e as t si gni f ic an t w o r d . t o c onf igu r e a n y of t he t i m e rs for i n d i vi du al 1 6 -b it op era t io n: 1. c l e a r the t3 2 bit co rres p o ndi ng to tha t t i m e r (t2 c o n < 3 > for t i m e r2 an d t i m e r3 or t4 co n< 3> f o r t i m e r 4 an d t i m e r5). 2. se lec t th e ti me r pres c a le r rati o us in g th e tckps1 :tckps0 bi t s . 3. se t the cl oc k a nd g a t i ng mo des us in g the tc s an d tg a te bi t s . se e s e ct i o n 10 . 4 ? p er i p h e r a l pin sele ct? for mo re i n for m at ion . 4. load the tim e r period v a lue into the pr x register . 5. if in terru pt s are req u ire d , se t the in terru pt en abl e bi t, tx ie; us e the p r io rity b i t s , tx ip2:t x ip0 , to s e t t he i n te rrup t pri o rit y . 6. se t the t o n b i t ( t xco n <15 > = 1 ). note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i nten de d to be a com pr ehe nsi v e refer enc e source . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ? s ec tion 1 4 . t im e rs? (ds39 704 ). note : fo r 32-bit operation, t3con and t5con control bits are ignored. o n l y t2 c o n an d t4 c o n con t rol bi t s are use d f o r s e tu p an d c ont rol. t i m e r2 an d t i m e r4 c l oc k and ga te i npu t s a r e u t il iz ed fo r the 32 -bit tim e r m o d u le s, but an int e rrupt i s g ene rated w i th th e t i me r3 o r t i m e r5 int e rrup t fl ags .
pic24fj64ga004 family ds39881d-page 128 ? 2010 microchip technology inc. f i gu re 12 - 1 : t i m e r 2/ 3 an d t i me r4 /5 ( 3 2 - bi t ) blo c k di ag r a m tmr3 tmr2 s e t t3 i f ( t 5 i f) eq ual comparator pr 3 pr 2 res e t ls b ms b no te 1: t he 3 2 -bit t i m e r co nf igurat ion bit , t 32, m u st be set f o r 32-bit t i m e r/ c ount e r opera t ion. all cont r o l bit s ar e res pect i v e t o t he t 2 co n and t 4 co n regist ers. 2: t h is p e ri phe ra l? s in put s m u st be a s si gn ed t o a n av ai labl e rp n p i n be f o r e us e. p l ea se se e s ect i o n 1 0 .4 ?p e r iphe r a l pi n se le c t ? fo r m o r e in fo r m a tio n . 3: t he a dc event t r igger i s av ai lable only on t i m e r2/ 3 . dat a b u s<15: 0> t m r3hld r ead t m r 2 (t mr 4) (1 ) writ e t m r 2 (t mr 4) (1 ) 16 16 16 q qd ck tgate 0 1 to n tc kp s1 : t c k p s 0 prescaler 1, 8, 64, 256 2 t cy tc s (2) tgate (2) gate t2ck sy n c a dc event t r igger (3 ) sy n c (t 4ck ) (pr5 ) ( pr4) (t mr 5 h l d ) (t mr5) (t mr4 ) 1x 01 00
? 2010 microchip technology inc. ds39881d-page 129 pic24fj64 ga004 family fig u r e 1 2 -2 : t i m e r 2 an d t i m e r 4 (1 6-b i t s y n c h r o no us ) b l oc k di agr a m figure 12-3: timer3 and timer5 (16-bit synchronous) block diagram to n tc k p s 1 : tc kp s0 prescaler 1, 8, 64, 256 2 t cy tcs (1) 1x 01 tgate (1) 00 gate t2 c k sync pr2 (pr4) s e t t 2 if ( t 4 i f ) e qual com p arat or t mr 2 (t mr 4 ) res e t q qd ck tga t e 1 0 (t 4ck) sy nc no t e 1: t h is pe rip h e r al ? s inp u t s m u s t b e as s i gne d t o a n av aila ble rp n pi n be f o re us e. pl eas e s e e se ct io n 1 0 .4 ? p e r iphe r a l pin se le c t ? f o r mor e in f o rma t i o n . ton t c k ps1: t c k p s 0 2 t cy tcs (1) 1x 01 tg a te (1 ) 00 t3 c k pr 3 (pr 5 ) s e t t3 i f ( t 5 i f) equal c o mp arat or t m r3 (t mr5) re s e t q q d ck tg a t e 1 0 adc event trigger (2) (t 5 c k ) pr e s ca l e r 1, 8, 64, 256 sy n c no t e 1: t h is p e r i phe ra l? s in pu t s m u st be a s si gn ed t o a n av a ilab l e rp n p i n be f o r e us e. p l ea se se e s ect i o n 1 0 .4 ?p e r iphe r a l pi n s e le c t ? f o r mo re i n f o rma t i on . 2: t he adc event t r igger i s av ai lable only on t i m e r3.
pic24fj64ga004 family ds39881d-page 130 ? 2010 microchip technology inc. regis t er 12-1: txcon: t i mer 2 and t i m e r4 control regis t er r/ w - 0 u -0 r/w - 0 u -0 u-0 u -0 u-0 u -0 to n ?tsidl ? ? ? ? ? bi t 15 bi t 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 ? tgate tckps1 tckps0 t32 (1) ?tcs (2) ? bi t 7 bi t 0 leg e nd : r = r e ada bl e bi t w = w r it abl e bi t u = u n im ple m e n ted bi t, re ad as ?0? -n = v a lu e at po r ? 1? = bit is se t ? 0? = bi t i s c l e a red x = bi t is u n kn own bi t 15 to n : ti m e r x o n b i t when txcon<3> = 1 : 1 = s t a rt s 3 2 -bi t t i m e rx /y 0 = s top s 3 2 -b it t i me rx/y when txcon<3> = 0 : 1 = s t a rt s 1 6 -bi t t i m e rx 0 = s top s 1 6 -b it t i me rx bi t 14 unim ple m en ted: r e ad as ? 0 ? bi t 13 tsi d l : s t op in idle m ode bi t 1 = d i s c o n tin u e mo dul e o pera t io n w h e n d e v i c e en ters id le mo de 0 = c ont inu e m o d u le op erati o n in idl e m ode bi t 12 -7 unim ple m en ted: r e ad as ? 0 ? bit 6 tgate: timerx gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = g ate d ti me ac cu mu lat i on en abl ed 0 = g ate d ti me ac cu mu lat ion di sa ble d bi t 5-4 tckps1 :tckps0: t i m e r x i n p u t cl oc k p r es ca l e s e le ct b i ts 11 = 1:2 56 10 = 1 : 64 01 = 1 : 8 00 = 1 : 1 bi t 3 t3 2: 32 - b i t t i me r mo de s e l e ct bi t (1 ) 1 = t im erx a nd t i me ry form a sin g l e 32 -bi t tim e r 0 = t im erx a nd t i me ry ac t as tw o 16-b i t t i m e rs in 32 -bit mo de, t3c o n c ontr o l b i t s d o no t af fe ct 3 2 -b it ti me r op era t ion . bi t 2 unim ple m en ted: r e ad as ? 0 ? bi t 1 tcs: t i m e rx c l oc k source sele ct bit (2 ) 1 = ex tern al cl oc k fr om pin , tx c k (on th e ris i n g e dge ) 0 = in tern al cl ock (f os c /2) bi t 0 unim ple m en ted: r e ad as ? 0 ? note 1 : in 32-b i t m o d e , t he t3c o n or t 5 c o n co ntro l b i t s do no t af fec t 3 2 -bi t ti me r op erat ion . 2: if t c s = 1 , r p i n r x ( t x c k ) mu st be co n f i g ur e d t o an avai l a b l e r p n pi n . f o r m o r e in f o rm at i o n, se e sec t ion 10.4 ? periphe ral pi n sel ect? .
? 2010 microchip technology inc. ds39881d-page 131 pic24fj64 ga004 family regis t er 12-2: t y con: t i m e r3 and t i me r5 co n t ro l r e gis t er r/w - 0 u -0 r/w - 0 u -0 u-0 u -0 u-0 u -0 ton (1) ?tsidl (1) ? ? ? ? ? bi t 15 bi t 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 ?tgate (1) tckps1 (1) tckps0 (1) ? ?tcs (1,2) ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 to n : t i m e ry o n b i t (1 ) 1 = s t a rt s 16-b i t t i m e ry 0 = s t ops 1 6 - bi t t i me r y bi t 14 un im pl e m e n te d : r ead as ? 0 ? bi t 13 ts i d l : s t op in idl e m o d e b i t (1 ) 1 = d i s c o n ti nue m odu le ope rati on w h en dev ic e e n te rs i d le m ode 0 = c on t in ue mo dul e op era t io n in idl e m od e bit 12 - 7 un im pl e m e n te d : r ead as ? 0 ? bi t 6 tg a t e : t i me ry ga ted t i m e ac cu mu lat i on ena b le bi t (1 ) w hen tc s = 1 : t h is bit is ignored. when tcs = 0 : 1 = g at e d t i me ac cu mu l a t i on en a b l e d 0 = g at e d t i me ac cu mu l a t i on di sa b l e d bi t 5- 4 t ckps1:tckps0 : t i m e ry inp u t c l oc k pr esc a l e se lec t b i t s (1 ) 11 = 1 : 256 10 = 1 : 64 01 = 1 : 8 00 = 1 : 1 bi t 3- 2 un im pl e m e n te d : r ead as ? 0 ? bi t 1 tc s : t i me r y c l oc k s o ur c e s e le ct b i t (1 , 2 ) 1 = e x t e r nal cl oc k f r om pi n t y c k (o n th e ri si ng e dge ) 0 = i nter nal cl oc k (f os c /2) bi t 0 un im pl e m e n te d : r ead as ? 0 ? note 1 : w hen 32- bit ope rati on is ena ble d (t 2c o n <3> or t4 c o n < 3> = 1 ), t hes e b i t s ha ve no ef fec t on t i m e ry o pera t io n; a ll tim e r f unc tio n s are se t th roug h t2 c o n and t4c o n . 2: if tcs = 1 , rpinrx (txck) must be configured to an available rpn pin. see section 10.4 ?peripheral pin select? for more information.
pic24fj64ga004 family ds39881d-page 132 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 133 pic24fj64 ga004 family 13 .0 inpu t captu re figure 13-1: input capture block diagram note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i nten de d to be a com pr ehe nsi v e refer enc e source . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ? s ec tion 1 5 . i nput capture ? (d s3 970 1). icxbuf icx pi n i c m< 2 : 0> ( i c x c o n < 2:0> ) mode select 3 10 set fl ag icxif (in ifsn register) tmry tmrx e dge d e t e cti o n l ogi c 16 16 fifo r/w lo gi c ici<1:0> ic ov , icbne ( i cxcon<4 : 3 > ) ic x c o n interrupt logic system b u s from 16- b i t t i me rs ict m r ( i cxcon<7 > ) fi fo p r e scaler co u n te r ( 1 , 4, 1 6 ) an d c l o ck s yn chr oni z e r no t e 1: an ? x ? in a signal, regist er or bi t nam e denot es t he num ber of t he capt ure channel. 2: t h is peripheral? s i n puts must be assigned to an available rpn pin before use. please see section 10.4 ?peripheral pin select? for more information.
pic24fj64ga004 family ds39881d-page 134 ? 2010 microchip technology inc. 13. 1 i nput capt ure regist ers regis t er 13-1: icx c o n : i n put c a pture x co n t ro l regis t er u-0 u -0 r/w - 0 u -0 u-0 u -0 u-0 u -0 ? ?icsidl ? ? ? ? ? bi t 15 bi t 8 r/w - 0 r /w -0 r/w -0 r -0 , hc r-0 , hc r/w -0 r /w -0 r/w -0 ictmr i ci1 i ci0 i co v i cbne i c m 2 (1 ) icm1 (1 ) icm 0 (1 ) bi t 7 bi t 0 le gen d : hc = ha rd wa re cl e a ra b l e b i t r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 4 un im pl e m e n te d : read as ? 0 ? bi t 13 ic s i d l : in put capt ure x m o d u le s t op in i d le co n t rol bit 1 = in put ca ptu r e m odu le will ha lt i n c p u i dle mo de 0 = in put ca ptu r e m odu le will co nti nue to ope rate in cp u idl e m o d e bi t 12 - 8 un im pl e m e n te d : read as ? 0 ? bi t 7 ic t m r : i n p u t ca pt u r e x t i me r s e l e ct bi t 1 = tm r 2 c o n t en t s are c a p t ure d o n c apt ure eve n t 0 = tm r 3 c o n t en t s are c a p t ure d o n c apt ure eve n t bi t 6- 5 ic i 1 : i c i 0: sel e c t nu m b e r of c aptu r es pe r int e rrup t bi t s 11 = int e r r up t on ev er y fo u r t h ca p t ur e ev en t 10 = int e r r u p t on ev er y th i r d c a p t ur e ev en t 01 = int e r r u p t on ever y se co nd ca p t u r e even t 00 = int e r r u p t on ev er y ca pt u r e e v e n t bi t 4 ic o v : inp u t c a pture x ov erf l ow s t a t us fl ag b i t (read -onl y) 1 = in put ca ptu r e ov erf l ow o c c u rre d 0 = n o inp u t c a p t ure ov erfl ow oc c u rred bi t 3 ic b n e : inp u t c a pture x buf f er em pt y s t a t us bi t (rea d -o nly ) 1 = in put ca ptu r e bu f f e r is n o t e m p t y , a t le as t on e m o re ca ptu r e v a lu e c a n be read 0 = in put ca ptu r e bu f f e r is e m p t y bi t 2- 0 ic m 2 :i c m 0: inp u t c a ptu r e x m ode sele ct bi t s (1 ) 11 1 = i npu t cap t ure f unc tio n s a s in terru pt pi n onl y w h e n dev ic e is in sle ep o r id le m o d e ( r is ing e d ge d e te ct onl y , al l o t he r co ntro l b i t s are no t ap pli c a b le ) 11 0 = u n u s ed ( m o dul e d i sa bl ed) 10 1 = c a p tu re m o d e , e v er y 1 6 th ris i ng ed ge 10 0 = c a p tu re m o d e , e v er y 4 t h ri si ng edg e 01 1 = c a p tu re m o d e , e v er y ri si ng edg e 01 0 = c a p tu re m o d e , e v er y fa ll ing ed ge 00 1 = c a p tu re m ode , ev ery ed ge (ri si ng a nd f a ll ing ) ? ic i < 1:0 > bi t s do n o t c ont rol i n te rrupt gen era t ion for th is mo de 00 0 = i npu t c aptu r e m o d u le tu rned of f note 1 : r p in r x (ic x r x ) m u s t b e c onf igu r ed to a n a v ai la ble rp n p i n. for mo re i n form at ion , s ee secti o n 1 0.4 ? p eriph e ral pin se lect? .
? 2010 microchip technology inc. ds39881d-page 135 pic24fj64 ga004 family 1 4 .0 outp u t c o mp are 14. 1 s et up f o r sing le o u tput pul se gener a ti on w hen the o c m co ntro l b i t s (o c x c o n < 2 : 0> ) are s e t to ? 100 ?, th e se lec t ed outp ut c om p are c ha nne l in iti ali ze s the ocx p i n to the l ow s t ate and gen erat es a si ngl e ou t p ut pu l s e . t o g ene rate a s i n g le ou tpu t pu ls e, th e fo ll ow in g s t ep s a r e requ ired (t hes e st ep s a s s u m e the ti me r s o u r ce i s i n it ial l y turn ed o f f , bu t thi s i s n o t a req u ir em ent for th e m o d u le op erati o n ) : 1. de te r m i n e th e i n s t r u c t io n cl o ck cy cl e t i m e . t a ke in t o ac co u n t t h e fr e q u e n cy of t h e ex t e r n al c l o c k to t he ti me r s o u r ce (i f one i s us ed) a nd th e tim e r pr e s c a le r se t t i n gs . 2 . c a lc ul at e t i m e to the ri si ng e dge o f th e ou tpu t p u l s e re la ti ve to th e tm ry s t ar t v a l u e (0 00 0h ). 3 . c a lc ul at e th e ti m e to the fa ll in g ed ge of t h e pul s e ba se d on t h e d e s i r e d pu ls e w i dt h an d t h e t i me to t he ris i ng ed ge o f t he pu ls e. 4. w r i t e th e v al u es c om pu t ed in s t eps 2 an d 3 a bove i n to the o u tp ut c o mp are x regi ste r , o c xr , a nd the o u tput c o mp are x se con da r y re gist er , o c xr s, resp ec tive l y . 5. s et t i m er p er i od r e g i s t er , p r y , t o v al u e eq u al t o or g r ea t e r t h a n v a l u e i n oc x r s , t h e ou t p u t c o m p are x se con d a r y re gis t e r . 6 . se t th e o c m bi t s to ? 100 ? an d th e o c ts el ( o cxcon<3 > ) b i t t o t h e d e si re d t i me r so u r c e . t he o c x pi n s t ate w i ll no w b e dri v e n lo w . 7. s e t th e ton ( t yc on < 1 5 > ) b i t to ? 1 ?, w h i c h e n a b l e s th e co m p a r e tim e ba s e t o c o unt . 8 . u p on the fi rs t ma tc h b e t w ee n tm r y an d o c x r , t he o c x pi n w i ll b e dri v e n hi gh . 9 . w h e n t h e in c r em en ti ng ti me r , tm r y , m a tc he s th e o u tpu t c o mp ar e x se co nd ary re gi s t er , o c x r s, t he s e co nd an d tra i l i n g e d g e (h ig h-t o -l ow ) o f th e pu ls e is dr iv en on to th e oc x p i n . n o ad di ti on al pu ls es ar e dr iv en on t o t h e oc x pi n a n d i t r e ma in s at lo w . a s a r e s u l t of th e se co nd c o m p a r e mat c h e v e n t , th e o c x i f i n ter r upt fl ag b i t is set , w h ic h w i ll re sul t in a n in terru pt if it is ena bl ed, b y s e t- ti ng th e oc x i e bi t. for fu rther i n for m at ion o n p e rip hera l int e rrup t s , re fer to secti o n 7 .0 ? i nte r ru pt contro ller? . 10 . t o i n i t i a t e an ot h e r s in g l e pu lse o u t p ut , ch an ge t h e t i me r an d c om p are reg i s t e r se tti ng s, i f ne ed ed , an d th en i ssu e a w r i t e t o set t h e o c m b i ts t o ? 100 ?. d i sa bl in g a nd re -e na bl in g of t h e t i m e r a n d cl ea r- i n g th e tm r y re gi st er ar e no t r equ ir ed , b u t m a y be ad va ntag e o u s f o r de f i n i n g a pu ls e f r om a k n o w n ev en t t i m e bo un da ry . th e o utp ut c om p a r e m od ule do es no t ha ve to be dis - ab le d af te r t he fa lli ng ed ge o f t he ou tpu t pul se. an oth e r pu ls e can b e i n it iat ed by rew r i t in g t he va lue o f th e ocx c on reg i st e r . 14. 2 s et up f o r conti nuous output pul se gener a ti on wh en the o c m co ntrol b i t s (o c x c o n < 2 : 0>) are s e t to ? 101 ?, th e se lec t ed o u tp ut c o mp are c h a nne l in iti a li ze s th e o c x pin to the lo w st ate an d ge ne rates o utp ut pu ls es on eac h and ev ery co mp are ma tch ev en t. fo r the u s e r to c onfi gur e the mod u l e for th e ge nera tio n of a co ntin uo us s t rea m o f outp ut p uls es , the f oll ow in g s t ep s a r e re qu ired (th ese s t ep s a s s um e t he t i m er s ourc e i s in iti a ll y tu rned of f, bu t this is not a requ ire m e n t fo r the m odu le ope rati on): 1. d e t e rm ine th e ins t ru cti on c l oc k c y c l e ti me. t a k e in t o ac co u nt t h e fr e q ue n c y of t h e ex t er n al c l o c k to t he tim e r s our ce (i f o ne i s us ed) a nd the t i m e r pr esc a l e r s e tt ing s . 2 . c a lc ul at e t i m e t o t he ri si ng ed ge o f th e out pu t p u l s e re la tiv e to th e tm ry st art v a l u e (0 00 0h) . 3 . c a lc ul at e th e ti m e to the fa ll in g ed ge of t h e p u l s e bas ed on th e de si red p u l s e w i d t h an d the ti m e t o th e ris i ng ed ge o f th e pu ls e. 4. w r it e t h e va lu es co mp ut ed i n st ep 2 an d 3 ab ove i n to t he o u tp ut c o mp ar e x r egi s t er , o c x r , an d t h e ou tp ut c o mpar e x s e co nd ar y r e gi st e r , ocxrs , r e sp ect i vel y . 5 . se t t i me r per i o d re gi st er , p r y , to va lu e e qua l t o o r g r ea te r th an v a l u e in o c x r s. 6 . se t th e o c m b i t s t o ? 101 ? an d t h e o c tsel bi t t o th e de si red ti m e r so urc e . th e oc x p i n s t a t e w i l l no w be d r ive n l o w . 7 . en ab le th e c o m p are ti m e b a s e b y se tti ng th e t o n (t y c o n < 1 5 > ) bi t t o ? 1 ?. 8 . u p on the fi rst ma tc h b e t w ee n tm r y an d o c x r , th e o c x pi n w i ll b e d r i v e n hi gh . 9. whe n the comp ar e t i me base , tmr y , mat c hes th e oc xr s , the seco nd and tr ail i ng edge ( h igh - t o -l ow ) of the pu lse i s dr iven ont o t he oc x p in. 10 . a s a r e su lt of th e s e c o n d co mpar e m a t c h ev en t, th e o c xi f i n t e rru pt fl ag bi t se t. 1 1 . w he n the c o mp ar e tim e b a s e an d th e va lu e in it s re s p ec ti v e t i m e r peri od reg i s t e r m a tc h, t h e t m ry re gi s t er re se t s to 0x0 000 a n d r e su me s co un ti ng . 1 2. s te p s 8 thr ou gh 1 1 a r e r ep ea t ed an d a c on t in uo us s t re am o f pu ls es is g e n e ra te d in de fin i t e l y . th e ocxi f f l a g is se t o n ea ch ocxrs / t m ry com p a r e ma tc h ev en t. note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i nten de d to be a com pr ehe nsi v e refer enc e source . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ? s ec tion 16. o u tpu t c o m p ar e ? (d s3 970 6).
pic24fj64ga004 family ds39881d-page 136 ? 2010 microchip technology inc. 14. 3 p ul se-w i d t h modul ati on mode th e fol l ow i ng s t ep s sh ou ld be t a ke n w hen c o n f ig urin g th e o u tp ut c o m p a r e m odu le for p w m ope rati on: 1. s e t t h e p w m p e r i o d by w r i t in g t o th e se l e c t ed t i m e r peri od regi s t e r (pry ). 2 . se t th e p w m du ty cy c l e by w r i t in g t o th e o c x r s re gi s t er . 3. w r it e th e oc xr r e gi st er w i th t h e i n i t i a l d u t y c ycl e. 4 . en ab le i n t e rru pt s, i f req u i r ed , for t he ti m e r an d o utp ut c om p are m od ul es . th e out pu t co mp ar e in te r r up t i s re qu ir e d f or p w m f au l t pi n ut i l i z at i on . 5 . c o nfig ure t he ou tpu t co mp are m odu le f or one of t w o p w m op er a t io n mo de s b y w r it i n g t o t h e o utp ut c om p a r e mo de bi t s , o c m < 2: 0> (ocx con<2 : 0 > ) . 6 . se t th e tm r y pre s ca le va lu e a nd e n a b l e th e ti m e ba se b y se tt i n g ton ( t xcon< 1 5 > ) = 1 . 14. 3.1 p w m pe rio d th e pwm pe riod i s spe c i f ie d b y w r iti ng to pr y , th e t i me r peri od regi st er . t he pwm pe riod ca n b e c a l c ul ate d u s in g eq uat ion 1 4 - 1. equa tion 1 4 -1: calculatin g th e p w m pe rio d (1) 14. 3.2 p w m dut y c y cl e th e pwm du ty c y c l e is s p e c i f ie d b y w r iti n g to th e oc x r s r e g i st er . t h e oc xr s r e gi st e r ca n be w r i t t e n t o at a n y ti me , but th e dut y cy cl e va lue i s no t lat c he d in to o c xr un til a m a tc h betw e en pr y an d tm r y oc cur s (i .e., the p e ri od i s c o m p l e te ). thi s p r ov id es a do ubl e bu f f e r for th e pwm du ty c y c l e a nd i s es s e nti a l f o r gl itc h - l ess pw m ope rati on. in th e pw m mo de, o c xr i s a re ad-o n ly re gis t er . s o m e im po r t an t bo u n d a r y par a m e t er s of t h e p w m d u ty cy cl e i n cl ud e : ? if th e o u tpu t c o mp are x regi ste r , o c x r , is l oad ed w i t h 0 000 h, th e o c x pin wi l l re ma in low (0 % d u ty cy cl e) . ? if o c x r is gre a te r th an pry (t i m e r peri od re gis t er), the pi n w i l l re ma in hig h (1 00% du ty cy cl e) . ? if o c x r is eq ua l to pry , th e o c x pin wil l be lo w fo r one ti me ba se co unt va lue an d hi gh for a l l ot her co unt va lue s . se e ex am ple 1 4 - 1 fo r pwm m ode tim i n g d e t a ils . t abl e 1 4-1 s ho w s e x am pl e pw m fre que nc ies an d re sol u ti ons fo r a d e v i c e o pera t in g a t 10 mi ps. equa tion 1 4 -2: calculation for m a x i m u m p w m r e so luti o n (1 ) note: this peripheral co n t ai n s i n pu t a n d ou t pu t fu nc tio ns t hat m ay nee d to b e co nfi gure d by t h e pe r i ph er a l pi n s e l e ct . s e e se ction 1 0 . 4 ?pe r i pher a l pin se lect? for m o re in form ati on. note : th e o c x r regi ste r sho u l d be in iti a li ze d be f o re t h e o u t p u t c o mpar e mo du l e i s f i r s t e nab led . the oc x r r egi ste r bec om es a r ea d -o nl y d u ty c y c l e r egi ste r w he n th e m o d u le i s o pera t ed i n th e pwm mod e s . th e va lu e hel d in o c xr w i l l bec om e th e pw m duty c y c l e f o r t he firs t p w m pe riod . th e c o n t en t s of t he ou tpu t c o m p a r e x s e c o n d a r y r e gi st e r , oc xr s , w i l l no t be tra n s f erre d i n to o c x r unt il a tim e b a s e pe r i od ma t c h oc cu r s . note : a pr y v a l ue o f n w i ll p r od uce a pwm pe rio d of n + 1 ti me bas e c o u n t c y c l es . fo r ex am pl e, a va lue of 7 w r itte n in to t h e pr y re gis t er w ill y i el d a pe riod c ons is tin g o f 8 t i m e base cycles. pwm period = [(pry) + 1] ? t cy ? (timer pr escal e v a l u e) pw m f r equ e n c y = 1/ [ p w m p e r i od] wh e r e : note 1 : bas ed on t cy = 2 * t os c , d o ze mo de a n d p l l a r e d i s a bl ed . ( ) m a x i m u m p w m re so lu tion (b its) = f cy f pw m ? (tim er p r e s cal e v a l u e ) lo g 10 log 10 (2 ) bi ts note 1: based on f cy = f osc /2, doze mode and pll are dis ab l ed .
? 2010 microchip technology inc. ds39881d-page 137 pic24fj64 ga004 family ex amp l e 14-1: pw m pe riod and duty c y cle calculations (1) t able 1 4 -1: e x a mp le pw m fre q uen c ies and res o lutions a t 4 mi ps (f cy = 4 mh z) (1 ) table 14-2: example pwm frequencies and resolutions at 16 mips (f cy = 16 mhz) (1) pwm fr e quen c y 7 .6 h z 6 1 hz 122 hz 97 7 h z 3.9 kh z 3 1 . 3 k h z 1 2 5 k h z t i m e r p r e s c a l e r ra t i o 81 111 11 pe riod reg i s t er v a l u e ffffh fff fh 7 fffh 0fff h 0 3 ffh 0 07f h 001 fh r e sol u ti on (bit s) 16 1 6 15 12 1 0 7 5 note 1 : ba se d on f cy = f os c /2, do z e m o d e an d pl l a r e d i sa bl ed. pwm fr e quen c y 3 0.5 h z 2 44 h z 488 hz 3 . 9 k h z 15. 6 kh z 125 kh z 5 0 0 k h z t i m e r p r e s c a l e r ra t i o 81 111 11 pe riod reg i s t er v a l u e ffffh fff fh 7 fffh 0fff h 0 3 ffh 0 07f h 001 fh r e sol u ti on (bit s) 16 1 6 15 12 1 0 7 5 note 1 : ba se d on f cy = f os c /2, do z e m o d e an d pl l a r e d i sa bl ed. 1 . f i nd th e t i mer p e r i od r e g i st er val u e f o r a desi r e d pw m f r e q u e n cy o f 52. 0 8 khz , wh er e f osc = 8 mhz wit h pll (3 2 m h z dev i ce cl oc k rat e ) and a t i mer2 p r escal e r se t t i n g of 1: 1 . t cy = 2 * t o sc = 62 .5 ns p w m p e r i od = 1 / p w m f r equ e n c y = 1 / 52 .0 8 khz = 1 9. 2 ? s pwm pe rio d = (pr2 + 1 ) ? t cy ? (t i m er 2 p r esca l e v a l u e) 19 .2 ? s = ( p r 2 + 1) ? 62 . 5 ns ? 1 pr2 = 30 6 2 . f i nd t h e max i mum resol u t i on o f t h e d u t y cycl e t h at can b e used wi t h a 52 . 0 8 khz frequen c y an d a 32 m h z d e vi ce cl ock r a t e : pwm re solu tio n = l o g 10 (f cy /f pwm )/l o g 10 2) bi t s =( l o g 10 ( 1 6 m h z / 52 . 08 k h z) / l og 10 2) bi t s = 8 .3 bi ts no t e 1 : bas ed o n t cy = 2 * t os c , d o z e m o d e an d pl l a r e d i s abl ed.
pic24fj64ga004 family ds39881d-page 138 ? 2010 microchip technology inc. f i g ure 14- 1: o u t p ut c o m p are module block dia g r a m c o mp arat or output logic q s r ocm2:ocm0 o u t put enable ocx (1) set flag bit ocxif (1) oc x r s (1) mode select (4) 3 no te 1: w here ?x? is shown, r e f e re nce is m ade t o t he r egist er s a ssoc i at ed wi t h t he respec t i ve out pu t compare c hannels 1 t h rough 5. 2: o c f a pin c ont r o l s o c 1-o c 4 channels . o c f b pin cont rols t he o c 5 ch annel . 3: ea ch out p u t com p are c hannel can use on e of t w o select able t i m e bases. ref e r t o t he device dat a s heet f o r t h e t i me bases as sociat ed wit h t he m odule. 4: this peripheral?s inputs and outputs must be assigned to an available rpn pin before use. please see section 10.4 ?peripheral pin select? section for more information. octsel 0 1 16 16 ocfa or ocfb (2) t m r regist er i nput s f r om t i m e bas es (se e no te 3 ). period mat c h signals f r om t i me bases (see no t e 3 ). 0 1 ocxr (1)
? 2010 microchip technology inc. ds39881d-page 139 pic24fj64 ga004 family 14. 4 o ut put com p are regi ster re gi ste r 1 4 - 1 : ocx c on: outp u t com p are x contro l regis t er u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?ocsidl ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 r-0, hc r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? o cf l t oct sel ocm 2 (1 ) ocm1 (1 ) oc m 0 (1 ) bi t 7 bi t 0 le gen d : hc = ha rd wa re cl e a ra b l e b i t r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 4 un im pl e m e n te d : r ead as ? 0 ? bi t 13 ocsi dl : s t op o u t put c o m p are x in idl e m ode c o n t rol bit 1 = o u t put c om p are x w ill ha lt i n c p u i dle mo de 0 = o u t put c o m p are x w ill co nti nue to ope rate in c p u idl e m o d e bi t 12 - 5 un im pl e m e n te d : read as ? 0 ? bi t 4 ocf l t : pwm fa ult cond iti on s t a t us bi t 1 = p w m faul t c ond iti on has oc c u rred (c lea r ed in h w on ly ) 0 = n o pwm fa ult co ndi tio n ha s occu rre d (t his bi t i s o n ly us ed wh e n o c m< 2:0> = 111 ) bi t 3 octsel: o u tpu t co m p are x t i me r sel e ct bi t 1 = t i m er3 is the cl oc k s ou r ce for o u tput c om p are x 0 = t i m er2 is the cl oc k s ou r ce for o u tput c om p are x r e fer t o th e d e v i ce da t a s h e e t f o r s pecif ic tim e b a s e s av ail abl e t o th e ou tpu t c o m p are m o du le. bi t 2- 0 ocm2 :ocm 0: o u tp ut c o mp are x m o d e se lec t b i t s (1 ) 11 1 = p w m mo de o n o c x, fau l t pin, o c fx, ena bl ed (2 ) 11 0 = p w m mo de o n o c x, fau l t pin, o c fx, dis ab l ed (2 ) 10 1 = i nit i al iz e o c x p i n low , ge nera t e c o n t in uou s o u tp ut p u ls es on o c x p i n 10 0 = i nit i al iz e o c x p i n low , ge nera t e s i n gle ou tpu t pu ls e on o c x p i n 01 1 = c o m p are ev ent tog gle s o c x pin 01 0 = i n i ti a l i z e oc x pi n h i gh , c o mpar e ev en t fo r c es o c x p i n lo w 00 1 = i nit i al iz e o c x p i n low , co mp are ev ent forc es o c x p i n hig h 00 0 = o u t put co mp are ch ann el is dis a b led note 1 : r p o r x (oc x ) m u s t be co nfi gured to an av ai lab l e r p n pi n. f o r m o re in form ati o n, se e se ction 1 0 . 4 ? p eriph e ral pin se lect? . 2: o c f a p in co ntro ls oc 1 - oc 4 ch an nels. oc fb pin co ntro ls the o c 5 chan nel.
pic24fj64ga004 family ds39881d-page 140 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 141 pic24fj64 ga004 family 1 5 .0 ser ia l pe ri ph er a l inte r f ace ( s p i ) th e se ria l per i ph eral int e rfa c e (spi) m odu le is a s y n c h r ono us se ria l i nte rfac e u s e f ul for co mm un ic atin g w i th othe r p e ri phe ral or m i cr oco n tro l l e r d e v i c e s . t hes e p e rip hera l dev ic es m a y be se rial eep r o m s , s h if t re g- i s te rs, d i s p la y dri v e r s, a/ d co nve r ters , et c. th e spi m o d u le is co mp ati b le w i th mo toro la? s spi an d sio p i n ter f ac es . th e m odu le s upp ort s ope rati on i n tw o bu f f e r m o d e s . in s t an da rd m o d e , dat a is s h if t ed thro ug h a s i n g le s e ria l b u f f e r . in enha nc ed buf f er mo de, da t a i s sh if te d t h r o ug h an 8- l e ve l f i fo bu f f e r . th e mod u l e a l s o s u p port s a ba si c fram ed spi prot oco l w h ile o p e r ati ng in eit her m a s t er o r s l av e m ode . a tot a l o f fou r fra m e d spi co nfig ura t ion s are s u p por ted. th e spi se rial in terfa c e co ns is t s of fo ur p i n s : ? s dix : se rial dat a in put ? s d o x: seri al d a t a ou tput ? s c k x : shi f t c l oc k i npu t or ou tpu t ? ssx : ac tiv e -l ow sla v e sel e c t or fram e sy nc hron iz ati on i / o pul s e th e spi m o d u l e c a n b e c o n f ig ured t o o per ate us in g 2, 3 or 4 pi ns. in th e 3-pi n mod e , ssx is n o t us ed. in th e 2- pin mode, both sdox and ssx are not us ed. bl ock di agra m s of th e mo dul e in s t a nda rd an d en han ce d m ode s a r e s ho w n in fig ure 15- 1 an d fi gur e 1 5 - 2. d epending on t he pi n c oun t, de vic es of th e pic 2 4fj 64g a0 04 fam i l y of fer on e o r t w o spi m o du le s on a sin g l e de vi ce . note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i nten de d to be a com pr ehe nsi v e refer enc e source . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ? s ec tion 23. ser i a l pe r i phe r a l i nter f ac e (spi )? (d s3 969 9) note : do n ot perform re ad-m o d i fy -write ope ra- ti ons (s uc h as bi t-ori ent ed ins t ru cti ons ) o n th e s p ixbu f reg i s t er in eit her s t and ard or en han ce d bu f f e r mo de. note : in th is s e c tion, the spi m o d u le s are re ferre d to toge the r as spix or s e p a r ate l y as spi1 and s p i2. s p e c ia l fu nc tio n r e g- is te rs w ill f o ll ow a s i m i l a r not atio n. for ex am pl e, spix c on 1 o r spixc o n 2 ref e rs to th e co ntrol re gi ste r fo r t he spi1 or spi2 m odu le .
pic24fj64ga004 family ds39881d-page 142 ? 2010 microchip technology inc. t o s e t u p the spi m odu le fo r the s t and ard m a s t er m o d e o f op erat ion : 1 . if us ing in terru pt s : a ) c l ear the spixi f bi t i n th e re sp ect i v e if s x re gis t er . b ) se t th e spix i e b i t in the re sp ec tiv e i e c x re gis t er . c ) w r ite th e spixi p bi t s in th e re sp ec tiv e i p c x re gis t er to s e t the int e rrup t p r iori ty . 2 . w r ite t he de sir ed se ttin gs to t he spix c on 1 an d spix c o n 2 regi ste r s w i th m s ten (spi x c on1<5 > ) = 1 . 3 . c l ear t he spir o v bit (spix s t a t< 6>). 4 . en abl e spi op erat ion by s e tti ng the spien b i t (spi x s t a t<15 >). 5. w r i t e t h e da ta t o b e t r an s m i t t e d t o t h e s p i xb u f re gis t er . t r an sm is si on (a nd rec epti on ) w ill st art a s s oon as d a t a is w r i tte n to t he spix b u f re gis t er . t o se t up th e spi m odu le fo r the s t a nda rd sla v e m o d e of op erat ion : 1. c l e a r t he sp ixbu f regi st er . 2. if us ing in terru pt s : a) c l e a r t he spixi f bi t in th e re spe c t i ve ifsx re gis t er . b) se t th e spixie b i t in the re sp ect i v e i e c x re gis t er . c ) w r ite th e s p ixip bi t s in th e re sp ec tiv e i p c x re gis t er to s e t the int e rrup t pr iori ty . 3. w r it e t he d esi re d se tt in gs t o t he sp i x c o n 1 an d s p i x c o n 2 r e g i st er s w i t h ms te n (spi x c on1< 5 > ) = 0 . 4. c l e a r t he sm p b i t. 5. if th e cke bit i s se t, the n the sse n b i t (spix c o n 1<7 > ) mu st be se t to en abl e the ss x pi n. 6. c l e a r t he sp ir ov bit (spix s t a t<6 > ). 7. en abl e spi ope rati on by se tti ng the spien b i t (spix s t a t < 15 >). figure 15-1: sp ix module bl o c k diagram (standard mode) i n te r n a l data bus sdix sdox ssx /f s y ncx sc kx spixsr bit 0 sh i f t cont ro l e dge sel e ct f cy pr i m a r y 1: 1/ 4/ 16/ 64 enable p r escal e r sync cloc k cont rol spix bu f cont rol transfer t r ansf e r writ e sp ixb u f r ead s p i x bu f 16 s p i x co n1 <1:0> spixcon1<4:2> master clock s e condary prescaler 1: 1 t o 1: 8
? 2010 microchip technology inc. ds39881d-page 143 pic24fj64 ga004 family t o s e t up the spi m odu le for the enha nc ed buf f er ma st e r m o de of o p e r at i o n: 1 . if us ing in terru pt s : a ) c l ear t he spixi f bi t i n th e re sp ect i v e if s x re gis t er . b ) se t th e spix i e b i t in the re sp ect i v e i e c x re gis t er . c ) w r ite th e spixi p bi t s in th e re sp ec tiv e i p c x re gis t er . 2 . w r ite t he de sir ed se ttin gs to t he spix c on 1 an d spix c o n 2 regi ste r s w i th m s ten (spi x c on1<5 > ) = 1 . 3 . c l ear t he spir o v bit (spix s t a t< 6>). 4 . se lec t enh a n c ed buf f er m o d e by se tti ng th e spib e n bit (spix c o n 2 < 0>). 5 . en abl e spi op eratio n by s e tti ng the spien b i t (spi x s t a t < 15 >). 6. w r i t e t h e da ta t o be t r an s m i t t e d t o t h e s p i xb u f re gis t er . t r an sm is si on (a nd rec epti on ) w ill st art a s s oon as d a t a is w r i tte n to th e spix b u f re gis t er . t o s e t up t he spi m odu le for t he enha nc ed buf f e r sl ave m ode of ope rati on: 1. c l e a r t he sp ixbu f regi st er . 2. if us ing in terru pt s : ? c le ar t he sp ixif bi t in the res p e c ti ve ifsx re gis t er . ? s e t the spix i e b i t i n th e re sp ect i v e iecx re gis t er . ? w rite the spix i p b i t s in the res p e c ti ve ipcx re gis t er to s e t the int e rrup t pr iori ty . 3. w r ite th e des ire d se tting s to th e spix c o n 1 an d spix c o n 2 re gi ste r s w i th m s ten (spix c on1<5 > ) = 0 . 4. c l e a r t he sm p b i t. 5. if t he cke bi t is s e t, th en th e ssen bi t m u s t b e s e t, thus e nab lin g th e ssx pi n. 6. c l e a r t he sp ir ov bit (spix s t a t<6 > ). 7. se lec t enh anc ed buf f er m o d e by se ttin g th e spiben bit (spix c on2< 0>). 8. en abl e spi ope rati on by se tti ng the spien b i t (spix s t a t < 15 >). figure 15-2: sp ix module bl ock diagram (enhanced mode) in t e r nal data bus sdix sdox ss x /f sy nc x sc k x spix s r bit 0 shi f t cont rol edge sel e ct f cy pr i m a r y 1: 1/ 4/ 16/ 6 4 e nable p r escale r secondary prescal e r 1: 1 t o 1: 8 sync clock cont ro l spix bu f control tr ansf e r t r ans f er w r i t e spixbuf read spixbuf 16 s p ix con1<1:0> s p ix con1<4:2> m a st er c l oc k 8- level f i f o t r a n s m i t bu ffe r 8-level fif o rec e iv e b u f f e r
pic24fj64ga004 family ds39881d-page 144 ? 2010 microchip technology inc. r e gi ste r 1 5 - 1 : s p i x st a t : sp ix s t atus a nd control re g i ste r r/w - 0 u -0 r/w - 0 u -0 u-0 r -0 r-0 r -0 spi en (1 ) ? spisidl ? ? spibec2 spibec1 spibec0 bi t 15 bi t 8 r- 0 r /c-0 r/w -0 r /w -0 r / w -0 r /w -0 r-0 r -0 srm p t spirov s rxm p t s isel 2 s isel 1 s i sel0 spitbf spirbf bi t 7 bi t 0 le gen d : c = cl e a ra b l e b i t r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 sp ien: spix ena b le bi t (1 ) 1 = en abl es mo dul e a nd con f ig ures sc kx , sd o x , sd ix and ssx as se rial po rt pi ns 0 = d i s a b l es m odu le bi t 14 un im pl e m e n te d : r ead as ? 0 ? bi t 13 sp isidl: s t op in idl e m o d e b i t 1 = d i s c onti nue s mo dul e o pera t io n w he n d ev i ce en ters id le m od e 0 = contin ues m odu le ope rati on in idle m ode bi t 12 - 1 1 un im pl e m e n te d : read as ? 0 ? bi t 10 - 8 sp ibec2:spibec0 : spix buf f er el em en t c o u n t b i t s (v ali d i n enh a n c ed buf f er mo de) m a s t er mo de: n u mb er o f spi t r ansfers pending. slave mode: nu mb er o f spi t r ans fer s u n rea d . bi t 7 srm p t : shi f t r e g i s t er (spixsr ) emp t y bit (va lid in enh anc ed buf f er m o d e ) 1 = s pi x s hi ft r e gi s t e r is em pt y a n d r e ad y t o se nd or r e ce i v e 0 = s pi x s h i ft r e gi s t e r is no t em pt y bi t 6 sp iro v : re c e iv e o v erfl ow fl ag bit 1 = a new byte/w ord is com pletely receiv ed and disc arded. the user s of t w are has n ot read the previou s d a t a in the sp ix b u f regis t e r . 0 = n o ov erfl ow h as oc cur r ed bi t 5 srxm pt : re c e iv e fifo em pty bi t (v ali d i n en han ce d bu f f e r mo de ) 1 = r ec ei ve f i fo i s e m p t y 0 = r e c e i v e fif o is not em pty bi t 4- 2 si sel2:si sel0: spix buf f e r in terru pt m o d e b i t s (v ali d i n en han ce d buf f e r mo de) 11 1 = i nterr upt w hen spix tran sm it buf fer is ful l (spit b f b i t i s s e t) 11 0 = i nterr upt w hen las t b i t i s shi f te d i n to spixsr ; as a re su lt, the tx fifo is em pty 10 1 = i nterr upt when the la st b i t is sh if te d o u t o f spix s r; n o w th e tra n s m i t is c o m p le te 10 0 = i nterr upt w hen on e da t a is sh if te d i n to the spix s r ; as a res u lt , the tx f i fo ha s one op en s p o t 01 1 = i nterr upt w hen spix rec e iv e buf fer is ful l (spir b f bi t se t) 01 0 = i nterr upt w hen spix rec e iv e buf fer is 3/4 or m o re ful l 00 1 = i nterr upt w hen dat a i s a v a ila ble in rec e i v e buf fer (sr m pt bit is s e t) 00 0 = i n t erru pt w h e n th e la st d a t a in th e rec e i v e buf fer i s re ad; a s a re su lt, t he b u f f e r is em pty (srxm p t b i t i s set ) note 1 : if spien = 1 , th ese fu nct i on s m u s t b e a s s i gn ed to a v a ila ble rp n p i n s b e fo re us e. see secti o n 1 0.4 ? p eriph e ral pin se lect? f o r m o re inf o rm ati on.
? 2010 microchip technology inc. ds39881d-page 145 pic24fj64 ga004 family bi t 1 sp itbf: spi x t r a n s m i t buf f er ful l s t at us bit 1 = t r a n sm it not ye t s t arte d, spixt xb is ful l 0 = t r a n s m it s t arted , spix txb is em pty i n s t an dard buf f er mo de: au tom a t i ca ll y s e t in h a rd w a re wh en cpu write s spi xbuf l o c a ti on, loa d i ng sp ixt xb. automatically cleared in hardware when spix module transfers data from spixtxb to spixsr. in enhanced buffer mode: aut o matically set in ha rdw a re w h en c p u w r it es s p ixb u f locat i on, loadi ng t he la st avai lable buf fer loca tion. au tom a t i ca ll y c l e a red in har dw are w hen a b u f f er l o c a ti on is av ail abl e fo r a c p u w r ite . bi t 0 sp irbf: spix r e c e i v e buf f er f u ll s t atu s b i t 1 = rec e i v e c o m p let e , spi x r xb i s f u ll 0 = receive is not complete, spixrxb is empty in standard buffer mode: automatically set in hardware when spix transfers data from spixsr to spixrxb. automatically cleared in hardware when core reads spixbuf location, reading spixrxb. in enhanced buffer mode: au tom a t i ca ll y s e t in ha rdware whe n sp ix tran sfe r s dat a fro m spix s r to buf fe r , fi ll ing th e l a st un read b u f f er l o c a ti on. automatically cleared in hardware when a buffer location is available for a transfer from spixsr. r e gi ste r 1 5 - 1 : s p i x st a t : sp ix s t a t u s a nd control re g i ste r (continue d) note 1 : if spien = 1 , th ese fu nct i on s m u s t b e a s s i gn ed to a v a ila ble rp n p i n s b e fo re us e. see secti o n 1 0.4 ? p eriph e ral pin se lect? f o r m o re inf o rm atio n.
pic24fj64ga004 family ds39881d-page 146 ? 2010 microchip technology inc. reg i s t er 15- 2: sp i x c o n1 : s p i x c o nt ro l re g i s t e r 1 u-0 u -0 u-0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ? ? ? d issck (1 ) diss d o (2 ) m o de16 sm p cke (3) bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ssen (4 ) c k p m st en spre2 spre1 spre0 ppre1 ppre0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 un im pl e m e n te d : read as ? 0 ? bi t 12 di ssck : d i s abl es sc kx p i n bit (spi m a s t er mo des on ly ) (1 ) 1 = i nter nal spi c l o c k is di sa ble d ; p i n fun c ti ons as i/o 0 = i nter nal spi c l o c k is en abl ed bi t 1 1 di ssdo : d i sa ble s sd o x pi n b i t (2 ) 1 = s d o x pi n is n o t u s e d by m odu le ; pi n fu nc tio n s as i/o 0 = s d o x pi n is c ont roll ed by the mo du le bi t 10 m o d e 16: w o rd/by t e c omm un ic ati on sele ct bit 1 = c om mu ni ca t i on is wo r d - w id e ( 1 6 bi ts) 0 = c om mu ni ca t i on is byte - w i d e ( 8 b i t s ) bi t 9 sm p: spi x d a t a i npu t sam p l e ph as e bi t m a s t er mo de: 1 = i npu t da t a sam p l ed at e nd of d a t a ou tput tim e 0 = i npu t data sampled at middle of data output time slave mode: sm p m u s t b e c l ea red w hen spix is us ed in slav e m o d e . bi t 8 cke: spix c l oc k e dge sel ect bi t (3 ) 1 = s e r ia l o utpu t da t a ch ang es on tran sit i on from a c ti ve cl oc k s t at e to idl e c l o c k st ate (se e b i t 6 ) 0 = s e r ia l o utpu t da t a ch ang es on tran sit i on from id le cl oc k s t at e to ac tiv e c l o c k st ate (se e b i t 6 ) bi t 7 ss en : slav e sele ct enab le bit (sla ve mo de) (4 ) 1 =s s x pi n u s ed f o r s lave mode 0 =ssx p i n not use d b y m o d u l e ; p i n c o n t rol l ed by po rt fu nc tio n bi t 6 ckp: c l oc k p o la rity sel e c t bi t 1 = i dle st ate for c l o c k is a hig h l e v e l; ac tiv e s t at e is a low lev e l 0 = i dle st ate for c l o c k is a low lev e l ; ac tiv e s t a t e i s a hi gh lev e l bi t 5 ms t e n: mas t e r mo de enab le bit 1 = m as ter mo de 0 =s l a v e m o d e note 1 : if dissck = 0 , sc kx mu st be c o n f ig ured to an ava i l abl e r p n pin . see sec t ion 10. 4 ? p er iph e r a l pin se lect? fo r m o re inf o rm atio n. 2: if dissdo = 0 , sd ox m u s t be co nfi gure d to an av ai lab l e r p n pi n. s ee se ctio n 1 0 .4 ? p er ip her a l pin se lect? fo r m o re inf o rm atio n. 3: th e c ke bit is not us ed in t he fram ed spi m ode s. the us er s h o u ld pro g ram th is bi t to ? 0 ? for t he f r am ed spi m o des (frm en = 1 ). 4: if ssen = 1 , ssx mu st be c o n f igured to an available rpn pin. see section 10.4 ?peripheral pin select? for more information.
? 2010 microchip technology inc. ds39881d-page 147 pic24fj64 ga004 family bi t 4- 2 sp r e 2 : spre0: seco nd ary pres ca le bit s (m as ter mo de) 11 1 = se co nda ry p r es ca le 1:1 11 0 = se co nda ry p r es ca le 2:1 .. . 00 0 = se co nda ry p r es ca le 8:1 bi t 1- 0 pp r e 1 : ppre0: prim ary pres ca le bit s (m as ter mo de) 11 = p r im ar y pr e s c al e 1 : 1 10 = p r im ar y pr e s c al e 4 : 1 01 = pri m a r y p r es ca le 16:1 00 = pri m a r y p r es ca le 64:1 reg i s t er 15- 2: sp i x co n 1 : sp ix co n t r o l r e gis t er 1 (continue d) note 1 : if dissck = 0 , sc kx mu st be c o n f ig ured to an ava i l abl e r p n pin . see sec t ion 10. 4 ? p er iph e r a l p i n se lect? fo r m o re inf o rm atio n. 2: if dissdo = 0 , sd ox m u s t be co nfi gure d to an av ai lab l e r p n pi n. s ee se ctio n 1 0 .4 ?p er ip her a l pin se lect? fo r m o re inf o rm atio n. 3: th e c ke bit is not us ed in t he fram ed spi m ode s. the us er s h o u ld pro g ram th is bi t to ? 0 ? for t he f r am ed spi m o des (frm en = 1 ). 4: if ssen = 1 , ssx mu st be c o n f ig u r ed t o a n av ai l a b l e r p n pi n . s e e sect ion 1 0.4 ? p er ip her a l pin se lect? fo r m o re info rm a t io n. regis t er 15-3: sp ix c o n2 : sp ix c o ntrol re gis t e r 2 r/w - 0 r /w -0 r/w -0 u -0 u-0 u -0 u-0 u -0 f r m e n spifsd spifpol ? ? ? ? ? bi t 15 bi t 8 u-0 u -0 u-0 u -0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? spife spiben bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 fr m e n : f r am ed spix supp ort b i t 1 = fra m e d spi x s u p port ena ble d 0 = f r am ed s p i x su pp o r t d i sa bl e d bi t 14 sp ifsd: frame sync pulse direction control on ssx pin bi t 1 = fra m e sy nc pu ls e i npu t (s lav e ) 0 = fra m e sy nc pu ls e o u tp ut (m as ter) bi t 13 sp ifpol: fra m e sy nc puls e pola rity bi t (fra me m ode onl y) 1 = fra m e sy nc pu ls e i s a c ti ve -hi g h 0 = f r am e s y n c p ul s e is ac t i v e- l ow bi t 12 - 2 unimpl e m e n te d : r ead as ? 0 ? bi t 1 sp ife: fr ame sy nc puls e edge sel e c t bi t 1 = fra m e sy nc pu ls e c o i n ci de s w i th fi rst bi t cl oc k 0 = fra m e sy nc pu ls e p r ec ede s f i rs t bi t c l oc k bi t 0 sp iben: enh anc ed buf f er en ab le b i t 1 = en han ced buf f er ena bl ed 0 = en han ced buf f er dis a b l ed (le gac y mo de)
pic24fj64ga004 family ds39881d-page 148 ? 2010 microchip technology inc. figure 15-3: s p i m a ste r /s l a ve conne ction (s t a n dard m o de) f i g ure 15- 4: sp i m a st e r /s la ve conne ction (enha nced buffer mode s) serial receive buffer (spixrxb) (2) s h ift re giste r (s p i x s r ) lsb ms b sdi x sdo x pr o c e s s o r 2 (sp i sl ave) sckx ssx (1) serial transmit buffer (spixtxb) (2) serial receive buffer (spixrxb) (2) s h i f t r egi s t er ( spi x s r) ms b ls b sdo x sdix p r o c es so r 1 (s pi m aster) serial clock s sen ( s pi x c o n 1 < 7 > ) = 1 and m s t e n (s p i xc on 1< 5 > ) = 0 no t e 1 : usin g th e ssx p i n i n s l ave mo de o f o per ati o n i s o p ti o nal . 2: user must write transmit data to read received data from spixbuf. the spixtxb and spixrxb registers are memory mapped to spixbuf. sckx serial transmit buffer (spixtxb) (2) msten (spixcon1<5>) = 1 ) spix buffer (spixbuf) (2) spix buffer (spixbuf) (2) sh if t re g i ste r ( spi x s r) lsb ms b sdi x sdo x pr oc esso r 2 ( sp i enh a nce d b u ffer sl a ve) sckx ssx (1) sh if t re g i s t e r ( spi x s r) ms b ls b sdo x sdix pr o c es sor 1 (spi enha n ced bu f f er mas t er) se r ia l clo ck ssen (spix c o n 1 < 7 > ) = 1 , no t e 1 : usin g th e ssx pi n i n s l av e m ode of op era t i o n i s op ti on al . 2: u ser must write transmit data to read received data from spixbuf. the spixtxb and spixrxb registers are memory mapped to spixbuf. ssx sckx 8-level fifo buffer msten (spixcon1<5>) = 1 and spix buffer (spixbuf) (2) 8-level f i f o b u f f er spi x buffer (spixbuf) (2) spi ben ( s pi x c o n 2 < 0 > ) = 1 ms t e n (s p i x c o n 1< 5 > ) = 0 an d spi ben ( spixcon2<0>) = 1
? 2010 microchip technology inc. ds39881d-page 149 pic24fj64 ga004 family figure 15-5: sp i m a ste r , fram e mas t er connec t i o n diagram f i g ure 15- 6: sp i m a st e r , f rame slav e connec t io n diagram figure 15-7: sp i s l ave , fram e m a s t e r c o nn ection di agram figure 15-8: spi slave, fram e slave connection diagram sdo x sdix pi c2 4 f se r ia l clo ck ssx sckx fr am e s yn c pu ls e sdi x sdo x pro c esso r 2 ssx sckx ( s p i s l ave , fr am e s l a v e) sd o x sdi x pi c2 4 f se r ial clock ssx sckx f r am e s yn c pu ls e sdi x sdo x pro c es so r 2 ssx sckx s p i ma s t er , fr am e s l a v e ) sdo x sdi x pi c2 4 f se r ia l clo ck ss x sckx frame s y n c . pu ls e sdi x sdo x pro c esso r 2 ssx sckx ( s p i s l a v e, fr a m e s l av e ) sdo x sdi x pi c2 4 f ser ia l clo ck ssx sckx frame sy nc pu ls e sdi x sdo x p r oc e s s or 2 ssx sckx ( s p i ma s t er , fr am e s l av e )
pic24fj64ga004 family ds39881d-page 150 ? 2010 microchip technology inc. equa tion 1 5 -1: r ela t i o n s hip be twe e n dev i ce and spi clo c k s p e e d (1) t a ble 1 5 -1: s am ple s ck fre q u e nci es (1, 2 ) f cy = 16 m h z se cond ar y pr e sca ler se tting s 1 : 12 : 1 4 : 16 : 18 : 1 p r im ary pres ca ler setti ngs 1: 1 i nv ali d 8 000 40 00 2 6 6 7 20 00 4: 1 400 0 2 000 10 00 667 5 00 16: 1 100 0 5 00 25 0 167 1 25 6 4 : 1 2 50 12 5 63 4 2 31 f cy = 5 mh z p r im ary pres ca ler setti ngs 1: 1 500 0 2 500 12 50 833 6 2 5 4: 1 125 0 6 25 31 3 208 1 56 1 6 : 1 3 13 15 6 78 5 2 39 6 4 : 1 7 83 9 2 01 31 0 no te 1 : ba s e d on f cy = f os c /2 ; d o z e m o d e a nd pll are d i s abl ed . 2: sc k x f r eq ue n c i e s sh ow n i n k h z. primary p r es cal er * s eco nd ary p r e s cal er f cy f sc k = note 1 : bas e d on f cy = f os c /2; d o z e m o de an d pl l ar e di sa ble d .
? 2010 microchip technology inc. ds39881d-page 151 pic24fj64 ga004 family 1 6 .0 inte r - integ r ate d c i rc uit (i 2 c?) th e in ter-i nteg rate d c i r c ui t? (i 2 c ? ) m o d u le is a s e ria l i n ter f ac e u s ef ul f o r c o m m u n ic at ing w i th oth e r p e rip h - e r al or m i c r oc ontr o ll er dev ic es . the s e p e rip hera l d e vi ce s m a y b e se r i al e e p ro m s , d i sp la y dr i v e r s, a / d co nve r ters , e t c. th e i 2 c mo du l e s u p p o r ts t h es e f e at u r es : ? i n dep en den t m ast er a nd sla v e lo gic ? 7 -bit and 10 -bit de vic e add res s es ? g en er a l ca l l addres s, as defi n ed i n the i 2 c protocol ? c l o ck s t retc hi ng to p r ov ide de lay s for t he p r oc esso r to re sp ond to a s l av e d a t a req uest ? b ot h 10 0 k h z a n d 4 0 0 k h z bu s sp e c i f ic at i o ns . ? c on fig u ra ble ad dres s ma sk ing ? m ul ti-m as ter m od es to prev en t loss of me ss age s i n ar bitr atio n ? b u s re pea ter m o d e , all o w i n g th e a c c ept anc e o f a ll me ss ag es as a s l a v e re gard l es s of th e add res s ? a u tom ati c sc l a b l o c k di agra m of t he m o d u le is s how n in fi gure 1 6 - 1. 16. 1 p er ipher a l remapping opti ons th e i 2 c m od ule s are ti ed to f i x ed pi n as sig nm ent s, an d c ann ot be re ass i g ned t o a l te rnat e p i n s us ing p e rip heral pi n se l e c t . t o al lo w s o m e fl e x i b i l i t y w i t h pe r i ph e r al m u l t ipl e x i ng , th e i2c 1 mo dul e in al l de vi ces , c an b e re as sig n e d to the alte rna t e pi ns , d e s i gn ate d as as c l 1 a nd a s d a 1 du rin g de vi ce co nfi gura t io n. pi n ass i g n m ent i s co ntrol l e d b y the i 2 c 1 sel c o n f ig u- ra tio n bi t; pro g ra mm ing thi s b i t (= 0 ) mu ltip le xe s th e m o d u le to the ascl1 a n d asda1 p i ns . 16. 2 c omm uni cat ing as a mast er in a si ngle master envi ron m ent th e d et a ils of se ndi ng a m es s ag e i n m as t er m od e de pe nds on th e c o m m u n i c at ion s prot oco l f o r t h e dev i c e be in g com m uni ca ted w i th. t y pi cal l y , th e se que n c e of ev en t s is as fol l o w s : 1. as se rt a s t a r t c ond iti on on sd ax a nd sc l x . 2. se nd th e i 2 c de vi ce a d d r ess by te t o th e sl av e w i t h a w r ite ind i c a ti on. 3. w a it for an d ve rify an ac kn ow le dge fr om th e s l av e. 4. se nd the fi rst da t a by te (so m e t im es k now n a s th e c o m m a nd) to t he s l a v e . 5. w a it for an d ve rify an ac kn ow le dge fr om th e s l av e. 6. se nd th e s e ri al m e m o ry ad dres s l o w b y te to th e s l av e. 7. r ep eat s t ep s 4 an d 5 un til al l d at a by tes a r e s ent . 8. as se rt a r e pea ted s t art c o nd itio n on sd ax an d sclx . 9. se nd the de vi ce add res s by te to t he sl av e w i th a read in dic a t i on . 10 . w a i t for an d ve rify an ac kn ow le dge fr om th e s l av e. 1 1. e n abl e ma ste r re ce ptio n to rec ei v e s eria l me mo r y d a ta . 12 . g en erat e an ac k or n a c k c ond iti on a t th e en d of a re ce iv ed byt e of da t a. 13 . g en erat e a s t o p c o n d iti o n on sd ax a nd sc lx. note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 24. inter-integrated circuit (i 2 c?)? (ds39702).
pic24fj64ga004 family ds39881d-page 152 ? 2010 microchip technology inc. f i g ure 16- 1: i 2 c? bloc k diagram i2cxrcv i n t e rnal d a ta b u s sclx sd a x shift match detect i2cxadd start and stop bit detect cloc k address match clock stretching i2cxtrn lsb shift clock brg down counter reload control t cy /2 start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk
? 2010 microchip technology inc. ds39881d-page 153 pic24fj64 ga004 family 16. 3 s et ti ng bau d rat e when oper ati ng as a bus mast er t o co mp ute th e bau d r a te g ene rato r relo ad v a lu e, us e eq uat ion 16- 1. equa tion 1 6 -1: c omp u ting baud rate reload v a lue (1 ) 16. 4 s l ave addr ess m a s k ing th e i2 c x m sk re gis t er (r egi ste r 16 -3) d e s i gn ate s ad dre s s b i t po si tio n s as ?don ?t c a re? fo r b o th 7 - bit an d 10 -bit a ddre s s i ng mo de s. se ttin g a p a rti c u l ar b i t l o c a - ti on ( = 1 ) in the i2c x m sk regi st er c aus es the sl av e m odu le to re sp ond w h eth e r the c o rre sp ond ing a d d r es s bi t v a l ue is a ? 0 ? or a ? 1 ? . f o r e x am pl e, w h en i2 c x ms k i s se t to ? 0010000 0 ? , t h e sl av e mo du l e w i l l de t e ct b o t h ad dre s s es, ? 000 0000 ? a nd ? 00100000 ?. t o ena ble a ddr ess ma sk ing , t h e ipm i (inte lli ge nt pe riph eral ma na gem en t int e rfac e) mus t b e di sa ble d b y c l ea rin g th e ipm i en b i t (i 2cxco n <1 1 > ). t able 1 6 -1: i 2 c? clo c k rate s (1) t able 1 6 -2: i 2 c? res e r v e d addre s s e s (1) i2 cx brg f cy f sc l -- - --- -- -- - - f cy 1 0 000 0 00 ?? -- -- -- -- --- -- -- -- -- -- -- -- --- - - ? ?? ?? 1 ? = f sc l f cy i2 cx brg 1 f cy 10 000 000 ?? -- --- -- -- -- -- -- -- -- --- -- -- -- - - ++ - - - - - - - - - - - - - - - --- -- -- -- -- -- -- -- --- -- -- -- -- -- -- -- --- -- -- -- -- -- -- -- --- - = or note 1 : bas ed on f cy = f os c /2 ; d o ze m ode an d pll are dis a b l ed . note : as a re su lt o f ch ang es in the i 2 c ? prot o- c o l, t he ad dre s s e s i n t abl e 1 6-2 a r e re ser v ed and w i ll n o t be a c k now l e dg ed i n sl ave m ode . th is inc l u des an y a ddre s s m a s k s e t t ing s that in cl ude an y o f th es e ad dre s s e s . require d sys t em f sc l f cy i2 cx brg v a l u e ac tu a l f sc l ( d e ci m al ) ( h e xa d ec i ma l ) 10 0 k h z 16 mh z 1 5 7 9d 10 0 k h z 10 0 k h z 8 m h z 78 4e 10 0 k h z 10 0 k h z 4 m h z 39 27 99 kh z 40 0 k h z 16 mh z 3 7 2 5 4 0 4 k h z 40 0 k h z 8 m h z 18 12 40 4 k h z 4 0 0k h z 4m h z 9 9 3 8 5k h z 4 0 0k h z 2m h z 4 4 3 8 5k h z 1 m h z 16 mh z 1 3 d 1.02 6 m h z 1m h z 8m h z 6 6 1 . 0 2 6m h z 1m h z 4m h z 3 3 0 . 9 0 9m h z note 1 : ba se d on f cy = f os c /2, do z e m o d e an d pl l a r e d i sa bl ed. slav e addres s r/w bit d esc r i ption 0000 000 0 ge nera l c a ll addre s s (2 ) 0000 000 1 st a r t b y t e 0000 001 x c b us add r es s 0000 010 x re se r v e d 0000 011 x re se r v e d 0000 1xx x hs mo de ma ste r c o d e 1111 1xx x re se r v e d 1111 0xx x 10-bi t sl av e upp e r by te (3 ) no t e 1 : the add res s b i t s li ste d he re w i ll n e v e r c aus e a n a ddre s s m a tc h, i nde pen de nt of the add res s m a s k set t in gs. 2: addre s s w i l l b e ac kn ow le dge d o n ly if gc en = 1 . 3: ma tch on thi s a ddress can only occur on the upper byte in 10-bit addressing mode.
pic24fj64ga004 family ds39881d-page 154 ? 2010 microchip technology inc. regis t er 16-1: i2c x con: i2cx control regis t er r/w - 0 u -0 r/w - 0 r /w -1 hc r/w - 0 r /w -0 r/w - 0 r /w -0 i2cen ? i 2 c sidl sclrel ipm i en a10m dissl w smen bi t 15 bi t 8 r/w - 0 r / w -0 r/w - 0 r /w - 0 , hc r/w - 0 , hc r/w - 0 , h c r/w - 0 , hc r/w - 0 , hc gcen stren a ckdt acken rcen pen rsen sen bi t 7 bi t 0 le gen d : hc = ha rd wa re cl e a ra b l e b i t r = read abl e b i t w = w r it ab le bit u = un im pl em ent ed bit, rea d as ? 0 ? -n = v a l ue a t po r ? 1 ? = bit i s set ? 0? = bit is cl ear ed x = bit i s unk no w n bi t 15 i2 cen: i2c x en abl e bi t 1 = ena b le s the i2c x mo dul e a nd co nfig ure s th e sd ax an d sc l x p i ns a s s e ri al port pin s 0 = dis a b l es i2cx m odu le . all i 2 c ? pi ns are co ntrolle d b y p o rt f unc tio n s . bi t 14 u n im p l em en t e d : read as ? 0 ? bi t 13 i2 csidl: s t o p in idl e m o d e b i t 1 = d i s c o n ti nue s m o d u le op erat ion wh e n de vi ce en ters an idl e m o d e 0 = c on t inu es m odu le ope rati on i n i dle mo de bi t 12 sclrel : sc lx re l eas e c o ntro l b i t (w h en ope rati ng a s i 2 c slav e) 1 = r e l eas es sc lx c l oc k 0 = h o l d s s c lx cl oc k l o w ( c loc k str e tc h) if stren = 1 : bit is r/w ( i . e . , s oftware may write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware clear at beginning of slave transmission. hardware clear at end of slave reception. if stren = 0 : b i t is r / s ( i .e. , sof t w a r e may onl y w r ite ? 1 ? to relea s e clock). h a r d w a re cle a r at beginn ing of slave tr ansmission. bi t 1 1 ipm i en: i n te lli gen t per i ph eral m ana gem en t in terfa c e (ipm i) ena b l e bi t 1 = ipm i su ppo rt m ode is en abl ed; al l ad dre s s e s ack n o w led ged 0 = ipm i m ode is di sa ble d bi t 10 a1 0 m : 10- bit sl av e ad dres si ng bit 1 = i2c x ad d is a 10-b i t sla v e ad dres s 0 = i2c x ad d is a 7-bi t s l av e add res s bi t 9 dissl w : d i s abl e sl ew r a te c o n t rol bi t 1 = sle w rate co ntro l d i s abl ed 0 = sle w rate co ntro l e nab le d bi t 8 sm en: sm bus inp u t lev el s b i t 1 = ena b le s i/o pi n th res hol ds co mp lia nt w i th sm bus s pec if ica t io n 0 = di sa bl e s s m b u s i n pu t t h r e sh ol d s bi t 7 gcen: g e n e ral c a l l ena b l e bi t (w h en o per atin g a s i 2 c sl av e) 1 = e n abl es int errup t w hen a ge ner al c al l ad dres s i s re ce ive d i n the i2c x r s r (mo dul e is en abl ed fo r re ce ptio n) 0 = g en eral c all ad dres s dis ab l ed bi t 6 s t re n: sc lx cl oc k s t r e tc h en abl e b i t (w h en o p e r ati ng a s i 2 c sl av e) u s ed in con j u n ct ion wi th sc lr el bit . 1 = e n a b le s sof t w a r e or r e ce iv e cloc k str e tc hin g 0 = di sa bl e s so ft war e or r e ce i v e c l oc k st r e t c h i n g
? 2010 microchip technology inc. ds39881d-page 155 pic24fj64 ga004 family bi t 5 ackdt : ack n o w led ge d a t a bit (whe n o pera t in g a s i 2 c m a s t er . app lic ab le d u ri ng mas t e r rec e i v e. ) v al ue t hat w ill be tran sm itt ed w h en the so f t w are in iti ate s a n ac kn ow le dge se qu enc e. 1 = send s n a c k d u r i n g a c k n ow l e dg e 0 = sen d s ac k du ring ac kn ow le dge bi t 4 acken: ac kn ow le dge seq uen ce ena b le bi t (wh en ope rati ng as i 2 c ma ste r . ap pli c a b le du ring m a st er re c e iv e.) 1 = i n i ti ate s ac kn ow le dge seq u e n ce on sd ax and sc lx pin s an d tra n s m i t s ac kd t d a t a b i t. h a rdw a re c l e ar at en d of ma ste r ac kn ow le dge se que nc e. 0 = a c k n o w l e dge s equ ence n o t in p r og res s bi t 3 rcen: r e cei v e ena b le bi t (w he n o perat in g a s i 2 c ma ste r ) 1 = enable s r e ce iv e m ode fo r i 2 c . h a rd w a re cle a r a t en d o f ei ght h b i t o f m a s t er re ce iv e da t a byt e . 0 = re c e iv es s equ ence not in prog ress bi t 2 pen: s t op co nd it i o n e n ab le b i t ( w h en op e r at i ng as i 2 c ma ste r ) 1 = ini t ia tes s t op co ndi tio n o n sd ax an d sc lx pi ns . h a rd w a re cl ear at e nd o f m a s t er s t o p s equ en ce. 0 = s t op co ndi tio n no t i n pro g re ss bi t 1 rsen: re pea ted s t art c o ndi tio n en abl ed bit (w hen op erat ing as i 2 c ma s t e r ) 1 = i n i ti ates r e p e a t ed s t a r t co nd itio n o n sd ax and sc lx pins. h a rdw a re cl ear at en d o f ma ste r r e pea ted s t art s e q uen ce . 0 = r e pea ted s t art c o n d iti o n not in prog res s bi t 0 sen: s t a r t c o n d i t ion ena b le d b i t (w h en ope rati ng as i 2 c ma st e r ) 1 = ini t ia tes s t art co ndi tio n on sd ax and sc l x pi ns . h a rd w a re cl ear a t e nd o f m a s t er s t a r t s equ enc e. 0 = s t art con d i t ion no t in pro g re ss regis t er 16-1: i2c x con: i2cx control regis t er ( c o n tin u ed)
pic24fj64ga004 family ds39881d-page 156 ? 2010 microchip technology inc. regis t er 16-2: i2c x st a t : i2cx s t atus re giste r r-0 , hs c r -0 , hsc u -0 u-0 u -0 r/c-0 , hs r-0 , hsc r -0 , hsc ackst a t t r st a t ? ? ? b cl g c s t a t add10 bi t 1 5 bi t 8 r/c-0 , hs r/c- 0 , hs r-0 , hs c r /c- 0 , hsc r / c -0 , hsc r -0 , hsc r -0 , hsc r -0 , hsc i w col i 2 c ov d/a psr/w rbf t bf bi t 7 bi t 0 le gen d : c = c l e a ra ble bi t h s = h a rdw a re sett abl e b i t h s c = h a r d w a r e s e t t a b l e , c l ea rable bit r = r ead abl e b i t w = w r i t ab le b i t u = u n im ple m e n ted bi t, re ad as ?0? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0? = bi t i s c l e a red x = bit i s u n k nown bi t 15 ackst a t : ac kn ow le dg e s t atu s bit 1 = nack wa s d e te cte d l a s t 0 = a c k wa s d e te cte d l a st h a rdw a re s e t o r cl ear at e n d of ac k now l edg e. bi t 14 tr s t a t : t r ans m i t s t a t us bi t (w hen op era t ing as i 2 c ? m a s t er . appl ic abl e t o m a s t er t r ans m i t o perat io n.) 1 = m a s ter t r ans m i t i s i n p r ogre s s (8 bit s + ac k) 0 = m a s t er t r ans m i t i s n o t i n p r ogr ess h a rdw a re s e t a t be gin n i ng o f m a s t er t r ans m i ss io n. h a rdw a re c l ea r at end of sla v e ac kno w led ge. bi t 13 - 1 1 un im pl e m e n te d : read as ? 0 ? bi t 10 bcl : m a s t er b u s c o ll is i o n de t e ct b i t 1 = a b us co lli si on has be en det ect ed duri ng a m as t er oper atio n 0 = n o c o ll is io n h a rdw a re s e t a t de tec t io n o f bu s c o l lis io n. bi t 9 gcst a t : g e n e ral ca l l s t at us bit 1 = g e n e r a l ca ll add r e s s wa s r e ce iv ed 0 = gen e ral c a ll add res s wa s n o t rec e iv ed h a rdw a re s e t w h en a d d r ess m a tc he s g ene ral ca ll add res s . h a rdw a r e c l ea r at s t o p d e te cti on. bi t 8 add1 0 : 1 0 -bit addr ess s t at us bit 1 = 10-bi t ad dres s wa s ma tch e d 0 = 10 -bi t ad dres s wa s not ma tc hed h a rdw a re s e t a t m a tc h o f 2n d b y te of mat c h ed 1 0 -b it a ddre s s . ha rdw a re cl ear at s t o p de tec t io n. bi t 7 iw c o l : w r ite co ll is ion de te ct bit 1 = an atte mp t to write the i2cx trn re gis ter fai l ed be cau s e the i 2 c m odu le is bus y 0 = n o c o ll is io n ha rd wa re se t a t o c c u rre n c e o f wri t e t o i2 cx trn wh i l e b u s y (cl e a r e d b y s o f t wa re ). bi t 6 i2 c o v : r e c e i v e ov erf l ow f l ag bi t 1 = a byt e wa s r e ce iv ed wh il e t h e i 2 c x r c v r e gi s t e r is st i ll ho l d i n g t h e pr e v io us byt e 0 = n o o v er f l ow ha rdware s e t a t at tem p t t o tra n s f er i 2 cx rsr t o i2 cx rcv (cl e a r e d b y so f t wa re ). bi t 5 d/a : data/address b i t (w h en ope rati ng a s i 2 c sl av e) 1 = in dic a te s that the la st b y t e re cei v e d wa s d a t a 0 = in dic a te s that the la st b y t e re cei v e d wa s d e v i ce ad dres s h a rd w a re c l e a r at d e v i ce ad dr es s ma tc h. h a rd ware set by write to i2cxtrn or by reception of slave byte.
? 2010 microchip technology inc. ds39881d-page 157 pic24fj64 ga004 family bi t 4 p: s t op b i t 1 = in dic ate s that a s t op bi t ha s bee n d etec t ed la st 0 = s t op bi t w a s no t de tec t ed la st h a rdw a re s e t o r cl ear when s t art, re pe ate d s t art or s t o p de tec t ed . bi t 3 s: s t art b i t 1 = in dic a te s that a s t a r t (or r epe ated s t art) bit ha s b een de tect ed las t 0 = s t art bit wa s no t detec t ed la st h a rdw a re s e t o r cl ear when s t art, re pe ate d s t art or s t o p de tec t ed . bi t 2 r/w : r e ad/w rite inform at ion bi t (w he n o pera t in g a s i 2 c s l av e) 1 = rea d ? in dic a te s d a t a tra n sf er i s o u tp ut fro m sl ave 0 = w r ite ? i n d i ca tes da t a trans fe r is in put to s l a v e ha rdware s e t o r c l ear af te r rec e p tio n o f i 2 c de vi ce add res s b y te . bi t 1 rbf : r e c eive bu f f e r fu ll s t a t us bi t 1 = re ce i v e c o m p l e t e , i2 cx rcv i s f u l l 0 = re ce i v e n o t c o m p l e t e , i2 cx rcv i s e m p t y ha rd wa re se t wh e n i2 cx r c v i s wri t te n w i th re ce i v e d b y te . ha rd wa re cl e a r wh e n s o f t wa re re a d s i2 cx rcv . bi t 0 tb f : t r an sm it buf f er f u ll s t atu s b i t 1 = t r a n sm it in prog res s , i2c x tr n is fu ll 0 = t r a n sm it co mp let e , i2 c x t r n is em pty ha rd wa re se t wh e n so f t wa re wri t e s i2 cx trn. ha rd wa re cl e a r a t c o m p l e t i o n o f d a t a tra n sm i s si o n . regis t er 16-2: i2c x st a t : i2cx s t atus re giste r (continue d)
pic24fj64ga004 family ds39881d-page 158 ? 2010 microchip technology inc. 16. 5 a cknowl edge s t at us in bo th m a s t er a nd sl av e m ode s, the ac kst a t b i t i s o n ly u pda ted w hen tra n s m i ttin g d a t a res u l t in g i n th e re ce ptio n of an ac k or n a c k fro m a not her d e v i ce . d o n o t ch ec k th e st a t e of ac kst a t w hen rec e iv in g dat a, e i the r as a sl av e or a ma ste r . r e a d i ng ac kst a t af ter re ce ivi n g add ress or dat a by tes retu rns an i n v a li d re s u lt. regis t er 16-3: i2c x ms k: i2cx sl av e mode addre ss mas k re gis t e r u-0 u -0 u-0 u -0 u-0 u -0 r/w - 0 r /w -0 ? ? ? ? ? ? a m sk9 amsk8 bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 am sk7 a m sk6 am sk5 am sk4 am sk3 am sk2 a m sk1 am sk0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 0 un im pl e m e n te d : read as ? 0 ? bi t 9- 0 amsk9 : amsk0 : m a s k for ad dre s s bit x se le c t b i t s 1 = en abl e m a s k i ng f o r b i t x of inc o m i n g m e s s a ge add res s ; bit ma tch no t req u ire d i n th is po si tion 0 = d i s a b l e ma sk ing for bit x; bit ma tch req u ir ed i n t h is po si tio n
? 2010 microchip technology inc. ds39881d-page 159 pic24fj64 ga004 family 17 .0 univ e rs al as y nchronous re ceiv e r t ran sm i tte r (uar t) the u nivers al as ynchronou s r ec eiver t r an smitter (u a r t) m odule is on e of t h e serial i/o mo dules avai lable in the pic 24f de vice family . t h e u a r t is a full-du plex asynchronous system that can com m unic a te w i th periph e r a l de vices , su ch as personal com puters, lin , r s - 2 32 and r s -48 5 interfaces. the m odule als o sup- port s a ha r d w a re f l ow control option w i th t h e u x c t s and uxrts pins and also i ncludes an ird a ? enc oder and dec oder . th e p r im ary fea t ure s o f th e u a r t m odu le a r e: ? f u l l - d upl ex, 8 or 9-bi t d a t a t r a n sm is s i on t h rou gh th e u x tx a nd u x r x pi ns ? e v e n , o dd or n o parit y o p t i on s (f or 8 - bit dat a) ? o ne or t w o s t op bi t s ? h ar dw are flow c ont rol op tio n w i t h u x c t s and uxrts pi ns ? f u lly in teg r ate d ba ud ra te g e n e ra tor wi th 1 6 -bi t pre s c a le r ? b a ud r a tes r an g in g fro m 1 m bp s to 15 bp s a t 16 m i ps ? 4 - d e ep, fi rs t-i n -fi r s t -out (fif o ) t r ans m i t dat a bu f f e r ? 4 -d ee p f i f o re c e iv e d a ta b u f f e r ? p arity , fr am ing and buf f e r o v errun err o r d e tection ? s u ppo rt fo r 9-b i t m o d e wi t h ad dres s d e tec t (9 th b i t = 1 ) ? t ra nsm i t an d r e c e i v e inte rrup t s ? lo op bac k mo de f or d i a gn ost ic supp ort ? s u ppo rt fo r syn c a n d brea k c h arac ters ? s u ppo rt s automa tic bau d rat e det e ct ion ? i rd a enco de r and de c o d e r l ogi c ? 1 6 x baud clo c k o u tpu t fo r irda su ppo rt a s i m p l i fi ed blo c k di agr am of the u a r t i s sho w n i n fi gur e 17 - 1. the u a r t m od ul e c ons is t s of thes e ke y i m po rt an t h a rdw a re e l em en t s : ? b a ud r a te g e nerat or ? a s y n c h r ono us t r an sm itte r ? a s y n c h r ono us rec eiv er figure 17-1: uart s i mp lifie d block dia g ra m note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 21. uart? (ds39708). uxrx irda ? hardware flow control uartx receiver uartx tr ans m i tte r uxtx uxcts uxrts bclkx b a ud r a te ge ne r ator note: this peripheral?s inp u t s an d outp u t s m u s t b e a s s i g ned to an av ail a b l e r p n p i n bef ore us e. pl ea se s ee secti o n 1 0.4 ? p e r i pher a l pin sele ct? for mo re in form at ion .
pic24fj64ga004 family ds39881d-page 160 ? 2010 microchip technology inc. 17. 1 uart ba ud rat e gener ator ( brg ) th e u a r t m odu le in cl ude s a de dic ate d 16- bit bau d r a te g ene rato r . the u x br g r egi ste r co ntro ls th e p e rio d o f a free -run n in g, 1 6 -b it t i m e r . e qua tion 17 -1 s how s th e f o rm ula fo r c o m put a t io n o f th e b a u d ra te wi th brg h = 0 . equa tion 1 7 -1: uart b a ud rate wi th brgh = 0 (1) ex am pl e 1 7 - 1 sh ow s th e ca lc ula t io n o f the b aud ra te e rror fo r th e fo llo w i ng c ond iti ons : ?f cy = 4 mh z ? d e s ire d ba ud r a te = 96 00 th e m a x i m u m bau d ra te (br g h = 0 ) pos s i bl e i s f cy /1 6 (fo r uxbrg = 0 ) a n d the m i n i m u m bau d ra te po ss ib le is f cy /(16 * 65 536 ). eq uati o n 17-2 sh ow s th e fo rmu l a fo r co mpu t at ion of th e b aud rate with brg h = 1 . equa tion 1 7 -2: uart b a ud rate w i th brgh = 1 (1) th e ma xim u m bau d ra te (br g h = 1 ) p o s s i b le is f cy /4 (fo r ux brg = 0 ) and the m i n i m u m bau d rat e po ss ibl e is f cy /(4 * 65 536 ). w r iti ng a new v a lu e to the u x br g re gi ste r cau s e s th e brg ti m e r to be res e t (c l eare d ). thi s e n s u res th e brg do es n o t w a i t for a tim e r o v erf l ow be fore g ene rati ng th e ne w ba ud rate. ex amp l e 17-1: baud rate e rro r c a l c u lation (brgh = 0 ) (1 ) note 1: ba s e d o n f cy = f os c /2, doz e m o d e a nd pll a r e d i s abl ed . ba u d r a te = f cy 1 6 ? (ux brg + 1 ) f cy 16 ? b aud rate uxbrg = ? 1 bau d rate = f cy 4 ? (uxbrg + 1) f cy 4 ? bau d rate ux brg = ? 1 not e 1 : ba se d on f cy = f os c /2, doz e m o d e a nd pll a r e d i s abl ed. de sir e d bau d rate = f cy /( 16 ( u xb r g + 1) ) so lv i n g fo r ux brg v a lu e : ux brg = ( ( f cy / d e s ired bau d rate)/1 6 ) ? 1 uxb r g = ( ( 4 00 00 00/ 9 6 0 0 ) / 16 ) ? 1 ux brg = 2 5 c a l c ul at ed b a ud r a t e = 4 00 00 00 /( 1 6 ( 25 + 1 ) ) = 9 61 5 erro r = (calc u lated ba u d ra te ? de s i r e d b a ud r a te ) de sired bau d rate = ( 9 61 5 ? 96 00) / 960 0 = 0 . 16% note 1 : bas ed on f cy = f os c / 2; d o ze mo de and pll are dis ab l ed .
? 2010 microchip technology inc. ds39881d-page 161 pic24fj64 ga004 family 17. 2 t r a nsmit t i ng i n 8 - bi t da t a mode 1 . se t up the uar t : a) w r i t e a p p r o pr i a te v a l u es f o r d a ta , p a r i ty a n d s t op bi t s . b ) w r ite a ppro p ria t e bau d rate va lu e t o th e u x br g r egi ste r . c ) se t up tra n s m i t and r e ce iv e in terru pt en abl e a nd p r io rity bi t s . 2 . en abl e th e u a r t . 3 . se t th e utxen b i t (cau se s a tra n s m i t in terru pt 2 c yc le s a fte r be i n g se t ) . 4 . w r ite dat a by te to l o w e r b y te of u x t x r e g w o rd. th e val u e w i l l be i m m e d i at ely tran s f erre d t o the tra n s m i t shi f t r egi ste r (ts r ) , an d the se rial b i t st r e am wi ll sta r t sh ift i ng o u t wi t h ne xt r i si n g e d g e o f the ba ud cl ock . 5 . al tern atel y , th e dat a by te m a y be tr ans ferre d whi l e u t xen = 0 , and the n th e us er m a y s e t u t xen . t h is w ill cau s e t he s e ria l bi t str eam to b egi n im me dia t el y be cau s e t he ba ud c loc k w il l s t art from a cl eared s t at e. 6 . a t r ans mi t i n terr upt w i ll be gen erat ed a s p e r i n ter r upt co ntro l bi t, u t xiselx . 17. 3 t r a nsmit t i ng i n 9- bi t d a t a mode 1 . se t up th e u a r t (as des cr ibe d in se ction 1 7 . 2 ? t ran s mi tting i n 8-bi t dat a m o de? ). 2 . en abl e th e u a r t . 3 . se t th e utxen b i t (cau se s a tra n s m i t in terru pt 2 c yc le s a fte r be i n g se t ) . 4. w r i t e u x tx r e g a s a 16 - b it va l u e on l y . 5 . a w o rd w r it e to u x txr e g trig gers the tra n s f er o f th e 9- bit dat a to th e tsr . seri al bit str eam w i l l s t art s h if tin g o u t with th e firs t ris i ng e dge o f th e b aud cl oc k. 6 . a tra n s m i t in terrupt w i l l b e ge nera t ed as per th e s e tti ng of c o n t rol bi t, utxi selx. 17. 4 b re ak and sync t r ans m i t sequen c e th e fo ll ow in g se qu enc e w i ll s en d a m es s a ge fram e h ead er ma de up o f a b r eak , fol l ow e d by an a u to -bau d sy nc by te. 1. c o nf i gu r e t h e u a r t fo r t he de si r e d m od e. 2 . se t ut xen a nd utxbrk ? s e t s up th e brea k c har act e r . 3 . l oad the u x t x r e g w i th a du mm y ch arac ter to i n iti a te tra n sm is s i on (va l ue is ig no red). 4 . w r ite ? 55h ? t o u x txr e g ? lo ads t he syn c c har act e r i n to the tran sm it fifo . 5 . af t e r t he break h a s be en sen t, the u txbr k b i t is r e se t by h a r d w a r e . t h e s y nc c h a r ac t e r n o w tra n s m i t s. 17. 5 r ecei vin g i n 8- bit or 9 - bit d a t a mode 1. se t u p the uar t (as des cri b e d in se ction 1 7 . 2 ? t rans mit t ing i n 8-bi t dat a mo de? ). 2. en abl e th e u a r t . 3. a re ce iv e i n ter r upt w ill be ge nera t ed w hen on e o r m o r e da ta c h a r ac t e r s ha ve be e n r e ce iv ed as pe r in terru pt c o n t rol bi t, urxisel x . 4. r e a d the o e r r bit t o dete r m i ne i f an ov erru n er ror has o c c u rre d. the o e r r bit m u s t b e res e t in so ft w a r e . 5 . re a d uxrxreg . th e a c t of read ing th e u x r x r e g ch arac ter w i l l m ov e th e nex t ch arac te r to t he to p of the re ce ive fifo , in c l u d i n g a ne w se t of p e r r an d fe r r v a l u es . 17. 6 o pera ti on of ux cts and ux rts cont rol pi ns uartx clear to send (ux cts ) a nd request to send (ux rts ) are the tw o h a rd w a re con t rol l ed pi ns th at a r e a sso ci a t ed w i t h t h e u a r t m o d u l e . th e s e t w o pi ns a l l o w t h e u a r t to op er a t e i n s i m p l e x an d f l o w c o n t r o l m ode . th ey a r e i m p l em en ted t o co ntro l th e tra n sm is - s i on and rec ept ion betw e e n t he d a t a t e rm ina l eq uip m e n t (d te). th e u e n <1: 0> bi t s i n the u x mo d e re gis t er co nfig ure the s e pin s . 17. 7 i nfr a red support th e u a r t m o d u le pro v i des tw o ty pes o f i n frar ed u a r t s upp ort: one is th e ir d a cl oc k o u tp ut to s upp ort ext e r- na l i r d a enc od er a nd dec od er d e vi ce (le gac y mo dul e s upp ort), an d th e o t he r is th e fu ll im pl em ent a t io n o f th e ird a en co der an d dec od er . n o te th at be ca use t h e ird a m ode s re qui re a 16 x ba ud c l o c k , the y w i l l onl y w or k whe n th e brg h b i t (ux m o d e<3 > ) i s ? 0 ?. 1 7 . 7 . 1 e xte r n a l i r d a su pp or t ? i r d a cl ock outp ut t o su ppo rt ex tern al ird a en cod e r an d dec o d e r de vic e s , t he b c lk x pi n ( s am e a s t he u x rts pi n) c an be c onf igu r ed to g ene rate th e 16x bau d cl oc k. wi th uen<1 : 0 > = 11 , the bc lkx pi n w i ll out put the 16 x ba ud cl oc k if the u a r t mo dul e is en abl ed. it ca n b e us ed to su ppo rt th e ird a c o d e c ch ip. 17. 7.2 b u i lt-in irda en co d e r a nd de coder th e u a r t ha s f ull im pl em ent atio n o f th e ird a enc od er an d dec od er a s p a r t o f th e u a r t m o d u le . t h e bui l t-i n ird a encod er a nd decod er f unctio n a lity i s ena ble d us in g th e ir en bit ( u xm od e< 12> ). wh en ena ble d (iren = 1 ), th e re cei v e pi n (u x r x ) ac t s a s t h e i n p u t fro m the in frare d rec e iv er . th e t r ans m i t pin (u x tx) a c t s as th e o u tp ut to th e in frare d tr ans mi tte r .
pic24fj64ga004 family ds39881d-page 162 ? 2010 microchip technology inc. regis t er 17-1: uxm o d e : uartx mode regis t er r/w - 0 u -0 r/w - 0 r /w -0 r / w - 0 u -0 r / w - 0 (3 ) r/w - 0 (3 ) uar t en (1 ) ? u sidl iren (2 ) rtsmd ? u en1 uen0 bi t 15 bi t 8 r/c-0 , hc r/w -0 r /w -0 , hc r/w -0 r / w -0 r/w -0 r /w -0 r/w -0 w ake l pback abaud r xi n v brgh pdsel1 p dsel 0 s t sel bi t 7 bi t 0 le gen d : c = cl e a r a b l e b i t hc = h a rd wa r e cl e a ra b l e b i t r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 uarten: uar t x en a b l e b i t (1 ) 1 = u ar tx is ena bl ed; all ua r t x pi ns are co ntro lle d b y ua r t x as def ine d b y ue n < 1 : 0> 0 = u ar tx i s di sa ble d; al l u a r t x pin s are co ntrol l e d by po r t l atc he s; u a r t x po w er co ns um ptio n is mi ni ma l bi t 14 un im pl e m e n te d : read as ? 0 ? bi t 13 usi d l : s t op in idle m ode bi t 1 = d i s c on t inu e m od ule op erat ion when de vi ce ent ers idl e m od e 0 = c o nti nue mo du le o pe r atio n i n id le mo de bi t 12 ir e n : irda ? enc o d e r an d d e co der e nab le bit (2 ) 1 = i rd a en cod e r a nd dec od er e nab led 0 = i rd a en cod e r a nd dec od er d i sa bl ed bi t 1 1 rt sm d: m o d e se lec t io n f o r u x r ts pi n bit 1 =uxrts pin in simplex mode 0 =uxrts p i n i n f l ow c o nt r o l m o d e bi t 10 un im pl e m e n te d : r ead as ? 0 ? bi t 9- 8 uen1 :uen0 : uar t x en a b l e b i t s (3 ) 11 = u xt x , u x r x an d b c lk x pi ns ar e en a bled and used; uxcts pin controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pin s a r e e nab le d an d u sed 01 = uxtx, uxrx and uxrts pin s a r e e nab le d an d u s ed; uxcts pi n c o n t rol l ed by po r t l a tc he s 00 = u xtx an d u x r x p i n s a r e en ab le d an d use d; uxcts and uxrts / b c l k x pi ns co nt r o l l e d by p o r t la tc he s bi t 7 w ake: w a k e -u p o n s t art bit d e tec t d u ring sle ep mo de en ab le b i t 1 = u ar tx w ill co nti nue to sa mpl e t he u x r x pi n; inte rrup t ge nera t ed on fal lin g e dge , bi t c l ea red in ha r dw ar e on f ol l o w i ng r i s i ng ed g e 0 = n o w a k e -up en abl ed bi t 6 l p bac k: u a rtx loopb ac k m o d e se lec t b i t 1 = e na bl e lo op b a c k m o d e 0 = l oop ba ck mo de is di sab le d bi t 5 abaud: au to-ba ud enab le bit 1 = e n a b l e ba ud ra te m eas ure m e n t on the n e xt c h a r ac ter ? re qui res rece pti on o f a syn c fi eld ( 5 5h ); c l e a red in ha rdw a re up on com p l e ti on 0 = b a u d rate me as urem en t d i sa bl ed or c o m p le ted note 1 : if uar t en = 1 , th e p e rip h e r al i n p u t s an d ou tpu t s mu st be c o n f ig ured to an ava i l abl e r p n pin . se e se ction 1 0 .4 ?p er ip her a l pin se lect ? f o r m o re inf o rm ati on. 2: th is fea t ure is on ly av ail a b l e f o r th e 1 6 x br g mo de ( b r g h = 0 ). 3: bi t av ai lab ili ty dep en ds on p i n av ail abi li ty .
? 2010 microchip technology inc. ds39881d-page 163 pic24fj64 ga004 family bi t 4 rxi n v : rec e iv e pola rity in ver s io n b i t 1 = u xrx i d l e stat e is ? 0 ? 0 = u xrx i d l e stat e is ? 1 ? bi t 3 brgh: h i g h ba ud r a te enab le bit 1 = b r g g ene rate s 4 cl oc ks pe r bi t pe rio d (4 x b aud cl oc k, h i gh -s p eed m ode ) 0 = b r g g ene rate s 1 6 c l o c k s p e r b i t p e ri od ( 16x ba ud cl ock , s t a nda rd m o d e ) bi t 2- 1 pdsel 1:pdsel0 : pari ty and dat a sel e c t io n b i t s 11 = 9 - bit dat a, n o p a rit y 10 = 8 - bit dat a, o dd p a ri ty 01 = 8 - bit dat a, e v e n p a rity 00 = 8 - bit dat a, n o p a rit y bi t 0 st sel: s t op bit sel e c t ion bi t 1 = t w o s t op bi t s 0 = one stop bit regis t er 17-1: uxm o d e : uartx mode regis t er ( c o n t i nued ) note 1 : if uar t en = 1 , the p erip he r al i np ut s an d outpu t s mu st be c on f ig ured to an ava i l abl e r p n pin . see se ction 1 0 .4 ?p er ip her a l pin se lect ? f o r m o re inf o rm ati on. 2: th is fea t ure is on ly av ail a b l e f o r th e 1 6 x br g mo de ( b r g h = 0 ). 3: bi t av ai lab ili ty dep en ds on p i n av ail abi li ty .
pic24fj64ga004 family ds39881d-page 164 ? 2010 microchip technology inc. regis t er 17-2: uxs t a: uartx s t atus and c o n t r o l r e gis t e r r/w - 0 r /w -0 r/w - 0 u -0 r/w - 0 , hc r/w - 0 r -0 r-1 utxi sel1 u txinv u txisel0 ? u txbrk u txen (1 ) utx b f trmt bi t 15 bi t 8 r/w - 0 r /w -0 r/w -0 r -1 r-0 r -0 r/c-0 r -0 urxis el 1 u r x i sel 0 a dden r idl e perr f er r o e r r urxda bi t 7 bi t 0 le gen d : c = cl e a ra b l e b i t hc = h a rd wa r e cl e a ra b l e b i t r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 , 1 3 ut xisel1: u t xisel0 : t r an sm is si on inte rrupt mo de sele ct ion bit s 11 = r es er v ed ; do no t us e 10 = i nter rupt w h en a c h a r ac ter is tran sf erred to the t r ans m i t shi f t r e g i s t er (tsr ) a nd as a res u l t, the t r ans m i t b u f f er b e c o m e s em pty 01 = i nter rupt w hen th e l a s t c har act e r i s sh if te d o u t of t he t r an sm it shif t r e g i s t er; all tra n s m i t o per atio ns are co mp let e d 00 = i nter rupt when a c h a r ac ter i s t r ans fe rred to th e t r a n s m i t shi f t r e gis t er (thi s i m p lie s there is at l e a s t o ne ch arac ter ope n i n th e tra n s m i t bu f f e r) bi t 14 ut xinv : irda ? en co der t r ans mi t po lari ty inv e rs ion bi t if iren = 0 : 1 = ux tx id le ? 0 ? 0 = ux tx id le ? 1 ? if iren = 1 : 1 = ux tx id le ? 1 ? 0 = ux tx id le ? 0 ? bi t 12 un im pl e m e n te d : r ead as ? 0 ? bi t 1 1 ut xbr k : t r ans m i t bre a k bi t 1 = s e n d syn c break o n n e xt tran sm is si on ? s t a r t b i t, foll owed by twe l v e ? 0 ? b i t s , fo ll ow ed by s t op bit ; c l e a red by ha rdw a re up on co mp leti on 0 = s y nc bre ak tran sm is si on d i s abl ed or c om pl eted bi t 10 ut xen: tran sm it enab le bit (1 ) 1 = t ra ns mi t en ab led , ux t x pi n c ont roll ed by ua r t x 0 = t rans mit disable d , an y pending transm i ssio n is a bor ted a nd b u f f er i s r e s e t. u x tx pin controll ed b y the po r t register . bi t 9 ut xbf: t r an sm it buf f er f u ll s t atu s b i t ( r ead -onl y) 1 = t ra ns mi t bu f f e r is fu ll 0 = t ra ns mi t bu f f e r is n o t fu ll , at lea s t one mo re c h a r ac ter c a n be writte n bi t 8 tr m t : t r an sm it shif t r e g i s t er em pt y b i t (re ad -onl y) 1 = t ra ns mi t shif t r e gis t er is emp t y a nd tran sm it bu f f e r i s em pty (the l a st tra n s m i s s i o n h a s c o m p l e ted ) 0 = t ra ns mi t shi f t r e gist e r is no t em pty , a t r ansm i ss io n i s i n p r ogre s s or que ued bi t 7- 6 urxis el1 : urxisel 0 : r e cei v e int e rrupt m ode sel e c t io n bi t s 11 = i nter rupt is se t on rs r tra n s f er , ma kin g t he re ce iv e b u f f e r fu ll (i.e ., h a s 4 d a t a ch arac ters ) 10 = i nter rupt is se t on rs r tra n s f er , ma kin g t he re ce iv e b u f f e r 3 / 4 fu ll (i.e ., h a s 3 d a t a ch arac ter s ) 0x = i nter rupt i s s e t w h e n an y ch ara c te r is re ce iv ed an d tra n s f erre d from the r s r to the re ce iv e buf f er . r e ce iv e buf f e r ha s one or m o re ch ara c te rs. note 1 : if uar t en = 1 , th e p e rip h e r al i n p u t s an d ou tpu t s mu st be c o n f ig ured to an ava i l abl e r p n pin . se e se ction 1 0 .4 ?p er ip her a l pin se lect ? f o r m o re inf o rm ati on.
? 2010 microchip technology inc. ds39881d-page 165 pic24fj64 ga004 family bi t 5 adden: ad dre s s c har act e r d e tec t bi t (bi t 8 of re ce iv ed dat a = 1 ) 1 = a d d re ss dete ct mo de e n a b le d. if 9-b i t m o d e i s n o t s e l e c t ed, thi s d o e s n o t t a ke ef fec t . 0 = a d dre ss d ete ct mo de d i s abl ed bit 4 ri d l e: r e c e i v er idl e bi t (re ad-o n l y ) 1 = r ec ei ve r i s i d l e 0 = r ec ei ve r i s ac t i v e bi t 3 pe r r : parit y erro r s t atu s bit (read -on l y ) 1 = p ar i t y er r o r ha s b e e n de t e c t ed f o r t h e cu r r e nt ch a r ac t e r ( c h a r ac te r a t t h e t o p o f t h e r e ce i v e f i f o ) 0 = parit y e rror h a s no t be en dete c te d bi t 2 f e rr: fram in g erro r s t atu s bit (read -on l y ) 1 = f ram i ng error h a s b een dete c t ed fo r t he c u rre nt ch ara c te r (cha rac t er a t the to p of th e rec e i v e f i fo ) 0 = fram in g er ror h a s not bee n d e te cte d bi t 1 oerr: re cei v e buf f er ov erru n erro r s t atu s bit (cl ear/ r ead -onl y) 1 = r ec ei ve b uff er h as o v er f l ow e d 0 = r e c e i v e b u f f e r h a s no t ov erf l ow e d (c le arin g a pre v i ous ly s e t oer r b i t ( 1 ? 0 trans i t i on ) w i l l re se t t he r ece iv er b uf f er a nd the r s r to t he emp t y st ate) bi t 0 urxda: re ce iv e buf f e r da t a a v ail a b l e b i t (read -onl y) 1 = r e c e i v e bu f f e r ha s dat a ; a t le as t one m o re ch arac ter ca n be rea d 0 = r ec ei ve b uff er i s em pt y regis t er 17-2: uxs t a: uartx s t atus and c o n t r o l r e gis t e r (continue d) note 1 : if uar t en = 1 , th e p erip he r al i np ut s an d outpu t s mu st be c on f ig ured to an ava i l abl e r p n pin . see se ction 1 0 .4 ?p er ip her a l pin se lect ? f o r m o re inf o rm ati on.
pic24fj64ga004 family ds39881d-page 166 ? 2010 microchip technology inc. regis t er 17-3: uxtx reg: uart x t ran smi t regis t er u - x u -x u-x u -x u-x u -x u-x w -x ? ? ? ? ? ? ?u t x 8 bi t 15 bi t 8 w- x w- x w - x w - x w- x w- x w- x w - x utx7 utx6 ut x5 utx4 utx3 utx2 utx1 ut x0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 9 un im pl e m e n te d : read as ? 0 ? bi t 8 ut x8 : d a t a o f th e t r an sm it ted c harac te r bi t (i n 9-b i t mo de) bi t 7- 0 ut x7 :utx0 : d a t a of the t r ans m i tte d c h arac ter bit s regis t er 17-4: uxrx re g : ua rtx re cei v e re g i ste r u-0 u -0 u-0 u-0 u-0 u-0 u-0 r-0 ? ? ? ? ? ? ?u r x 8 bi t 15 bi t 8 r-0 r -0 r-0 r -0 r-0 r -0 r-0 r -0 urx7 urx6 u r x 5 urx4 urx3 urx2 urx1 u r x 0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 9 un im pl e m e n te d : r ead as ? 0 ? bi t 8 urx8 : d a t a of the r e c e iv ed c hara c t e r bi t (i n 9 - bit mo de) bi t 7- 0 urx7:urx0: data of the received character bits
? 2010 microchip technology inc. ds39881d-page 167 pic24fj64 ga004 family 1 8 .0 p a rallel maste r port (p mp ) th e paral l el m a s t er port (pmp) mo dul e is a p a ra lle l 8 - bit i/o mo dul e, s pec ifi c a lly de si gne d to c o m m uni ca te w i th a w i de v ari ety o f p ara lle l dev ic es , su ch as co mm u- n i c a tio n per iph e ral s , lc d s , ex tern al me mo ry de vi ce s a nd m i cr oco ntro lle rs. be ca use t he in terfa c e t o p ara lle l periphe r al s v a r i es si gn i f ic an t ly , t h e p m p i s h ig h ly c onf igu r ab le. ke y fe atu r es of the pmp m o d u l e in cl ude : ? u p to 1 6 pro g ram m abl e ad dres s lin e s ? o ne ch ip sel e c t li ne ? p ro gram m abl e s t rob e o p t i on s: - i n d iv id ual re a d an d w r it e s t rob e s or; - r ea d/w r it e s t rob e wi th en abl e s t rob e ? a d d res s auto -inc rem ent /auto - d e c r em ent ? p ro gram m abl e ad dres s/ d a t a mu lti p le xi ng ? p ro gram m abl e po lari ty on c o ntro l si gna ls ? l e g a c y para lle l sl av e po rt sup por t ? e n han ce d par a ll el slav e su ppo rt: - a d d res s supp ort - 4 -by t e deep aut o -in c re m e n t in g bu f f e r ? p ro gram m abl e w a it s t a t es ? s e l ec t a b l e input voltage levels figure 18-1: pmp modul e ov er vie w note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e s our c e . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ?s ec tion 1 3 . p a ralle l m ast er port (pm p )? (d s397 13 ). note : a number of the pins fo r th e pmp are n o t p r es ent on pic 2 4fj 6 4 g a0 04 de vi ces . r e f e r t o th e spe c i f ic d e vi ce ? s p i no ut to d eter m in e w h ic h pi ns are av ai lab l e. pm a< 0> pm be pm r d pm w r pmd<7: 0> pm en b pm r d / pm wr pmcs1 pm a< 1> pm a<10: 2> pm all pm alh pm a< 7: 0> pm a<15: 8> eeprom addr ess bus d a ta b u s cont rol lines pic2 4f lcd fifo microcontroller 8 - bi t dat a up t o 1 1 -b i t a ddres s par a l lel m a s t er po r t buffer note 1 : pm a<10 :2> are not av ail a b l e o n 2 8 -pi n d e v i c e s. (1)
pic24fj64ga004 family ds39881d-page 168 ? 2010 microchip technology inc. regis t er 18-1: pm con: par a ll e l p o r t contro l regis t er r/w - 0 u -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 p m pen ? psidl adrmux1 (1 ) adrmux0 (1 ) ptb een ptwren ptrden bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 (2 ) u-0 r /w -0 (2 ) r/w - 0 r /w -0 r/w - 0 csf1 csf0 al p ? c s1p bep wrsp rdsp bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 pm pen: pa ral l el m a s t e r por t ena b le bi t 1 = p m p e nab led 0 = p m p d i s abl ed, no of f-ch ip acc e s s perf o rm ed bi t 14 un im pl e m e n te d : r ead as ? 0 ? bi t 13 ps idl: s t op in idl e m ode bi t 1 = d i s c on t inu e m od ule op erat ion w hen de vi ce ent ers idl e m od e 0 = con ti nue mo du le o pe r atio n i n id le mo de bi t 12 - 1 1 adrmux1 : adrmux 0 : ad dres s/ d at a mu lti ple xi ng se le cti on bit s (1 ) 11 = r es er v ed 10 = a l l 1 6 b i t s of add res s a r e m u l t ip lex e d on pmd < 7:0> pi ns 01 = l ow er 8 bit s o f a ddr ess a r e mu ltip le xed o n pm d < 7: 0> pin s , up per 3 b i t s a r e mul t ip lex ed on pm a<1 0 :8 > 00 = a d d re ss an d da t a app ear on sep a ra te p i ns bi t 10 pt been: byt e en abl e po rt ena b l e bi t (1 6-bit ma ste r m ode ) 1 = pmbe po rt e nab led 0 = pm be po rt d i sa bl ed bi t 9 pt wren: w r i t e e n ab l e s t r o be p o rt e n ab l e b i t 1 = p mw r / pm e n b po r t en ab l e d 0 = p m w r / p m en b p o rt d i s abl ed bi t 8 pt rden: r ead /w rite s t robe port enab le bit 1 = p mrd/pmwr port enabled 0 = pmrd/pmwr p o rt d i s abl ed bi t 7- 6 csf 1 :csf0 : c h ip sel e c t fu nc tion bi t s 11 = res e rv ed 10 = pm c s 1 f unc tio ns as ch ip se t 01 = res e rv ed 00 = res e rv ed bi t 5 al p: add r es s l a tc h po lari ty bit (2 ) 1 = a c t i v e- hig h (pm a ll an d pm alh ) 0 = a c t i v e- low (pm a ll and pmalh ) bi t 4 un im pl e m e n te d : r ead as ? 0 ? bi t 3 cs1 p : chi p se lec t 1 pol a rit y bit (2) 1 = active-high (pmcs1/pmcs1) 0 =active-low (pmcs1 /pmcs 1 ) note 1 : pm a<1 0 :2> are no t av ai lab l e on 2 8 -p in d e v i c e s . 2: th es e b i t s ha ve no ef fec t w h e n their corresponding pins are used as address lines.
? 2010 microchip technology inc. ds39881d-page 169 pic24fj64 ga004 family bi t 2 bep: byte ena b le pol a ri ty b i t 1 = byte enable active-high (pmbe) 0 = byte enable active-low (pmbe ) bi t 1 w r sp: w r i t e s t r o b e p o la r i ty bi t for slave modes and master mode 2 (pmmode<9:8> = 00,01,10 ): 1 = w rit e s t rob e a c ti v e -hig h (pm w r) 0 = write strobe active-low (pmwr ) for master mode 1 (pmmode<9:8> = 11 ): 1 = e n a b l e s t ro be a c t i ve -hi gh (pmen b ) 0 = enable strobe active-low (pmenb ) bi t 0 rdsp: r ead s t robe pol a rit y b i t for slave modes and master mode 2 (pmmode<9:8> = 00,01,10 ): 1 = r e ad stro be ac tiv e -hi gh (pmr d ) 0 = read strobe active-low (pmrd ) for master mode 1 (pmmode<9:8> = 11 ): 1 = read/write strobe active-high (pmrd/pmwr ) 0 = read/write strobe active-low (pmrd /pmwr) regis t er 18-1: pm con: par a ll e l p o r t contro l regis t er (continu ed) note 1 : p m a < 10 : 2 > a r e n o t a v a il a bl e on 28 - p i n de vi ce s. 2: th es e b i t s ha ve no ef fec t w h e n th eir co rres pon din g p i ns are us ed as ad dres s lin es .
pic24fj64ga004 family ds39881d-page 170 ? 2010 microchip technology inc. reg i s t er 18- 2: pm mo de : par a lle l p o r t mo d e r e g i st er r-0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 busy irqm 1 i r q m 0 i n c m 1 i ncm 0 m ode16 m ode1 m o de0 bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 wa i t b 1 (1 ) wa i t b 0 (1 ) wa i t m 3 wa i t m 2 wa i t m 1 wa i t m 0 wa i t e 1 (1 ) wa i t e 0 (1 ) bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 busy : bu sy bi t (m ast e r m o d e on ly ) 1 = p or t is bu sy ( n o t usef u l wh e n t h e p r oc es so r stal l is a c ti ve ) 0 = p or t is no t bu sy bi t 14 - 1 3 i r qm 1:ir q m 0: in terr upt r equ est mo de bit s 11 = i nter rupt ge nera t ed whe n read buf f e r 3 is re ad or w r i t e buf f er 3 is writt en (buf fere d psp m o de ) o r on a r ead or w r i t e o per ation w h en pma<1 : 0> = 11 (addre s s a b l e p sp mo de onl y) 10 = n o in terru pt g ene rated, p r oc es so r st all ac tiv a te d 01 = i nter rupt gen era t ed at th e e nd of t h e re ad /w rite cy cl e 00 = n o in terru pt g ene rate d bi t 12 - 1 1 i n c m 1:i n c m 0: inc r em en t mode bit s 11 = p s p rea d an d wri t e b u f f ers au to-i nc rem ent (leg ac y psp m o de onl y ) 10 = d e c re m e n t addr<1 0 :0 > b y 1 e v e r y re a d /wri t e cy cl e 01 = i nc rem ent ad d r < 10:0> b y 1 ev ery rea d /w ri te c y c le 00 = n o i nc r em en t or d ec r em e nt of a dd r e s s bi t 10 m o d e 16: 8/16- b it mo de bit 1 = 1 6 - bi t mo d e : d a t a r e gi st e r is 16 b i ts , a r e ad or w r i t e t o t h e d a t a r e gi st e r in vo k e s tw o 8 - bi t t r an sf e r s 0 = 8 -bi t m ode : d a t a reg i s t er i s 8 bi t s , a read or w r i t e t o th e d a t a re gis t e r inv o k e s on e 8 - bit tran sfe r bi t 9- 8 mode 1 : mo de 0: par a ll el port m o d e se lec t b i t s 11 = m as ter mo de 1 (pm c s1, p m r d / pm wr , pm enb, pm be, pm a an d pm d<7: 0>) 10 = m as ter m o de 2 (pm c s1, p m rd, pm wr, pm be, pm a< x : 0 > a nd pm d<7 : 0>) 01 = e nh an c e d p s p , control signals (pmrd , pmwr , pmcs 1 , p m d < 7 :0> and pm a<1:0 > ) 00 = l ega cy pa rall el slav e po rt, c o n t rol si gna ls (pm r d , pmwr , pmcs 1 a nd p m d < 7 : 0>) bi t 7- 6 w a itb1 : w aitb0 : dat a setu p to rea d /w rite w a i t s t at e con f ig urat ion bi t s (1 ) 11 = d ata w a i t of 4 t cy ; m ul t ip lex ed ad dres s pha se of 4 t cy 10 = d ata w a i t of 3 t cy ; m ul t ip lex ed ad dres s pha se of 3 t cy 01 = d ata wa i t of 2 t cy ; m ul t ip lex ed ad dres s pha se of 2 t cy 00 = d ata wa i t of 1 t cy ; m ul t ip lex ed ad dres s pha se of 1 t cy bi t 5- 2 wa i t m 3 : wa i t m 0 : re a d t o by te en abl e s t ro be w a it s t ate c onfi gur atio n b i t s 11 11 = w a it o f a ddi tio nal 15 t cy .. . 00 01 = w a it o f a ddi tio nal 1 t cy 00 00 = n o add iti ona l w a it c y c l e s ( ope rati on f o rc ed into on e t cy ) bi t 1- 0 wa i t e 1 : w a i t e 0 : da t a ho l d af ter s t ro be w a it s t a t e c o nfi gura t io n b i t s (1 ) 11 = w a i t of 4 t cy 10 = w a i t of 3 t cy 01 = w a i t of 2 t cy 00 = w a i t of 1 t cy note 1 : w a i tb an d w a it e bi t s are ign o red wh e nev er w a itm 3 :w ait m 0 = 0000 .
? 2010 microchip technology inc. ds39881d-page 171 pic24fj64 ga004 family regis t er 18-3: pm addr: p arallel port addr es s r e gis t er u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ?cs1 ? ? ? a ddr<1 0 :8 > (1 ) bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ad d r < 7:0> (1 ) bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 cs1 : chi p se lec t 1 bit 1 = c hi p s e l e ct 1 i s a c t i ve 0 = c h ip se lec t 1 is in act iv e bi t 13 - 1 1 un im pl e m e n te d : read as ? 0 ? bi t 10 - 0 addr1 0 : addr0 : p a r a l l e l p o r t de s t in at i o n a d dr e s s bi ts (1 ) note 1 : p m a < 10 : 2 > a r e n o t a v a il a bl e on 28 - p i n de vi ce s. regis t er 18-4: pm aen : para lle l port e nable re g i ste r u-0 r /w -0 u-0 u-0 u-0 r/w-0 r/w- 0 r /w -0 ?p t en14 ? ? ?pten10 (1 ) pten9 (1 ) pten8 (1 ) bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 pten7 (1 ) pten6 (1 ) pten5 (1 ) pt en 4 (1 ) pt en3 (1 ) pten2 (1 ) pt en 1 p t e n0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : read as ? 0 ? bi t 14 pt en14: pmc s 1 s t robe ena b le bi t 1 = p m c s1 func ti ons as c hip se le ct 0 = p mc s 1 p i n f u nc t i o ns as po r t i/ o bi t 13 - 1 1 un im pl e m e n te d : read as ? 0 ? bi t 10 - 2 pt en10:pt en2: pm p ad dres s port en ab le b i t s (1 ) 1 = p m a <1 0:2 > fu nc tion as pm p ad dres s lin es 0 = p m a <1 0:2 > fu nc tion as po rt i/ o bi t 1- 0 pt en1:pten0 : pm alh/pm all s tr obe ena b le bi t s 1 = p m a 1 and pm a0 fu nc tion as ei the r pm a<1:0 > o r pma l h an d pm all 0 = p m a 1 and pm a0 p ads fu nct i on s a s p o rt i/o note 1 : p m a < 10 : 2 > a r e n o t a v a il a bl e on 28 - p i n de vi ce s.
pic24fj64ga004 family ds39881d-page 172 ? 2010 microchip technology inc. regis t er 18-5: pm st a t : paralle l p o rt st atus re g i ste r r-0 r /w -0 , hs u-0 u -0 r-0 r -0 r-0 r -0 ibf i bo v ? ? i b3 f i b2f i b1f i b0f bi t 15 bi t 8 r-1 r /w -0 , hs u-0 u -0 r-1 r -1 r-1 r -1 obe obuf ? ? o b3e o b2e o b1 e o b0 e bi t 7 bi t 0 le gen d : hs = ha r d wa re se t b i t r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 ib f : in put buf f er f u ll s t atu s b i t 1 = a ll w r ita b l e i n pu t bu f f e r r e g i s t er s ar e fu l l 0 = s o m e or all of the w r it a b le in put buf fer regi st ers are em pty bi t 14 ib o v : i n pu t b u ff er ov er f l ow s t a t u s bi t 1 = a w r ite atte mp t to a f u ll in put by te re gis t er oc cu rred (mu s t b e c l e a red in so f t w a re ) 0 = n o ov erfl ow o c c u rre d bi t 13 - 1 2 un im pl e m e n te d : r ead as ? 0 ? bi t 1 1- 8 ib 3 f : i b 0 f in put buf f er x s t atu s ful l bi t s 1 = i npu t bu f f e r c ont ain s d a t a tha t ha s not bee n re ad ( r ead ing bu f f e r w i l l c l ea r th is bit ) 0 = i npu t bu f f e r do es no t co nt a i n any un rea d da t a bi t 7 obe: o u t put buf f er em pt y s t a t us bi t 1 = a l l re ad abl e ou tpu t bu f f e r re gis t ers ar e em pt y 0 = s o m e or all of the readabl e o u tp ut b u f f er re gis t e r s a r e fu ll bi t 6 obuf: o u tput buf f er u n de rflow s t a t us bi t s 1 = a read oc cu rred from a n em pt y o u tp ut b y te reg i s t er (m us t b e c l ea red in so f t w a re ) 0 = n o un derf l ow o c c u rre d bi t 5- 4 un im pl e m e n te d : read as ? 0 ? bi t 3- 0 ob3 e :o b0e ou t p ut b u ff er x s t at u s e m p t y b i ts 1 = o u t put buf fe r is em pty (w ri ting da t a t o th e b u f f e r w i ll c l e a r th is bi t) 0 = o u t put buf fe r co nt a i ns da t a that ha s n o t b een tra n sm it ted
? 2010 microchip technology inc. ds39881d-page 173 pic24fj64 ga004 family regis t er 18-6: p adc f g 1 : p ad c o n f i g u ration control re g i ste r u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? r t secsel (1 ) pmp ttl bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t i s s e t ? 0 ? = bit is cl eare d x = bit i s unk no w n bi t 15 - 2 u n im plem ent e d: r e ad as ? 0 ? bi t 1 rtsecsel: r t cc se c o n d s cl o c k ou tp u t se l e ct b i t (1 ) 1 = r t cc se co nd s c l o c k is se le ct e d f o r th e r t cc p i n 0 = r t c c al ar m pu l s e i s s e l e ct e d f o r t h e r t c c pi n bi t 0 pm pttl: pm p m o d u l e tt l in put buf f er se lec t b i t 1 = p m p mo dul e u s e s t t l i npu t b u f f e rs 0 = p m p mo dul e u s e s sc hm itt t r ig ger inp u t b u f f ers note 1: to enable the actual rtcc output, the rtcoe (rcfgcal) bit needs to be set.
pic24fj64ga004 family ds39881d-page 174 ? 2010 microchip technology inc. figure 18-2: legacy p ara l l e l sl av e p o rt ex amp l e figure 18-3: addre ss able pa rallel s l ave p o r t ex amp l e t a ble 1 8 -1: s lav e mode addre ss re solution figure 18-4: mas t er mode, dem u lti ple x e d ad dres s i ng (se p arate re ad and w rite s t robes , s i ngle chip se lect) pm a<1:0 > o u tput re gis t er (buffe r) in put re giste r (buffer) 00 pm d o u t 1<7 : 0> (0) p m d in 1< 7:0> (0) 01 pm do ut1 < 15 :8> (1) p m d in1<1 5 :8 > (1) 10 pm d o u t 2<7 : 0> (2) p m d in 2< 7:0> (2) 11 pm do ut2 < 15 :8> (3) p m d in2<1 5 :8 > (3) pm d<7: 0> pm r d pmwr master a ddress bu s d a ta b u s cont rol lines pm c s 1 pmd<7: 0> pm r d pmwr pic24f sl ave pm c s 1 p m d<7: 0> pm r d pm w r master pm c s 1 pma< 1: 0> a ddress b u s da t a b u s c ont rol lines pmr d pmwr pic24f s l ave pm c s 1 pm dout 1l ( 0 ) p m dout 1h (1) p m dout 2l (2) p m dout 2h (3) p m di n1l (0) p m din1h ( 1 ) p m di n2l (2) p m din2h (3) pmd<7: 0> wr i t e a ddres s decode r ead addr ess dec ode pm a< 1 : 0 > pm rd pm wr pmd<7 : 0 > pm cs1 pm a<1 0 : 0 > pic 24f addr ess bus data bus control lines
? 2010 microchip technology inc. ds39881d-page 175 pic24fj64 ga004 family figure 18-5: mas t er mode, par t ially m u ltiple x e d add res s i n g ( s ep arate rea d and w r ite st r o be s , si ngl e chi p s e le ct) figure 18-6: mas t er mode, fully m u lti ple x e d add res s i n g ( s ep arate rea d and w rite s t robes , s i ngle chip se lect) figure 18-7: ex amp l e o f a multip l ex ed addre ss ing ap plica t i o n figure 18-8: ex amp l e o f a par t i a lly m u ltiple x e d addr es sin g app l ication pm rd pm wr pm d<7 : 0 > pm cs1 pm a<1 0 : 8 > pm al l pm a<7 : 0 > pic24f address bus multiplexed data and address bus control lines pm rd pm wr pm d<7 : 0 > pm cs1 pm al h pm a<1 5 : 8 > pic2 4f multiplexed data and address bus control lines pm al l pm a<7 : 0 > pmd< 7:0 > pm alh d<7: 0> 37 3 a<15: 0> d<7: 0> a<7: 0> 37 3 pm r d pmwr oe wr ce pic24f add r ess bus d a ta b u s cont rol lines pmcs 1 pmall a< 15 : 8 > pm a< 1 0 : 8 > d<7: 0> 373 a<1 0 :0 > d<7: 0> a< 7: 0 > pm r d pmwr oe wr ce pic24f a ddress b u s dat a b u s cont rol li nes pmcs 1 pmall a < 10: 8> pmd<7: 0>
pic24fj64ga004 family ds39881d-page 176 ? 2010 microchip technology inc. f i g ure 18- 9: ex amp l e of a n 8- bit m u l t i ple x e d add res s a nd dat a ap plic ation figure 18-10 : p ar allel e e p r om e x a m ple (up to 1 1 - b i t addre ss , 8-bit dat a) figure 18-1 1 : p ar allel e e p r om e x a m ple (up to 1 1 - b i t addre ss , 16 - b it dat a) figure 18-12 : l cd control e x am ple (byte mode ope ration) ale pm r d pmwr rd wr cs pi c24f address bus data bus control lines pmcs 1 pmall ad<7:0> p a ral l el peri p h eral p m d<7: 0> pm a< n : 0 > a < n: 0> d<7:0> pm r d pmwr oe wr ce pi c24f address bus data bus control lines pmcs 1 pmd<7:0> parallel eeprom pm a< n:0 > a < n: 1> d< 7 : 0 > pmrd pmwr oe wr ce pi c24f address bus data bus control lines pmcs 1 pmd<7:0> parallel eeprom pmbe a0 pmrd/pmwr d<7:0> pi c24f addr ess bus d a ta b u s cont rol lines pma0 r/w rs e lcd controller pm c s1 pm < 7 :0>
? 2010 microchip technology inc. ds39881d-page 177 pic24fj64 ga004 family 19 .0 re al-t ime clock and cale ndar ( r tcc) figure 19-1: rtcc block diagram note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e s our c e . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ?section 29 . r eal-t ime c l ock and calendar ( r tcc ) ? (d s39696). r t cc p r es c a lers r t cc t im e r comp ar at or co mp are registers repeat counter ye ar mt hdy w k dy hr mi nse c a l mthdy alwdhr alminsec with mas k s r t cc interrupt logic rcfg ca l al c f gr p t ala r m ev ent 32. 7 68 khz i npu t fr o m so sc os c i ll a t o r 0. 5s rt cc c l o ck do main al arm p u l s e r t cc i nterrupt cp u cl o ck do m a i n rtcva l alr m v a l rtcc pin rtcoe
pic24fj64ga004 family ds39881d-page 178 ? 2010 microchip technology inc. 19. 1 r tcc modul e regist ers th e r t c c mod u l e reg i s t ers are o r ga niz e d int o thre e ca t e g o r ie s: ? r t c c cont rol r e gi ste r s ? r t cc v a l u e re g i ste r s ? a l a rm v a lu e r e g i s t ers 19. 1.1 r eg is t e r ma pp ing t o l i m i t the reg i st er i n te rfac e, the r t c c t i me r an d a l a r m t i me r e gi st e r s a r e ac ce ss ed t h r o ug h c o r r e - s pon di ng reg i s t er po int e rs . t he r t c c v a lu e reg i s t er w i ndo w (r tc v a lh an d r t c v all ) us es the r t c p tr bi ts ( r c f g c a l < 9 :8 > ) t o s e le ct t h e de si r e d t i me r re gis t er p a i r (s ee t a b l e 19- 1). by wri t in g the r t cv al h by te, th e r t cc poin ter v a lu e, r t c p tr <1: 0 > b i t s , d e c r em ent b y one un til the y reac h ? 00 ?. o n c e t hey reac h ? 00 ? , t he mi n u tes a nd sec - onds val u e wi l l b e a c c e s s i b l e th ro u g h r t cv al h a n d r t c v al l u n til th e po in ter v a l ue i s ma nua lly c han ged . t a ble 1 9 -1 : r tcv a l re giste r m a pp ing th e ala r m v a lu e regi st er w i nd ow (alr m v al h an d al r m v a ll ) us es t he alr m ptr bit s (al c fg r p t<9: 8>) to s e l e c t th e d e s i red al arm reg i s t er p a ir (se e t abl e 1 9-2). by w r iti ng th e alr m v a lh by te, th e al arm po inter v a l ue, alr m ptr < 1 : 0> bi t s , de cre m e n t by on e unti l th ey re ac h ? 00 ? . on ce t hey reac h ? 00 ?, the alr m m i n a nd alr m sec va lue w ill b e ac ce ss ib le th roug h al r m v a lh a nd alr m v a ll un til the po inte r v a lu e i s m a n ual ly ch ang ed. t able 1 9 -2: a lrmv al re g i ste r m a ppi n g c on s i deri ng t hat th e 16 -bi t cor e doe s n ot di sti ngu is h be tw ee n 8 - bit and 16 -bit rea d op era t io ns, the us er m u s t be a w are th at w h e n read ing e i th er the al r m v a lh or al r m v a ll by tes w ill de cre m e n t t he a l r m p t r < 1:0 > v a lu e. th e s a m e ap pli e s t o the r t c v alh or r t c v al l by te s w i th t he r t c p tr <1 :0> bei ng decrem e n t ed. 19. 1.2 w rit e lo ck in orde r to p e rfo r m a w r i t e t o an y of the r t c c t i m e r re g i ste r s, th e r t cwren b i t (rcfgc al <1 3 > ) mu s t b e s e t (r efer to ex am pl e 1 9-1). ex amp l e 19-1: se tting the rtcwr e n b i t rt c p t r <1:0 > rtcc v a l u e re gis t e r w i nd ow rtcv al <1 5 : 8 > rt c v al<7 :0 > 00 minutes seco nds 01 w eekda y ho urs 10 mon t h d a y 11 ? yea r alrm pt r <1 : 0 > a l ar m v alue re gist er w i nd ow alrmv a l< 1 5 : 8 > alrmv a l< 7 : 0 > 00 alrm m i n a lrm sec 01 al rm w d al rmhr 10 al rm mnth al rmda y 11 ?? note : th is o n ly app lies to read operations and not write operations. note : t o av oi d a c c i de nt a l w r it es to th e ti me r , i t is re com m end ed tha t t h e r t c w r e n bi t ( r c f gc a l <1 3 > ) i s ke pt cl ea r at an y ot her ti me . f o r the r t cwren b i t to be s e t, th ere i s on ly 1 ins t ruct i on c y c l e ti me w i n dow al low e d betw e en th e 5 5h/ aa s equ enc e and th e s e tt ing of r t c w r e n ; th eref ore, it i s r eco mm en ded tha t c ode f ol l ow t h e p r oc ed u r e i n e x am pl e 1 9 - 1. asm volatile("push w7"); asm volatile("push w8"); asm volatile("disi #5"); asm volatile("mov #0x55, w7"); asm volatile("mov w7, _nvmkey"); asm volatile("mov #0xaa, w8"); asm volatile("mov w8, _nvmkey"); asm volatile("bset _rcfgcal, #13"); //set the rtcwren bit asm volatile("pop w8"); asm volatile("pop w7");
? 2010 microchip technology inc. ds39881d-page 179 pic24fj64 ga004 family 19. 1.3 r tcc control re giste rs regis t er 19-1: rcfgcal: rtcc ca l i bration and config uration re giste r (1) r/w - 0 u -0 r/w - 0 r -0 r-0 r /w -0 r/w - 0 r /w -0 rtc e n (2 ) ? r tcwren r t csync h a l f s e c (3 ) r t coe r tcptr1 rtcptr0 bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 cal 7 cal 6 cal 5 cal 4 cal 3 cal 2 cal 1 cal 0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 rt cen : r tc c en abl e b i t (2 ) 1 = r tc c m odu le is ena ble d 0 = r tc c m odu le is dis a b l ed bi t 14 un im pl e m e n te d : read as ? 0 ? bi t 13 rt cwren: r t c c v a l ue r egi ste r s w r i t e en abl e b i t 1 = r tc v a l h an d r t c v al l re gis t ers c an be w r i tte n to by the us er 0 = r tc v a l h an d r t c v al l re gis t ers a r e lo ck ed ou t from b e in g w r i tten to by the us er bi t 12 rt csync : r t c c v a l ue r e gis t e r s r e ad s y nc hro n iz at ion bi t 1 = r tc v a l h , r t c v all an d alc f g r pt reg i st ers c a n c han ge w h i l e re adi ng du e to a rol l ov er rip p le re su lti ng in a n inv a l i d da t a rea d . if the reg i s t er is re ad tw i c e an d res u lt s in th e sam e da t a , th e dat a c a n be assu me d to be va lid . 0 = r tc v a l h , r t c v al l or alc f g r pt re gis t e r s c a n be read wi th ou t co nc ern ov er a roll ov er ri ppl e bi t 1 1 hal fsec: ha l f -sec on d s t atu s bit (3 ) 1 = s e c o nd hal f pe rio d of a s e c o n d 0 = f irs t ha lf p e ri od of a se co nd bi t 10 rt co e: r tc c o u tp ut en abl e b i t 1 = r tc c ou tpu t en abl ed 0 = r tc c ou tpu t di sa ble d bi t 9- 8 rt cptr1 : rtcptr0 : r t c c v a l u e regi ste r wi ndo w poi n te r bi t s po in t s to the c o rre sp ond ing r t c c v a lu e regi ste r s w hen re adi ng th e r t c v al h a nd r t c v all re gis - te r s ; t h e r t c p tr < 1 : 0 > va l u e de cr e m e n t s on ev er y r e a d o r wr it e of r t c v a l h un t i l it r e ac he s ? 00 ?. rt c v a l < 1 5 : 8 > : 00 = m inutes 01 = w eekda y 10 =month 11 =reserved rtcval<7:0>: 00 = seconds 01 = hours 10 = da y 11 = year note 1 : th e r c f g c al regi st er is o n ly af fec t e d by a por . 2: a wri t e t o th e r t cen b i t i s o n l y a l l o we d wh e n r t cwren = 1 . 3: th is bi t is re ad-o n ly . it is cleared to ? 0 ? on a write to the lower half of the minsec register.
pic24fj64ga004 family ds39881d-page 180 ? 2010 microchip technology inc. bi t 7- 0 cal 7 : cal0 : r t c dri f t ca l i b r a t i o n b i t s 01 111111 = m a x i m u m p o s i ti ve adj us tme n t; add s 5 0 8 r t c c l o c k pu ls es eve r y one mi nu te .. . 01 111111 = m i nim um p osi tiv e a dj ust me nt; a dd s 4 r t c c l o c k pu ls es ev ery one m i nu te 00 000000 = n o ad j u s t me nt 11 111111 = m i nim um n ega tiv e a dju stm en t; s ub t rac t s 4 r t c cl oc k p uls es ev ery on e m i n ute .. . 10 000000 = m a x i m u m n ega tiv e a dju st me nt; s ub t rac t s 51 2 r t c cl ock p uls es ev ery on e m i n ute regis t er 19-1: rcfgcal: rtcc ca l i bration and config uration re giste r (1) note 1 : th e r c f g c al regi st er is o n ly af fec t e d by a por . 2: a wri t e to th e r t cen b i t i s o n l y a l l o we d wh e n r t cwren = 1 . 3: th is bi t is re ad-o n ly . it i s c l e a re d to ? 0 ? on a w r i t e to the lo w e r h a lf of t he m i n sec re gi ste r . regis t er 19-2: p adc f g 1 : p ad c o n f i g u ration control re g i ste r u-0 u -0 u-0 u - 0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bit 8 u-0 u -0 u-0 u - 0 u-0 u -0 r/w - 0 r/w-0 ? ? ? ? ? ? r t secsel (1 ) pmp ttl bi t 7 bit 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t i s s e t ? 0 ? = bit is cl eare d x = bit i s unk no w n bi t 15 - 2 u n im plem ent e d: r e ad as ? 0 ? bi t 1 rtsecsel: r t cc se c o n d s cl o c k ou tp u t se l e ct b i t (1 ) 1 = r t cc se co nd s c l o c k is se le ct e d f o r th e r t cc p i n 0 = r t c c al ar m pu l s e i s s e l e ct e d f o r t h e r t c c pi n bi t 0 pm pttl: pm p m o d u l e tt l in put buf f er se lec t b i t 1 = p m p mo dul e u s e s t t l i npu t b u f f e rs 0 = p m p mo dul e u s e s sc hm it t t r ig ger inp u t b u f f ers note 1 : t o e nab le the ac tua l r t c c output, the rtcoe (rcfgcal) bit needs to be set.
? 2010 microchip technology inc. ds39881d-page 181 pic24fj64 ga004 family r e g i ster 19 - 3 : alcfgrpt : alarm co nfiguration re giste r r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 al rm en chim e am ask3 am ask2 am ask1 am ask0 al rm pt r 1 alrmptr0 bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 arpt7 a rpt6 arpt 5 a rpt4 arpt3 a rpt2 arpt1 a rpt 0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 al rm en: al arm ena b le bi t 1 = a l a rm i s e n a b le d (c le ared a u tom a t i c a ll y af te r an al arm e v e n t w h ene ve r ar pt< 7 :0> = 0 0 h and chime = 0 ) 0 = a l a rm is di sa bl ed bi t 14 chime: ch im e en abl e b i t 1 = c h i m e i s e nab led ; ar pt< 7 :0 > bi t s are all o w e d to roll ov er f r om 00 h to ffh 0 = c h i m e i s d i s abl ed; ar pt<7 :0> bit s s t op on ce the y re ac h 00h bi t 13 - 1 0 amask3 :amask0 : al arm m a sk co n f ig urat ion bi t s 00 00 = e v e r y h a lf se con d 00 01 = e ve r y se co n d 00 10 = e ve r y 10 se co n d s 00 11 = e v e ry m i nu te 01 00 = e v e ry 1 0 m i nu tes 01 01 = e v e ry h our 01 10 = o nc e a day 01 11 = o nc e a w e e k 10 00 = o nc e a m ont h 10 01 = o nc e a y ear (ex c ep t w h e n c o n f ig ured for feb r uary 29 th, onc e eve r y 4 y ears ) 10 1x = r e s e r ve d ? do not us e 11 xx = r e s e r ve d ? do not us e bi t 9- 8 al rm ptr1 :alrm p t r 0 : al arm v a lu e r e g i s t er w i nd ow po int e r bi t s poin t s to the correspo nding alarm v a lue registers w hen r e a d ing alr m v a lh and alr m v a ll regis t ers; the alr m ptr < 1:0> valu e decreme nt s on every r e a d or w r ite of alr m v a lh until it reache s ? 00 ?. al r m v a l< 15:8 > : 00 = a lr mmi n 01 =alrmwd 10 = alrmmnth 11 = unimplemented alrmval<7:0>: 00 = a l r m sec 01 =a l r m h r 10 =a l r m d a y 11 = u ni mp le me nted bi t 7- 0 arpt 7 :arpt0 : alar m r e pea t c o u n te r v a lue bi t s 11 111111 = a larm wil l re pea t 2 55 m o re ti me s .. . 00 000000 = a larm wil l n o t re pe at t he c o u n ter d e c r em ent s on any al arm e v e n t. t he c oun ter i s pre v e n te d from rol lin g ov er fr om 0 0 h to f f h u n less chime = 1 .
pic24fj64ga004 family ds39881d-page 182 ? 2010 microchip technology inc. 19. 1.4 r t c v a l re gi st e r ma pp ing s r e g i ster 19 - 4 : ye ar: y e ar v a lue re g i ste r (1) u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x yr ten3 yr ten2 yr ten1 yr t e n0 yrone3 yrone2 yro n e1 yro n e0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 8 un im pl e m e n te d : r ead as ? 0 ? bi t 7- 4 yrt e n3 :yrten0 : bin a ry c ode d d e cim a l v a lu e o f y e a r ? s t e n s d i git; c ont ain s a v a lu e fro m 0 to 9 bi t 3- 0 yrone3: y r o ne0 : bin a ry c ode d d e c i m a l v a lu e of y ear ? s o n e s d i git ; c o n t ai ns a v a lu e f r om 0 to 9 note 1: a write to the year register is only allowed when rtcwren = 1 . r e g i ster 19 - 5 : mthdy : month and day v a lue regis t er (1 ) u-0 u-0 u-0 r-x r-x r-x r-x r-x ? ? ? mt ht en0 mt hon e3 m t hone 2 mth o ne 1 m tho ne0 bit 15 bi t 8 u-0 u -0 r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x ? ? da yten1 d a y ten0 da yone3 d a y o n e 2 da yone1 d a y one0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 uni m ple m ente d: re a d a s ? 0 ? bi t 12 mt ht e n 0 : binar y c oded d e cimal v a lue of mon t h? s t ens d i g i t; c ontains a value of ? 0 ? or ? 1 ? bi t 1 1- 8 mt ho n e 3 : m t ho n e 0 : b i nary c o d ed d e cimal v a lue of mont h? s ones d i git; c ont ain s a val ue f r om 0 to 9 bi t 7- 6 uni m ple m ente d: re a d a s ? 0 ? bi t 5- 4 da yt en 1:d a y t e n 0: b i nary c o d ed d e cimal v a lue of d a y? s t ens d i git ; c ont a i ns a v a lue f r om 0 to 3 bi t 3- 0 da yo n e 3 : da yo n e 0 : b i nary c o d ed d e cimal v a lue of d a y? s ones d i git; c ont ain s a val ue f r om 0 to 9 note 1 : a wri te to th is reg i s ter i s o n l y a llo wed w h en r t cwren = 1 .
? 2010 microchip technology inc. ds39881d-page 183 pic24fj64 ga004 family r e g i ster 19 - 6 : wk dyhr : w e e kday and hour s v a lue re giste r (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x ? ? ? ? ? w da y2 wda y 1 w da y0 bi t 15 bi t 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? h r t en1 h r t e n 0 hrone3 hrone2 h r o ne1 hro ne0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 w d a y 2:wd a y 0: b i n a r y c o d e d d e ci ma l v a l u e o f wee k d a y d i gi t ; c o n t ai ns a v a l u e f r om 0 t o 6 bi t 7- 6 un im pl e m e n te d : r ead as ? 0 ? bi t 5- 4 hrt en 1 : hrten0 : bina ry c o ded d e c i m a l v a lue of h our ? s t ens d i g i t; c o nt a i ns a va lue fro m 0 to 2 bi t 3- 0 hrone3 : hrone0 : bina ry c o ded d e c i m a l v a lue of h our ? s o nes d i g i t; c ont ain s a va lu e fro m 0 to 9 note 1 : a w r i t e t o th is reg i s t er i s o n l y a llo w ed w h en r t c w r e n = 1 . r e g i ster 19 - 7 : mins e c : minute s and s e conds v a lue re giste r u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? m inten2 minten1 m inten0 m i n o ne3 m ino n e2 minone1 m inone0 bi t 15 bi t 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? secte n 2 se c t en1 secten0 secone3 secone2 seco n e1 seco n e0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 un im pl e m e n te d : r ead as ? 0 ? bi t 14 - 1 2 m i n t en 2:min te n 0: b i nar y c o ded d e cimal v a lue o f minut e? s t ens d i gi t; c ontains a value fro m 0 t o 5 bi t 1 1- 8 m i n o ne 3 : mi no ne 0 : b i nar y c o ded d e cimal v a lue o f minu te? s ones d i git ; c ont a i ns a value f r om 0 to 9 bi t 7 uni m ple m ente d: re a d a s ? 0 ? bi t 6- 4 sec te n2 :se c t e n 0 : bina ry c oded d eci m a l v alue of second ? s t ens d i git; c ont ain s a val ue f r om 0 to 5 bi t 3- 0 sec o n e 3 :s ec o n e 0 : bina ry c oded d eci m a l v alue of second ? s o n es d i git; c ont ains a valu e fr om 0 to 9
pic24fj64ga004 family ds39881d-page 184 ? 2010 microchip technology inc. 19. 1.5 a l r mv al reg i s t er map p i ng s r e g i ster 19 - 8 : almthdy : alarm m o nth and day v a lue r e gis t e r (1) u-0 u -0 u-0 r /w -x r/w - x r /w -x r/w - x r /w -x ? ? ? mt ht en0 mt hon e3 m t hone 2 mth o ne 1 m tho ne0 bit 15 bi t 8 u-0 u -0 r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x ? ? da yten1 d a y ten0 da yone3 d a y o n e 2 da yone1 d a y one0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 uni m ple m ente d: re a d a s ? 0 ? bi t 12 mt ht e n 0 : binar y c oded d e cimal v a lue of mon t h? s t ens d i g i t; c ontains a value of ? 0 ? or ? 1 ? bi t 1 1- 8 mt ho n e 3 : m t ho n e 0 : b i nary c o d ed d e cimal v a lue of mont h? s ones d i git; c ont ain s a val ue f r om 0 to 9 bi t 7- 6 uni m ple m ente d: re a d a s ? 0 ? bi t 5- 4 da yt en 1:d a y t e n 0: b i nary c o d ed d e cimal v a lue of d a y? s t ens d i git ; c ont a i ns a v a lue f r om 0 to 3 bi t 3- 0 da yo n e 3 : da yo n e 0 : b i nary c o d ed d e cimal v a lue of d a y? s ones d i git; c ont ain s a val ue f r om 0 to 9 note 1 : a wri te to th is reg i s ter i s o n l y a llo wed w h en r t cwren = 1 . r e g i ster 19 - 9 : al w dhr: alarm w e ekd a y a nd hours v a lue regis t er (1 ) u-0 u -0 u-0 u-0 u-0 r/w-x r/w-x r/w-x ? ? ? ? ? w da y2 wda y 1 w da y0 bi t 15 bi t 8 u-0 u -0 r/w -x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? h r t en1 h r t e n 0 hrone3 hrone2 h r o ne1 hro ne0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 - 8 w d a y 2:wd a y 0: bina ry c o de d d e c i m a l v a lue of w e ek day d i g i t; c ont a i n s a va lue fro m 0 to 6 bi t 7- 6 uni m ple m ente d: re a d a s ? 0 ? bi t 5- 4 hrt en 1 : hrten0 : b i n a r y c o d e d d e ci ma l v a l u e o f h o u r ?s t e n s d i gi t ; c o n t ai ns a v a l u e f r om 0 t o 2 bi t 3- 0 hrone3 : hrone0 : bina ry c o ded d e c i m a l v a lue of h our ? s o nes d i g i t; c ont ain s a va lu e fro m 0 to 9 note 1 : a wri te to this register is only allowed when rtcwren = 1 .
? 2010 microchip technology inc. ds39881d-page 185 pic24fj64 ga004 family 19. 2 c al ibr a ti on th e re al -tim e c r y s t a l i npu t c an be cal i b r ated us in g th e p e rio d ic aut o-ad jus t fea t ure . w h e n prop erly ca lib rate d, th e r t c c can pro v i de a n err o r of les s t han 3 s e c ond s p er m ont h. th is is ac com pl i s hed by fin din g th e nu mb er of error c l o c k p u l s es an d sto r in g the v a l ue i n to th e l o w e r hal f of the r c f g c al re gis t er . th e 8 - bit si gne d v a l ue l oad ed int o th e l o w e r hal f of r c f g c a l is m u l t i- p lie d by fou r an d w i l l be eit her a d d ed o r su btra cte d fro m th e r t c c tim e r , on ce ev ery mi nut e. r e fer t o th e s t ep s b e lo w for r t c c c a li brat ion : 1 . u s ing a not her tim e r res o u r ce o n the de vi ce , th e u s er m u s t f i nd t he erro r o f t he 32 .76 8 k h z cr y s tal . 2 . o n c e the erro r is k now n , i t m u s t be c onv ert ed to th e n u m ber of e rror c l o c k pu ls es per mi nute . eq ua t i o n 1 9 - 1 : 3. a) if t he os cil l a t or i s fas t er then id eal (n ega t iv e re sul t form s t ep 2 ) , th e rc f g cal re gis t e r v a lu e ne ed s to be ne ga tiv e . thi s ca us es th e sp eci f ie d nu mb er of c l oc k pu ls es t o be su btra cte d from th e ti me r c oun ter o n c e e v ery m i n u te. b) if t he osc i l l at or i s s l o w er t h en id eal (po s i t iv e re sul t from s t ep 2 ) th e r c f g c a l r e gis t er v a lu e ne ed s to b e pos iti v e . th is c a us es th e sp eci f ie d nu mb er of c l oc k pu ls es t o be su btra cte d from th e ti me r c oun ter o n c e e v ery m i n u te. 4. d i v i d e th e nu mb er of e rror c l o c k s p e r m i nu te b y 4 to get th e c o rre ct c a l val ue an d l o ad th e rcfg c al r egi ste r with the c o rrec t v a l ue. (ea c h 1 - bit i n c r em ent i n c a l a dds or su btra ct s 4 pul se s). w r i t es t o t h e l o w e r ha l f o f t h e r c f gc a l r e gi s t e r s hou ld on ly oc c u r w h en the ti me r i s turn ed of f, or i m m edi ate l y af ter the ris i n g e d ge o f th e s e c o n d s pu ls e. r e g i ster 19 - 1 0 : almin s e c: alarm m i nute s a nd s e conds v alue re g i ste r u-0 r /w -x r/w - x r /w -x r/w - x r /w -x r/w - x r /w -x ? m inten2 minten1 m inten0 m i n o ne3 m ino n e2 minone1 m inone0 bi t 15 bi t 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? secte n 2 se c t en1 secten0 secone3 secone2 seco n e1 seco n e0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 uni m ple m ente d: re a d a s ? 0 ? bi t 14 - 1 2 m i n t en 2:min te n 0: b i nar y c o ded d e cimal v a lue o f minut e? s t ens d i gi t; c ontains a value fro m 0 t o 5 bi t 1 1- 8 m i n o ne 3 : mi no ne 0 : b i nar y c o ded d e cimal v a lue o f minu te? s ones d i git ; c ont a i ns a value f r om 0 to 9 bi t 7 uni m ple m ente d: re a d a s ? 0 ? bi t 6- 4 sec te n2 :se c t e n 0 : bina ry c oded d eci m a l v alue of second ? s t ens d i git; c ont ain s a val ue f r om 0 to 5 bi t 3- 0 sec o n e 3 :s ec o n e 0 : bina ry c oded d eci m a l v alue of second ? s o n es d i git; c ont ains a valu e fr om 0 to 9 (id eal f r e q u e ncy ? ? measur ed fr e q ue ncy) * 60 = c l oc ks pe r m i nu te ? i dea l f r equ enc y = 32 ,76 8 h z note : it is up to th e us er to in cl ude i n the e rror v a lu e the ini t ia l error o f the c r ys t a l, dri f t du e to te mp eratu r e an d drif t d u e to c r y s t a l ag in g.
pic24fj64ga004 family ds39881d-page 186 ? 2010 microchip technology inc. 19. 3 a l a rm ? c on f i gu r ab l e f r o m ha l f s ec o nd to o ne ye ar ? e n abl ed us ing the alr m en bi t (al c fg r p t<15 >, r e gis t er 19-3 ) ? o ne -tim e a l a r m a nd repe at a l a r m o pti ons a v ai la ble 19. 3.1 c o n f i g uring t h e a l ar m th e al arm fe atu r e is e nab led u s i ng th e alr m e n bi t. th is b i t is cl ea red w hen a n a l arm is is su ed. w r ite s to al r m v a l s h o u ld on ly t a k e p l ac e w h en alr m en = 0 . as sho w n in fi gur e 1 9 - 2, th e int e rva l se le cti on of th e a l arm is c onf igu r ed thro ugh the amask bit s ( a lc f g r p t < 1 3 : 1 0> ) . t h es e bi ts de t e r m in e w h ic h a n d h o w m a n y dig i t s o f th e ala r m mu st m a tc h t he cl oc k v a l ue f o r th e a l arm to oc cu r . th e a l arm c an als o b e c onf igu r ed t o re pea t ba se d on a p r ec onfi gu r ed in terv al. th e a m o un t o f ti me s thi s oc cu rs o nce t he ala r m is e nab le d i s st ored i n t he ar pt b i t s , arpt7 :ar pt0 (alc f g r p t< 7:0 > ). w hen th e v a l ue of th e ar pt bi t s equ al s 0 0h and th e c h i m e b i t (al c fg r p t<14 >) i s c l e a re d, th e re pe at fu nc tio n i s d i s abl ed and onl y a s i ng le ala r m w ill oc cu r . th e a l ar m c an b e repe ate d up to 2 55 ti me s by loa din g arpt7 : arpt0 with ffh . a fte r ea ch al a r m is is su ed , t h e v a l u e o f t h e a r p t b i t s i s d ec r em ente d b y o ne. o nce th e v alu e h as reac he d 00 h, the a l arm w i ll be i s s ued o ne las t time , af t e r w h ic h th e al r m en b i t w ill be cl ea red auto m a t ic al ly an d th e al arm wil l tu rn o f f. indefin ite repetiti on of the alarm can occ u r if the c h ime bit = 1 . ins t ead of the a l arm being disabl ed w hen the va lue of the ar pt bi t s r e a c hes 00h, it rolls ov er to ffh and c ontinues c ounting in definitely w h ile c h i me is se t. 19. 3.2 a l a rm inte rrup t at ev ery ala r m ev en t, an i n terr upt is gen era t ed. i n add i - ti on, an a l arm pu lse out put i s p r ov ide d th at op era t es at ha lf the fr equ enc y of th e a l ar m. thi s ou tput i s c o m p le tel y s y n c hr ono us t o the r t c c cl oc k a n d c an b e us ed as a trig ger c l o c k to oth e r p e rip her als . figure 19-2: alarm mas k s e ttings note: changing any of the registers, other the n th e r c f g c al a nd alc f g r pt r e gis t er s an d the c h i me bi t w h i l e the al arm i s en ab led (alr m e n = 1 ), c an res u lt in a f a l s e al a r m ev en t l e ad i n g t o a f a l s e al a r m in terr upt. t o avo i d a fa lse a l ar m ev ent, th e ti me r a nd al arm v alu es s h o uld o nly b e c han ged w h ile th e a la r m is di sa ble d (al r m e n = 0 ). i t is re co mm en ded tha t th e al c f gr pt re gis t er an d c h i me bi t b e c han ged wh e n r t c syn c = 0 . no te 1: ann ual ly , except w hen c onf igured for february 29. s ss mss mm s s hh m m ss dhhmmss dd hh mm s s mm d d h h m m s s da y o f th e we e k m o nt h d a y h our s m inu t e s se c o nds al arm mask set t i n g (am a s k 3: amas k0) 0000 ? ever y ha l f s e cond 0001 ? ever y s e cond 0010 ? ever y 10 sec onds 0011 ? ever y m i nut e 0100 ? ever y 10 m i nut es 0101 ? ever y ho ur 0110 ? ever y da y 0111 ? ever y w eek 1000 ? ever y m ont h 1001 ? ever y y ear (1 )
? 2010 microchip technology inc. ds39881d-page 187 pic24fj64 ga004 family 20 .0 pr o g ram mable cy clic re dundan cy ch eck ( crc) gene rator th e p r o g ra mm a b l e crc g e n e ra to r o f fe rs th e fo l l o w i n g fe atu r es : ? u se r-p ro g r a m ma b l e p o l y n o m i a l crc e q u a t i o n ? in terru pt o u tp ut ? d at a fi fo th e m od ule im ple m e nt s a s of t w are c on f igu r ab le c r c g ene rato r . the te rms o f the po ly nom ia l and i t s l eng th ca n b e p r o g r a m me d u s i n g th e crcxor (x< 1 5 : 1 > ) b i t s a n d t h e c rccon (pl e n 3 :pl e n0 ) b i t s , re sp e c ti v e l y . c o n s i der the c r c equ ati on: x 16 + x 12 + x 5 + 1 t o p ro g ra m th i s p o l y n o m i a l i n t o th e crc g e n e ra to r , th e crc r e g i s t e r b i t s sh o u l d b e s e t a s sh o wn i n t abl e 2 0-1. t able 2 0 -1: e x a m p le crc s e tup not e tha t for th e va lue of x<1 5 :1 >, the 1 2 th bit a nd th e 5t h bit a r e se t to ? 1 ?, a s r eq u i r e d by t h e eq ua t i on . t he 0 bi t req u ire d by t he eq uat ion i s a l w a y s xo r e d. f o r a 16 -bi t p o ly no mi al, the 16 th bi t is a l s o a l w a y s as su me d to be xor e d; t here f ore , the x<1 5 :1 > bi t s do n o t h a v e th e 0 bit or t he 1 6 th bi t. th e to p o l o g y o f a st a n d a r d crc g e n e r a t o r i s sh o w n i n fi gur e 2 0 - 2. figure 20-1: crc s h if ter det a ils note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e s our c e . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ?s ec tion 3 0 . pr og r a mm able c ycl ic red unda ncy chec k (crc)? (ds39 714 ). bit na me bit value plen3:plen0 1111 x<15:1 > 00010000001 0000 in ou t bit 0 0 1 p_clk x1 in out bit 1 0 1 p_clk x2 in out bit 2 0 1 p_clk x3 in ou t bi t 1 5 0 1 p_clk x15 xor d ou t 01 2 1 5 plen < 3 :0> hold hold hold ho l d crc read bus crc w r it e b u s crc s h if t reg i ster
pic24fj64ga004 family ds39881d-page 188 ? 2010 microchip technology inc. figure 20-2: crc ge ner a to r reconfigur ed for x 16 + x 12 + x 5 + 1 20. 1 u ser i n ter f ac e 20. 1.1 d at a int e rf ace t o sta r t se r i al sh ift i ng , a ? 1 ? m u s t be w r itt en to th e crcgo b i t . th e m odu le i n c o rpo r ate s a f i fo tha t is 8 de ep w h e n pl en (ple n < 3:0 > ) > 7, a n d 16 de ep, ot herw i se . th e d a t a fo r wh i c h th e crc i s t o b e ca l c u l a t e d mu st fi r s t b e w r i tten int o th e fif o . the sm al les t da t a e l e m en t th at c an b e w r itten in to the fifo is o ne b y te . for ex am pl e, i f plen = 5 , the n the s i z e of th e da t a is plen + 1 = 6 . th e d a t a mu st be w r itte n a s fo ll ow s: da t a [5 :0] = c r c_ inp u t[5 :0] da t a [7 :6] = ?bxx on ce d a t a i s wri tte n i n to th e crcwda t m s b (a s de f i ne d b y p l e n ) , t h e va l u e of t h e v w or d b i t s (crccon<1 2 :8 >) i n cre m e n t s b y o n e . th e se ri a l sh i f te r s t a r t s sh i f ti n g d a t a i n to th e crc e n g i n e wh e n crcgo = 1 a nd vw o r d > 0. whe n th e m s b i s s h i f ted out, vwo r d d e c r em ent s b y on e. th e s e ria l s h i f ter c ont inu e s s h i f ti ng un til the vw or d re ach e s 0. th ere f ore , for a gi ve n va lu e of ple n , i t w ill t a k e ( p le n + 1) * v w o rd nu mb e r o f cl o ck cy cl e s t o c o m p le te the c r c cal c u l at ion s . w h e n vword re a c h e s 8 (o r 1 6 ), th e crcful b i t wi l l b e se t. wh e n vword re a c h e s 0 , th e crcm pt b i t wi l l b e s e t. t o c o n t i n u a l l y f e e d d a t a i n to th e crc e n g i n e , th e re c - o m m e n ded m ode of op erat ion is t o i n it ial l y ?pri me ? th e fi fo w i th a su f f i c i ent num be r of w o rd s s o n o in terru pt i s ge nera t ed b e fo re the nex t w o rd c a n b e w r itte n. o n c e th a t i s d o n e , s t a r t th e crc b y se t t i n g th e cr cgo b i t to ? 1 ?. fr om t hat poi nt o n w a rd , the vwo r d bit s s hou ld b e p o ll ed. if th ey rea d l e ss th an 8 o r 16, an othe r w o rd ca n b e writ ten int o th e fi fo . t o em pty w o rd s al ready w r i tten i n to a fifo , th e crcgo b i t mu s t b e s e t to ? 1 ? a n d th e crc sh i f t e r a l l o we d t o ru n u n ti l th e crcm pt b i t i s se t. al s o , to g e t th e co rre c t crc re a d i n g , i t wi l l b e n e c e s s a r y to wa i t f o r th e crcmpt b i t t o g o h i g h b e fo re re adi ng the c r c w d a t regi ste r . if a word i s writte n when th e cr cf ul b i t is s e t, th e vwo r d poin ter w i l l r o ll o v er to 0. th e hard w are w i l l th en b eha ve a s if t he fif o i s em pty . h o w e v e r , th e co n- di tio n to ge nera t e an i n te rrupt w i l l no t b e me t; the r efor e, no inte rrup t w i ll b e gen era t ed (se e secti o n 2 0.1 . 2 ? i nte r rup t o p era t ion? ). at le as t o ne in st ruct ion c y c le m u s t p a s s a f ter a w r it e to crcwda t b e fo re a re a d o f th e vword b i t s i s d o n e . 20. 1.2 i nte rrup t o p e r ation w h e n t h e v w or d 4 :v w o r d 0 bi ts ma ke a t r an s i t i on fro m a v a lu e of ? 1 ? to ? 0 ?, an i n te rrupt wil l be g e ne rate d. 20. 2 o pera ti on i n power save modes 20. 2.1 s l e e p mo de if sl eep mod e is ent ered w h ile the m o d u le i s o p era t in g, th e m odu le w ill be su sp end ed i n i t s cur r ent st a t e u n ti l c l oc k exec utio n re su me s. 20. 2.2 i dle m o d e t o c o n t in ue ful l m o d u le op era t ion i n id le m o de , th e c s id l bi t m u st be cl ea red prio r to en try into th e m o d e . if csidl = 1 , th e m odu le w i ll beh a v e th e s a m e way a s i t do es i n sl eep m o d e ; p e n d in g i n te rrupt ev en t s w i l l b e p a ss ed on , ev en th oug h th e m o d u le c l oc ks a r e n o t av ai la ble . d q bit 0 p_c l k dq bi t 4 p _ clk dq bi t 5 p _ clk dq bit 12 p_clk xo r sdox crc re a d bu s crc wr ite bu s dq bit 15 p_cl k
? 2010 microchip technology inc. ds39881d-page 189 pic24fj64 ga004 family 20. 3 r egi s te rs th ere are fo ur reg i s t ers us ed t o co ntro l pro g ram m abl e crc o p e r a t i o n : ? crccon ? crcxor ? crcda t ? crcwda t r e g i ster 20 - 1 : crccon: crc control regis t er u-0 u-0 r/w-0 r-0 r-0 r-0 r-0 r-0 ? ? c sidl vw o rd4 v w or d3 vword2 vword1 vword0 bi t 15 bi t 8 r-0 r -1 u-0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 crcful crcmpt ? crcgo p l e n3 pl en2 p l e n1 pl en0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 4 uni m ple m ente d: re a d a s ? 0 ? bi t 13 csi d l : crc s t o p i n id l e mo d e b i t 1 = d i s c on t inu e m od ule op erat ion w hen de vi ce ent ers idl e m od e 0 = con ti nue mo du le o pe r atio n i n id le mo de bi t 12 - 8 vw o rd4 :vword0 : po int e r v a lu e b i t s i ndi ca tes th e n u m ber of val i d w o rd s i n t he fifo . h a s a m a x i m u m v a l ue of 8 w h e n pl en 3:pl en 0 > 7, or 1 6 wh en p l en 3: p l e n 0 ? ? 7. bi t 7 crcful : fif o full bi t 1 = f ifo is fu ll 0 = f ifo is no t fu ll bi t 6 crcmpt : fifo em pty bi t 1 = f ifo is em pt y 0 = f ifo is no t e m pt y bi t 5 un im pl e m e n te d : read as ? 0 ? bi t 4 crcgo: s t art c rc b i t 1 = s t a rt crc se ri a l sh i f te r 0 = crc se ri a l s h i f te r tu rn e d o f f bi t 3- 0 pl en3:plen0 : pol y n o m i al le ngth bi t s d e not es the len g th of the pol yn om ial to be gen erat ed m i n u s 1.
pic24fj64ga004 family ds39881d-page 190 ? 2010 microchip technology inc. regis t er 20-2: crcx or: crc x o r p o ly nomial re giste r r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 x15 x 1 4 x1 3 x 12 x1 1 x 10 x9 x8 bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 u -0 x7 x6 x5 x4 x3 x2 x1 ? bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 x1 5:x1 : xo r of p o ly no mia l t e rm x n ena b l e bi t s bit 0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39881d-page 191 pic24fj64 ga004 family 2 1 .0 1 0 - b it high- s pe ed a/d conv erte r th e 1 0 -b it a/ d c onv ert e r h a s the fol l ow i ng ke y fe atu r es : ? s uc ce ss iv e a p p r ox im at i o n ( s a r ) co nv er s i o n ? c on ve rsi on sp eed s o f up to 500 ks p s ? u p t o 13 an a l o g i n pu t pi ns ? e x t ern a l vo lt a ge re fere nc e i npu t pi ns ? a u t om ati c c h ann el sca n m ode ? s e l ec t ab l e co nv ers i on trig ger so urc e ? 1 6-w o rd co nv ers i on res u l t bu f f e r ? s e l ec t a b l e buf f er f ill m ode s ? f o u r re su lt a l i gnm en t op tio n s ? o pe rati on duri ng c p u slee p a nd idle m ode s d e pen din g on t he p a rti c u l ar d e vi ce pin out , the 1 0 -b it a/d c o n v e r ter ca n hav e up to t h ree a nal og in pu t p i ns , d e si gn ated an 0 thro ugh an 12 . in add iti on, the r e a r e tw o a nal og in put pi ns fo r e x te rna l v o l t ag e refer enc e c onn ec tio n s . the s e vo lt a ge refe renc e i npu t s ma y b e s har ed w i th o t he r a nal og in put p i ns . the a c tu al nu mb er o f an alo g i npu t pi ns an d ex ter nal vo lt a ge refer enc e i npu t c onfi g u r ati on w i ll dep end on the sp ec ifi c d e v i c e . a b l oc k di a g r a m of t h e a / d c o n v er t e r i s sh ow n in fi gur e 2 1 - 1. t o pe r f or m an a / d c o nv er s i o n : 1. c o n f ig ure the a/d m odu le: a) se lec t p o rt pi ns as a nal og in put s (ad 1 pc f g < 15: 0>). b) se lec t v o lt age ref e ren c e so urc e to m a tc h ex pe cte d rang e o n a nal og in put s (ad 1 c o n 2 < 15: 13> ). c ) se lec t t he ana lo g c o n v e r si on cl oc k to m a tc h d e si red dat a rat e w i th pro c e s s o r cl o ck (ad1 con3 <7 :0 >). d) sel ect th e appr opria te sample/ c onver sion sequen c e ( a d 1c o n 1<7: 5> and ad 1c o n 3<12 :8>) . e) se lec t how co nv ers i on re su lt s a r e pr ese n te d i n th e b u f f e r (ad 1 c o n 1 <9:8 >). f) se lec t i n terr upt rate (ad1co n2<5 :2>) . g ) t u r n o n a/d mo d u l e (ad1 con1 <1 5 > ). 2. c o n f ig ure a/d in terru pt (i f re qui red) : a ) c l ea r th e a d 1i f bi t . b) se lec t a/d in te rrup t pri o ri ty . note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 17. 10-bit a/d converter? (ds39705).
pic24fj64ga004 family ds39881d-page 192 ? 2010 microchip technology inc. f i g ure 21- 1: 10- bit h i g h - spe ed a/d conv erte r block diagram comparator 10-bit sar conversion logic v ref + dac an 1 2 an8 (1) an9 an10 an11 an4 an5 an6 (1) an7 (1) an0 an1 an2 an3 v ref - sample control s/ h av ss av dd adc1bu f 0 : adc1bu f f ad1con1 ad1con2 ad1con3 ad1chs ad1pcfg ad1cssl control logic data formatting input mux control conversion control pin co nf ig. cont rol internal data bus 16 v r + v r - mux a mux b v in h v in l v in h v inh v in l v in l v r + v r - v r select no te 1: a nal o g cha nnel s a n 6 t h rough an8 ar e available on 44-pin devices only . 2: band gap voltage reference (v bg ) is internally connected to analog c hannel an15, which does not appear on any pin. v bg (2)
? 2010 microchip technology inc. ds39881d-page 193 pic24fj64 ga004 family regis t er 21-1: ad1c o n1 : a/d control re giste r 1 r/w - 0 u -0 r / c-0 u -0 u-0 u -0 r/w -0 r /w -0 ad on ?adsidl ? ? ?f o r m 1 f o r m 0 bi t 15 bi t 8 r/w -0 r/w -0 r/w - 0 u-0 u -0 r/w - 0 r /w -0 , hcs r/w -0, hc s ssrc2 ssrc1 ssrc0 ? ? a sam sam p d one bi t 7 bi t 0 le gen d : c = cl e a ra b l e b i t hcs = h a rd wa re cl e a ra b l e / se tt a b l e b i t r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 adon: a/d o p erat ing mo de bit 1 = a / d c onv ert e r m odu le is op erati n g 0 = a / d c onv ert e r is o f f bi t 14 un im pl e m e n te d : r ead as ? 0 ? bi t 13 adsidl : s t op in idle m ode bi t 1 = d i s c on t inu e m od ule op erat ion w hen de vi ce ent ers idl e m od e 0 = continue mo du le o pe r atio n i n id le mo de bi t 12 - 1 0 un im pl e m e n te d : read as ? 0 ? bi t 9- 8 fo r m 1 : fo r m 0 : da t a o u tput form at bi t s 11 = si gne d fra c t i on al ( sddd dddd dd00 0 000 ) 10 = fra c t i on al ( dddd dddd dd00 0000 ) 01 = si gne d i n teg e r ( s sss sssd dddd ddd d ) 00 = in teg e r ( 0000 00dd dddd dddd ) bi t 7- 5 ss r c 2 : ssrc0: co nve r si on t r ig ger s ourc e se lec t b i t s 11 1 = in tern al co unte r en ds sa mp lin g a nd st a r t s co nv ersi on (au t o-c onv ert ) 11 0 = re serv ed 10 x = re serv ed 01 1 = re serv ed 01 0 = t i me r3 c o m p ar e en ds sa mp lin g a nd st a r t s co nv ers i on 00 1 = ac tiv e t r ans it ion on in t0 pin en ds sa mpl i n g an d s t ar t s con v e r si on 00 0 = c l eari ng samp b i t end s s a m p l i ng an d s t art s c o n v ers i o n bi t 4- 3 un im pl e m e n te d : read as ? 0 ? bi t 2 asam: a/d s a mp le auto -s t a rt b i t 1 = s a m p l i ng b egi ns im m edi ate l y af te r la st co nve r si on co mp lete s. samp bit is au to-s et. 0 = s a m p l i ng b egi ns wh e n sam p bi t is s e t bi t 1 sam p : a/ d sam p le ena b le bi t 1 = a/d s a m p l e /h old am pl ifie r is s a m p li ng inp u t 0 = a/d s a m p l e /h old am pl ifier is ho ld ing bi t 0 done: a/ d c onv ers i on s t atu s bit 1 = a/d c o n v e r si on i s don e 0 = a/d c o n v e r si on i s n o t don e
pic24fj64ga004 family ds39881d-page 194 ? 2010 microchip technology inc. regis t er 21-2: ad1c o n2 : a/d control re giste r 2 r/w - 0 r /w -0 r/w - 0 r /w -0 u-0 r /w -0 u-0 u -0 vcfg2 v cf g 1 vcfg0 ? ? c scna ? ? bi t 15 bi t 8 r-0 u-0 r /w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 bufs ? s m p i3 sm pi2 s m p i1 sm pi 0 b ufm a l t s bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 1 3 vcf g 2 : vcfg0: v o lt a ge r e fer enc e c o nfi gura t io n bi t s bi t 12 - 1 1 un im pl e m e n te d : r ead as ? 0 ? bi t 10 cscna: sc an inp u t s e le cti ons fo r ch0+ s/h inp u t for m u x a in pu t mu lti p le xe r set t ing bi t 1 = s c a n in put s 0 = d o no t s c an in put s bi t 9- 8 un im pl e m e n te d : r ead as ? 0 ? bi t 7 buf s: buf f er f ill s t atu s bit ( v a lid on ly w h en bu fm = 1 ) 1 = a / d is cu rren t ly fil l i ng b u f f er 0 8 -0 f , u s e r s hou ld acc e s s dat a in 00 -07 0 = a / d is cu rren t ly fil l i ng b u f f er 0 0 -0 7, u s e r sh oul d a c c e s s d a t a in 08- 0f bi t 6 un im pl e m e n te d : r ead as ? 0 ? bi t 5- 2 sm pi3 : sm pi 0: sa mp le/c o n v e rt se qu enc es per inte rrupt sel e ct ion bi t s 11 11 = in terru pt s at the co mp let i on of con v e r si on for e a c h 1 6 th sa mpl e /c on ve rt s equ enc e 11 10 = in terru pt s at the co mp let i on of con v e r si on for e a c h 1 5 th sa mpl e /c on ve rt s equ enc e .. ... 00 01 = in terru pt s at the co mp let i on of con v e r si on for e a c h 2 nd s a m p l e /c onv ert se que n c e 00 00 = in terru pt s at the co mp let i on of con v e r si on for e a c h s a m p le /c onv ert seq u e n ce bi t 1 buf m : bu f f e r m ode sel e c t bi t 1 = buf f er co nfi gure d a s tw o 8-w o rd b u f f e rs (ad c 1bu fn < 15 :8> and ad c 1 bu fn <7:0 >) 0 = buf f er co nfi gure d a s o ne 1 6 -w o r d b u f f e r (ad c 1b u f n<1 5 :0 >) bi t 0 al ts: alte rnat e in put sam p le m ode sel e c t bi t 1 = u s e s m u x a in put mu lti p le xe r se tti ngs for firs t s a m p le , th en alt e rna t es be tw een m u x b an d m u x a i npu t m u l t ipl e x e r s e tt ing s f o r a ll s u b s e que nt s a m p l e s 0 = a lw a y s us es mu x a in p u t mu lt i p le xe r se t t i n gs vc fg 2: v c f g 0 v r +v r - 000 av dd *a v ss * 001 ex tern al v re f + p i n a v ss * 010 av dd *e x t e r n a l v re f - pi n 011 ex tern al v re f + pi n e x t ern a l v re f - pi n 1xx av dd *a v ss * *a v dd an d a v ss i npu t s are tied to v dd an d v ss on 28 -pin de vi ces .
? 2010 microchip technology inc. ds39881d-page 195 pic24fj64 ga004 family regis t er 21-3: ad1c o n3 : a/d control re giste r 3 r/w - 0 u -0 u-0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 adrc ? ? sam c4 sam c3 sam c2 sam c1 sam c0 bi t 15 bi t 8 r/w -0 r/w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 adcs7 a dcs6 a dc s 5 adcs4 a dcs3 a dcs2 a dcs1 a dc s 0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 adrc: a/ d c onv ers i o n cl o c k sou r ce bi t 1 = a /d i n te r n al rc cl oc k 0 = c lo ck de r i ve d f r om sy st em cl oc k bi t 14 - 1 3 un im pl e m e n te d : read as ? 0 ? bi t 12 - 8 sam c 4:sam c 0: a u t o - s am pl e t i me bi ts 11 111 = 3 1 t ad 00 001 = 1 t ad 00 000 = 0 t ad (n ot reco mm en ded ) bi t 7- 0 adcs7 : ad cs0 : a/d co nv ers i on cl oc k sel e ct bit s 11 111111 = re ser v ed 01 000000 00 111111 = 64 ? t cy 00 000001 = 2 ? t cy 00 000000 = t cy
pic24fj64ga004 family ds39881d-page 196 ? 2010 microchip technology inc. regis t er 21-4: ad1c h s: a/d inp u t se lect r e gis t er r/w - 0 u -0 u-0 u -0 r / w - 0 r /w -0 r/w - 0 r /w -0 ch0 nb ? ? ? ch0 sb3 (1 , 2 ) ch 0 sb2 (1 , 2 ) ch0 sb1 (1 , 2 ) ch0 sb0 (1 , 2 ) bi t 15 bi t 8 r/w -0 u-0 u -0 u-0 r / w -0 r/w -0 r /w -0 r/w -0 ch0na ? ? ? ch0 sa3 (1 , 2 ) ch 0 sa2 (1 , 2 ) ch0 sa1 (1 , 2 ) ch0 sa0 (1 , 2 ) bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 ch0 nb : c han nel 0 n e ga tiv e in put sel e ct for mu x b mul t ip le xer setti ng bit 1 = c h a nne l 0 ne gat ive in put is an 1 0 = c ha nne l 0 ne gat ive in put is v r - bi t 14 - 1 2 un im pl e m e n te d : r ead as ? 0 ? bi t 1 1- 8 ch0 sb3 : ch0 sb0 : chan nel 0 pos i tiv e inpu t se lec t fo r m u x b m u lti p l e xe r set t in g bi t s (1 , 2 ) 11 11 = c h ann el 0 po si tiv e i npu t i s an 1 5 (b and gap v o lt age refe ren c e) 1100 = c h ann el 0 po si tiv e i npu t i s an 12 10 11 = c h ann el 0 po si tiv e i npu t i s an 1 1 00 01 = c h ann el 0 po si tiv e i npu t i s an 1 00 00 = c h ann el 0 po si tiv e i npu t i s an 0 bi t 7 ch0 na : chan nel 0 n e ga tiv e in put sel e ct for mu x a mul t ip le xer setti ng bit 1 = c h a nne l 0 ne gat ive in put is an 1 0 = c ha nne l 0 ne gat ive in put is v r - bi t 6- 4 un im pl e m e n te d : read as ? 0 ? bi t 3- 0 ch0 sa3 : ch0 sa0 : chan nel 0 pos i tiv e inpu t se lec t fo r m u x a m u lti p l e xe r set t in g bi t s (1 , 2 ) 11 11 = c h ann el 0 po si tiv e i npu t i s an 1 5 (b and gap v o lt age refe ren c e) 1100 = c h ann el 0 po si tiv e i npu t i s an 12 1011 = c h ann el 0 po si tiv e i npu t i s an 1 1 00 01 = c h ann el 0 po si tiv e i npu t i s an 1 00 00 = c h ann el 0 po si tiv e i npu t i s an 0 note 1 : c o mb in at i o ns ? 1101 ? and ? 111 0 ? a r e u ni m p l em en t ed ; do no t us e. 2: an alo g c han ne ls an 6, an 7 an d an 8 are una va ila ble on 28- pin de vic e s ; d o n o t u s e.
? 2010 microchip technology inc. ds39881d-page 197 pic24fj64 ga004 family regis t er 21-5: ad1p c fg: a/d p o rt configuration re giste r r/w -0 u-0 u -0 r/w -0 r / w -0 r/w -0 r /w -0 r/w -0 pcfg15 ? ? p cfg1 2 p cfg1 1 p cfg1 0 p cf g 9 pcfg8 (1 ) bit 15 bi t 8 r/w -0 r/w - 0 r /w -0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 pcfg7 (1 ) pcfg6 (1 ) pcfg5 p cfg4 pcfg3 p cfg2 pcf g 1 p cfg0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 pcf g 1 5 : an alo g i npu t pin co n f igu r ati on c ontr o l b i t s 1 = b a n d gap v o lt a g e refe renc e is dis a b l ed 0 = b a n d gap v o lt a g e refe renc e ena ble d bi t 14 - 1 3 un im pl e m e n te d : read as ? 0 ? bi t 12 - 0 pcf g 1 2 :pcfg0: anal og inp u t pi n c o nfig ura t ion co n t rol bit s (1 ) 1 = p i n f o r c o rre spo ndi ng ana lo g c h an nel is c onf igu r ed in d i git a l mo de; i/o po rt rea d e nab le d 0 = p i n c o n f ig ured in ana l og mo de; i/o po rt re ad disa b l ed , a/d s a m p l e s pin vo lt a g e note 1 : an alo g c han ne ls an 6, an 7 an d an 8 are una va ila ble on 28- pin de vice s ; l eave t hese c o rre sp ond in g bi t s se t . regis t er 21-6: ad1c s s l : a/d inp u t s can s e le ct re g i ste r r/w -0 u-0 u -0 r/w -0 r / w -0 r/w -0 r /w -0 r/w -0 cssl1 5 ? ? c ssl 12 cssl1 1 cssl1 0 cssl 9 c ssl8 (1 ) bi t 15 bi t 8 r/w -0 r/w -0 r/w-0 r/w - 0 r / w -0 r/w - 0 r /w -0 r/w - 0 cs s l 7 (1 ) cssl6 (1 ) cssl 5 c s s l4 cssl3 c ssl2 c ssl 1 c ssl 0 bi t 7 bi t 0 le gen d : r = read abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 cssl 15: band g ap r e fere nc e in put pin sca n se lec t io n b i t s 1 = ban d g ap v o l t ag e re fere nce c han nel se le cte d fo r in put sc an 0 = ban d g ap v o l t ag e re fere nce c han nel om itt ed f r om in put sc an bi t 14 - 1 3 un im pl e m e n te d : read as ? 0 ? bi t 12 - 0 cssl 12:cssl 0: a/ d inpu t pi n sc an sele ct ion bit s (1 ) 1 = co rre sp ond ing an alo g c han ne l s e le cte d f o r i npu t sc an 0 = ana l og ch an nel om itt ed f r om in put sc an note 1 : an alo g c han ne ls an 6, an 7 an d an 8 are una va ila ble on 28- pin de vice s ; l eave t hese c o rre sp ond in g bi t s c l ea red.
pic24fj64ga004 family ds39881d-page 198 ? 2010 microchip technology inc. equa tion 2 1 -1: a /d c o nv e r sion clo c k pe riod (1) figure 21-2: 10-bit a / d conv erte r ana l og inp u t m o d e l note 1: based on t cy = 2 * t osc ; doze mode and pll are disabled. t ad = t cy ? (adcs +1 ) adcs = t ad t cy ? 1 c pin va rs anx v t = 0 . 6 v v t = 0 . 6 v i leakage r ic ? 25 0 ? s a m p lin g sw it ch r ss c hol d = d a c capaci t ance v ss v dd = 4.4 pf (t ypi c a l ) ? 50 0 n a le ge nd : c pin v t i l e akage r ic r ss c ho l d = in pu t c apaci t anc e = t h r e sho l d v o l t age = le a k ag e c u rr e n t at t h e p i n d u e t o = in ter c on nect r e si stan ce = sa m p lin g switch re sista n ce = sample/hold capacitance (from dac) vari o u s j u nct i o n s no te: c pin value depends on device package and is not tested. effect of c pin negligible if rs ? 5 k ? . r ss ? 5 k ?? ( t ypica l ) 6-1 1 pf (t y p i c al )
? 2010 microchip technology inc. ds39881d-page 199 pic24fj64 ga004 family figure 21-3: a/d t rans fer fun c tion 10 0000 0001 (5 13) 10 0000 0010 (5 14) 10 0000 0011 (5 15) 01 1111 1101 (5 09) 01 1111 1110 (5 10) 01 1 111 1111 (5 1 1 ) 11 1111 11 10 (10 22) 11 1111 11 11 (10 23) 00 0000 0000 (0) 00 0000 0001 (1) o u tp ut c o de 10 0000 0000 (5 12) (v inh ? v in l ) v r - v r + ? v r - 1024 512*(v r + ? v r -) 1024 v r + v r - + v r - + 1023*(v r + ? v r -) 1024 v r - + 0 ( b in ar y ( d ec im a l )) v o lt a g e le vel
pic24fj64ga004 family ds39881d-page 200 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 201 pic24fj64 ga004 family 22 .0 comp arator modul e figure 22-1: comparator i/o operating modes note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i nten de d to be a com pr ehe nsi v e refer enc e source . for m o re i n fo rm a tio n, ref e r to th e ? p i c 24 f fa mi l y r e f er e nc e m a nu al ? , ? s ec tion 16. o u tpu t c o m p ar e ? (d s3 970 6). c2 c2 in- v in - v in + c2 i n + cv re f c2 i n + c2out (1 ) cm con<7> c1 c1 in- v in - v in + c1 i n + cv re f c1 i n + c1out (1 ) cm con<6> c1 n e g c1pos c2 neg c2 pos c1 inv c2inv c1 o ut e n c2 o u ten c1en c2 en note 1 : thi s p e ri phe ral? s ou tput s m u s t b e a s s i gn ed to a n a v ai la ble rp n p i n befo r e u s e . ple a s e s e e secti o n 1 0.4 ?pe r iphe r a l pin sele ct? for mo re i n for m at ion .
pic24fj64ga004 family ds39881d-page 202 ? 2010 microchip technology inc. r e g i ster 22 - 1 : cmcon: c o m p arator control re giste r r/w -0 u -0 r/c-0 r /c-0 r/w -0 r /w -0 r/w -0 r /w -0 cmidl ? c 2evt c1evt c2 en c1en c2outen (1 ) c1outen (2) bit 15 bit 8 r-0 r -0 r/w - 0 r /w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 c2 o ut c1 o ut c2 inv c1 i nv c2 neg c2 p os c1 neg c1 p os bi t 7 bit 0 le gen d : r = read abl e b i t w = w r it a b le bi t u = un im pl em ent ed b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bit is se t ? 0? = bit is cl eare d x = bi t is u n kn own bi t 15 cm idl : s t op in i d le mo de bit 1 = w he n d e v i ce en ters id le m o d e , m o d u l e do es no t ge nera t e i n te rrup t s; mo dul e i s s t i ll e n a b le d 0 = c ont inu e no rm al m o d u le op erat ion in idle m o d e bi t 14 u nimp l em ente d: re ad as ? 0 ? bi t 13 c2evt : co m p a r ator 2 ev en t 1 = c om p a ra tor outp u t cha nge d s t a t es 0 = c om p a ra tor outp u t did not ch ang e s t at es bi t 12 c1evt : co m p a r ator 1 ev en t 1 = c om p a ra tor outp u t cha nge d s t a t es 0 = c om p a ra tor outp u t did not ch ang e s t at es bi t 1 1 c2 en: co m p a r ato r 2 enable 1 = c om p a ra tor is ena ble d 0 = c om p a ra tor is dis a b l ed bi t 10 c1 en: co m p a r ato r 1 enable 1 = c om p a ra tor is ena ble d 0 = c om p a ra tor is dis a b l ed bi t 9 c2 outen: co m p a r ato r 2 o u tput ena b le (1 ) 1 = c om p a ra tor outp u t is driv en on the ou tput p a d 0 = c om p a ra tor outp u t is not driv en on the ou tput p a d bi t 8 c1 outen: co m p a r ato r 1 o u tput ena b le (2 ) 1 = c om p a ra tor outp u t is driv en on the ou tput p a d 0 = c om p a ra tor outp u t is not driv en on the ou tput p a d bi t 7 c2 out : co mp arat or 2 o u tpu t bi t whe n c2 inv = 0 : 1 =c 2 v in + > c 2 v in - 0 =c 2 v in + < c 2 v in - whe n c2inv = 1 : 0 =c 2 v in + > c 2 v in - 1 =c 2 v in + < c 2 v in - bi t 6 c1out: comparator 1 output bit when c1inv = 0 : 1 =c 1 v in + > c 1 v in - 0 =c 1 v in + < c 1 v in - whe n c1inv = 1 : 0 =c 1 v in + > c 1 v in - 1 =c 1 v in + < c1 v in -
? 2010 microchip technology inc. ds39881d-page 203 pic24fj64 ga004 family bi t 5 c2 inv : c o mp ara t or 2 o u tpu t in ve rsi on bit 1 = c 2 ou t p ut i nv er t e d 0 = c 2 o u tpu t no t i n ve rted bi t 4 c1 inv : co mp ara t or 1 o u tpu t in ve rsi on bit 1 = c 1 ou t p ut i nv er t e d 0 = c 1 o u tpu t no t i n ve rted bi t 3 c2 neg: co m p a r ato r 2 n e gati v e inp u t c o nfi gure bi t 1 = i np ut i s c o n nec ted to v in + 0 = i np ut i s c o n nec ted to v in - see fig u re 22-1 f o r t h e c o mpar a t or m o d e s . bi t 2 c2pos: co m p a r ato r 2 po si tiv e i npu t c o n f ig ure b i t 1 = i np ut i s c o n nec ted to v in + 0 = inp ut i s c o n nec ted to cv re f see fig u re 22-1 f o r t h e c o mpar a t or m o d e s . bi t 1 c1 neg: co m p a r ato r 1 n e gati v e inp u t c o nfi gure bi t 1 = i np ut i s c o n nec ted to v in + 0 = i np ut i s c o n nec ted to v in - see fig u re 22-1 f o r t h e c o mpar a t or m o d e s . bi t 0 c1pos: co m p a r ato r 1 po si tiv e i npu t c o n f ig ure b i t 1 = i np ut i s c o n nec ted to v in + 0 = inp ut i s c o n nec ted to cv re f see fig u re 22-1 f o r t h e c o mpar a t or m o d e s . note 1 : if c2o u ten = 1 , t h e c 2 ou t pe r i ph er a l o u t pu t mu st be co n f i g ur e d t o an avai l a b l e r p n pi n. s e e se ction 1 0 .4 ?p er ip her a l pin se lect ? f o r m o re inf o rm ati on. 2: if c1o u ten = 1 , t h e c 1 ou t pe r i ph er a l o u t pu t mu st be co n f i g ur e d t o an avai l a b l e r p n pi n. s e e se ction 1 0 .4 ?p er ip her a l pin se lect ? f o r m o re inf o rm ati on. r e g i ster 22 - 1 : cmcon: c o m p arator control re giste r (continue d)
pic24fj64ga004 family ds39881d-page 204 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 205 pic24fj64 ga004 family 23 .0 comp arator v o lt a g e re fer e nc e 23. 1 c onf igur ing t he comp ar ato r v o l t age ref e ren c e th e v o l t ag e re feren c e m odu le i s con t rol l e d th roug h th e c v r c o n reg i s t er (r egi ste r 23 -1). the co mp ara t or v o l t age r e fere nc e pro v id es t w o r ang es o f o u tp ut v olt age , e ac h w i th 16 dis t i nct le ve ls . th e rang e t o b e us ed is s e l e c t ed b y th e c v r r bi t (c vr c o n <5 >). th e pr im ary di f f e r en ce be tw een th e rang es is the si ze o f th e s t ep s s e l e ct ed b y t he c v re f sele cti on bit s (c vr 3: c v r 0 ), w i th one rang e of fer i ng f i ne r res o lu tio n . th e c o m p ara t or re fere nc e su pp ly v o l t ag e c a n c o m e f r om ei t he r v dd an d v ss , o r the ex tern al v re f + an d v re f -. th e vo lt ag e so urc e is s e l e ct ed by the c v r s s b i t (cvrcon<4 > ). the sett ling time of t he c o mp arat or volt age r efer ence must be consid ered w hen changing the c v re f o u tput. figure 23-1: comp ar ato r v o lt a g e re fere nce block dia g ra m note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e source. for more information, refer to the ?pic24f family reference manual? , ?section 20. comparator voltage reference module? (ds39709). 16-to-1 mux cvr3:cvr0 8r r cvren cv rs s = 0 av dd v re f + cvrss = 1 8r cv rs s = 0 v ref - cv rs s = 1 r r r r r r 16 steps cvrr cv re f av ss
pic24fj64ga004 family ds39881d-page 206 ? 2010 microchip technology inc. r e g i ster 23 - 1 : cvr c on: comp ara t o r v o lt age re f e re nce control regis t er u-0 u -0 u-0 u -0 u-0 u -0 u-0 u -0 ? ? ? ? ? ? ? ? bi t 15 bi t 8 r/w - 0 r /w -0 r/w - 0 r /w -0 r / w - 0 r /w -0 r/w - 0 r /w -0 cvren c vro e cvrr cvrss c vr3 c vr2 c vr1 c vr0 bi t 7 bi t 0 le gen d : r = r ead abl e b i t w = w r i t ab le b i t u = u n im pl em ente d b i t, read as ?0 ? -n = v a l ue a t po r ? 1? = bi t is s e t ? 0 ? = bit is cl eare d x = bit i s u n k nown bi t 15 - 8 un im pl e m e n te d : r ead as ? 0 ? bi t 7 cvren: c o mp ara t or v o lt a g e r e fe renc e en ab le b i t 1 =c v re f circ ui t po w e re d on 0 =c v re f circ ui t po w e re d do w n bi t 6 cvroe: c o mp arat or v re f o u t put enab le bit 1 =c v re f vol t ag e l ev el i s outp ut on c v re f pi n 0 =cv re f vol t ag e l e v e l i s dis c o nne ct ed f r om c v re f pi n bi t 5 cvrr: co mp ara t or v re f ra nge sele c t io n bit 1 =c v rs rc rang e s h o u ld be 0 to 0.6 2 5 c v rs rc with cv rs rc /24 st ep siz e 0 =c v rs rc rang e s h o u ld be 0.2 5 to 0.7 19 c v rs rc with c v rs rc / 3 2 s t e p si ze bi t 4 cvrss: co m p ara t or v re f sourc e sele cti on bit 1 = c o m p a rat o r re fere nc e s ourc e cv rs rc = v re f + ? v re f - 0 = c o m p a rat o r re fere nc e s ourc e cv rs rc = a v dd ? a v ss bi t 3- 0 cvr3 :cvr0 : co m p arator v re f v a l ue se le cti on 0 ? cvr3 : c v r 0 ? 15 bi t s w h e n cvrr = 1 : cv re f = (cvr<3 :0>/ 24) ? (cv rs rc ) when cvrr = 0 : cv re f = 1/4 ? (c v rs rc ) + (cvr<3:0>/32) ? (cv rsrc )
? 2010 microchip technology inc. ds39881d-page 207 pic24fj64 ga004 family 2 4 .0 spec ia l fe atu r e s pic 2 4fj 6 4 g a0 04 f a m ily de vic e s in cl ude sev e ra l fe atu r es i nte nde d to m ax i m i ze app lic ati on fl ex ibi l i t y an d reliabil i ty , an d mi nim i z e co st thro ugh el im in atio n of e x te rnal c o m pon ent s. t hes e a r e: ? f l e x i bl e c o nfi gura t io n ? w a t c h dog t i m e r (wdt) ? c od e pro t ec tio n ? j t a g boun dary sc an inte rfac e ? i n - c i rc uit seri al program m i n g ? i n- c i r c u i t e m ul at i o n 24. 1 c onf igur ati on bit s the c onfiguration bit s ca n be program med (r ea d as ? 0 ?), or lef t u nprogramme d (read as ? 1 ?), to selec t v a rious dev ice configuration s . thes e bit s are m apped s t art i ng at program memo r y locatio n f80000h. a com plete lis t is s how n i n t able 2 4 - 1. a det ail ed expla nation of the vari- ous bit fun c tions is prov ided in r egister 24-1 through r egis t e r 24 - 4. n o t e t h at ad dr e ss f 800 00 h i s b e yo nd t h e us er pr o g r a m m e m o ry sp ac e . in fa ct , i t b e l o n g s to th e c o n f i g u r at io n m e m o ry s p ac e (8 00 00 0h -ff fff fh ) w h i c h ca n o n l y b e ac ces s e d us in g tab l e r e ad s an d tab l e w r i t e s . 24. 1.1 c o n s i dera t i o n s f o r configuring p i c24 f j6 4g a0 04 fam ily de vice s in pi c 2 4fj6 4 g a0 04 fa mi ly d e v i c e s, th e co nfi g ura t io n by te s are im ple m e nte d as vol ati le m em ory . t his me an s th at c onfi gur atio n da t a m u s t b e pro g ram m e d e a ch tim e th e d e v i ce i s p o w e re d u p . c o nfi gur atio n d a t a is s t ore d i n the tw o w o rds at th e to p of the o n -c hi p pro g ram m e m o ry sp ac e, k now n as the f l a s h c o nfi g ura t io n w o r d s . t h ei r s p ec if i c lo ca t i on s ar e sh ow n in t abl e 2 4-1. the s e are p a c k e d r epre s e n t a tion s o f th e ac tu al d e vi ce c o nfi gur atio n bi t s , w h os e ac tua l l o ca tio n s a r e d ist ribu ted am ong f iv e lo cat ion s i n co nfi g - ur atio n sp ac e. th e co nfig ura t ion d a t a i s au tom a ti ca ll y l oad ed from the fl as h c o nfi gura t io n w o rds to th e pr ope r c onf igu r ati on regi ste r s duri ng dev ic e r e se t s . t able 2 4 -1: flash configuration w o rd locations for pi c24f j 64g a00 4 f a m i l y de vice s wh en cre ati ng app li cat i on s for t hes e dev ic es , u s er s s hou ld alw a ys s pec ifi c a lly al lo ca te th e l oc ati on o f th e fl as h c o nfi gurat io n w o rd fo r co nfi gur ation d a t a . t h is i s to m a k e ce rt ai n tha t prog ram c o d e is n o t sto r ed i n this ad dre s s wh e n th e c ode is c o m p il ed. th e c o n f ig urat ion bit s are relo ad ed fro m t he fl as h c o nf i g u r a t i o n w o r d on an y d e v i ce r e s e t. th e upp er by te of both f l as h c onf igu r ati on w o rds i n pr ogra m m e m o ry sh ou ld a l w a y s b e ? 1111 1111 ?. thi s m a k e s the m app ear to b e nop ins t ru cti ons i n th e re mo te e v e n t tha t th eir lo ca tion s are ev er ex ecu t ed b y a cci d e n t . s i nc e c o nf i g u r a t i o n b i ts a r e no t i m p l em en t e d i n th e c o rr esp ond in g l o c a tio n s , w r i t in g ? 1 ?s to t he s e lo c a t i on s h a s no e f f e c t on de vi ce o p e r at i o n. note : th is d a t a s hee t s u m m a riz e s t he fea t ure s o f thi s g r oup of pi c 24f dev ic es . it i s n o t i n ten d e d to be a com p re he nsi v e refer enc e s our c e . for m o re i n fo rm a tio n, ref e r to th e fo llo w i ng s e c t io ns of the ?pic2 4 f fam i l y r e fe r e nc e m a n u a l ? : ? section 9. ?w atchdog t i mer (wdt)? (ds39697) ? section 32 . ?high-level d evi ce i n t egration? ( d s39719) ? section 33 . ?programm i ng and diagnosti cs? (ds39716) note : configuration data is reloaded on all types of device re se t s . de v i c e con f igura t ion w o rd a ddr es se s 12 pic 2 4fj 16g a 002 bfeh 002 bfc h pic 2 4fj 32g a 005 7feh 005 7 f c h p i c 2 4 f j4 8 g a 0 083 f e h 0 083 f c h pic2 4fj 64ga 0 0 abfeh 00 abfch
pic24fj64ga004 family ds39881d-page 208 ? 2010 microchip technology inc. regis t er 24-1: cw 1: flash co n f i g u ration w o rd 1 u-1 u -1 u-1 u -1 u-1 u -1 u-1 u -1 ? ? ? ? ? ? ? ? bi t 23 bi t 16 r-x r/p o -1 r/po - 1 r/po-1 r/po-1 r-1 r/ po -1 r/po - 1 r j t a gen g cp gwrp debug r i cs1 ics0 bi t 15 bi t 8 r / p o - 1r / p o - 1 u - 1 r / p o - 1r / p o - 1r / p o - 1r / p o - 1r / p o - 1 f w dten windis ? f w psa w d tps 3 w d tp s2 w d tp s1 wdtps0 bi t 7 bi t 0 le gen d : r = r e ser v ed bi t r = read abl e b i t p o = prog ram o n c e b i t u = u n im pl em ente d b i t, read as ? 0 ? -n = v a l ue w h en dev ic e i s u n p r ogra m m e d ? 1 ? = bit is se t ? 0? = bi t is c l ea red bi t 23 - 1 6 un im pl e m e n te d : read as ? 1 ? bi t 15 r e ser v e d: t he va lue is un kno w n; p r og ram as ? 0 ? bi t 14 jt a g e n : j t ag port enab le bit 1 = j t ag p o rt is ena ble d 0 = jt a g po r t i s d i sa bl e d bi t 13 gcp: g e n e ra l se gme n t progra m me mo ry c o de p r otec ti on b i t 1 = c o d e p r ote c ti on is dis a b l ed 0 = c o d e p r ote c ti on is ena ble d f o r th e e n tir e pro g ra m m e m o ry s p ac e bi t 12 gwrp: ge ner al se gm en t c ode fl as h w r ite prot ect i on bi t 1 = w r i t es to pr o g r am me mo r y ar e al l o w e d 0 = w r i t es to pr o g r am me mo r y ar e di s a b l e d bi t 1 1 debug : ba ck grou nd d ebu gge r ena b l e bi t 1 = d e v i c e re se t s int o o p e r ati ona l m ode 0 = d e vi ce r es ets i n to d e bu g m od e bi t 10 reserv e d: al w a ys ma in tai n a s ? 1 ? bi t 9- 8 ic s 1 : i c s 0 : emu l at or pi n pl ac eme n t sele ct bit s 11 = em ul ator emu c 1 /emu d 1 pin s are sha r ed wi th pg c 1 /pg d 1 10 = em ul ator emu c 2 /emu d 2 pin s are sha r ed wi th pg c 2 /pg d 2 01 = em ul ator emu c 3 /emu d 3 pin s are sha r ed wi th pg c 3 /pg d 3 00 = r e s e rv ed ; do no t us e bi t 7 fw d t e n : w a tch d o g t i m e r enab le bit 1 = w a tch dog t i m e r i s ena ble d 0 = w a tch dog t i m e r i s dis a b l ed bi t 6 w i ndis: w i nd ow ed w a tc hd og t i m e r d i s a b l e bit 1 = s t an dard w a t c h dog t i m e r e nab led 0 = wi ndo w ed w a tc hd og t i me r en abl ed ; fwd t en mu st be ? 1 ? bi t 5 un im pl e m e n te d : read as ? 1 ? bi t 4 f w psa: w d t pres ca ler ra ti o sel e c t bi t 1 = p r es ca l er r a ti o of 1: 1 2 8 0 = p r es ca l er r a ti o of 1: 3 2
? 2010 microchip technology inc. ds39881d-page 209 pic24fj64 ga004 family bi t 3- 0 w d tps3:w dtps0: w a tc hdo g t i me r pos t s c al er s e le ct b i t s 11 11 = 1 : 32 ,768 11 10 = 1 : 16 ,384 11 01 = 1: 8 , 19 2 11 00 = 1: 4 , 09 6 10 11 = 1: 2 , 04 8 10 10 = 1: 1 , 02 4 10 01 = 1 : 51 2 10 00 = 1 : 25 6 01 11 = 1 : 12 8 01 10 = 1 : 64 01 01 = 1 : 32 01 00 = 1 : 16 00 11 = 1 : 8 00 10 = 1 : 4 0001 = 1:2 0000 = 1:1 regis t er 24-1: cw 1: flash co n f i g u ration w o rd 1 (co n tinued )
pic24fj64ga004 family ds39881d-page 210 ? 2010 microchip technology inc. regis t er 24-2: cw 2: flash co n f i g u ration w o rd 2 u-1 u -1 u-1 u -1 u-1 u -1 u-1 u -1 ? ? ? ? ? ? ? ? bi t 23 bi t 16 r/po-1 r/po-1 r/po-1 r/po-1 r / po -1 r/po-1 r/po-1 r/po-1 i eso wutsel1 (1 ) wutsel 0 (1 ) soscsel 1 (1 ) soscsel0 (1 ) fno s c2 fno s c1 fno s c0 bi t 15 bit 8 r/po-1 r/po-1 r/po-1 r/po-1 u-1 r /po-1 r /po-1 r /po-1 fcksm 1 f cksm 0 os ci o f cn i o l 1 w a y ? i 2 c 1 s e l p o s cm d1 poscmd0 bi t 7 bit 0 le gen d : r = re s e rv e d bi t r = read abl e b i t p o = pro g ram o n c e b i t u = u n im pl em ent ed b i t, read as ? 0 ? -n = v a l ue w h en dev ic e i s u n p r ogra m m e d ? 1? = bit is se t ? 0? = bi t is c l ea red bi t 23 - 1 6 u n i m pl e m en t e d: rea d as ? 1 ? bi t 15 ieso: inte rna l ex tern al switc hov er bit 1 = ieso m o d e (t w o -s pee d s t art - up) ena ble d 0 = ieso m o d e (t w o -s pee d s t art - up) dis a b l ed bi t 14 - 1 3 wutsel1 : wutsel0 : v o lt a ge r e gul ato r sta ndb y m o d e wa ke -up tim e se le ct b i t s (1 ) 11 = de faul t re gul ato r st art-u p ti me us ed 01 = fa st reg u la tor s t a r t-up tim e u s e d x0 = re ser v ed ; do no t us e bi t 12 - 1 1 so scsel 1:soscsel0: second ary o s c ill ato r pow e r mo de sele ct bit s (1 ) 11 = de faul t (h i gh d r i v e s t reng th) mo de 01 = l o w-powe r (lo w drive s t ren g th ) m ode x0 = re ser v ed ; do no t us e bi t 10 - 8 fno s c2 :fnosc0 : in iti a l os ci ll ator sele ct bit s 111 = f a s t rc os ci l l a t o r wi th po st sc a l e r (frcdiv) 110 = re se rved 101 = l o w-po we r rc os ci l l a t o r (l prc) 100 = se c o nda ry os c i lla tor (so s c) 011 = pri m a r y os ci lla tor w i th pll mo dul e (xtp ll, h spll, ec pll) 010 = pri m a r y o s ci lla tor (xt , hs, ec) 001 = f a st rc o s c ill ato r wi th po st s c a le r an d pll m odu le (fr c p ll ) 000 = f a s t rc os ci l l a t o r (frc) bi t 7- 6 fcksm 1 :fcksm 0 : cl o c k sw itc h i ng and fai l -sa f e c l oc k m o n i to r c onf igu r ati on bit s 1x = c l o c k s w itc h i ng and fai l -sa f e c l oc k m o n i to r are dis a b l ed 01 = c l o c k s w itc h i ng is ena bl ed, fai l -saf e c l o c k m oni tor is dis a b l ed 00 = c l o c k s w itc h i ng is ena bl ed, fai l -saf e c l o c k m oni tor is ena ble d bi t 5 o s ciofcn: os c o p i n c o nf i g u r a t io n b i t if poscm d 1 : poscm d 0 = 11 or 00 : 1 = o s c o /c lko / r a 3 func tions as clko (f osc /2) 0 = osco/clko/ra3 functions as port i/o (ra3) if poscmd1:poscmd0 = 10 or 01 : osc i o f c n h a s no ef fec t on o s c o / c l k o / r a 3. bi t 4 io l 1 w a y : io lo c k o n e - w a y set enab le bit 1 = t he o s c c o n < io lo c k > bi t c an b e se t on ce, prov id ed th e u nlo ck se que nc e ha s be en c om pl ete d. on ce se t, th e pe riph era l pin sel e c t registers c ann ot b e w r i tten to a s e c ond tim e . 0 = t he o s c c o n < io lo c k > bit c an be s et a nd c l ea red as nee ded , prov id ed th e unl oc k se qu enc e ha s bee n c om ple ted bi t 3 u n i m pl e m en t e d: rea d as ? 1 ?
? 2010 microchip technology inc. ds39881d-page 211 pic24fj64 ga004 family bi t 2 i2c1sel : i2c1 pin sel e c t bi t 1 = u s e de f a ul t s c l1 / s d a 1 p i n s 0 = u s e a l ter nate sc l1 /sd a 1 p i ns bi t 1- 0 po scm d 1:poscm d 0 : pri m a r y o s cil l a t or c o nfi gura t io n bi t s 11 = pri m a r y o s c i l l at or d i sa bl ed 10 = hs o s ci lla tor m o d e s e l e c t ed 01 = xt os c ill ato r mo de se lec t ed 00 = ec o s ci lla tor m o d e s e l e c t ed note 1 : t h e s e bi ts ar e i m pl em en t e d on l y in de vi ce s w i t h a m a j o r s i l i c o n r e v i s i on l e ve l o f b or la t e r ( d e v r e v r e g i s- te r v a lu e i s 3 042 h o r gre a ter ) . refe r to sect ion 2 8.0 ?pa cka ging info r m atio n? in the dev ic e d a t a sh eet for the location and interpretation of product date codes. regis t er 24-2: cw 2: flash co n f i g u ration w o rd 2 (co n tinued ) regis t er 24-3: dev i d: d e vi ce i d re g i ste r uu uuuuu u ? ? ? ? ? ? ? ? bi t 23 bi t 16 uu rrrrr r ? ? f am id7 f am id6 f am i d 5 f am id4 f am id3 famid2 bi t 15 bi t 8 rr rrrrr r f a m i d1 f a m i d0 d e v5 dev4 dev3 dev2 dev1 d e v0 bi t 7 bi t 0 le gen d : r = read -on l y bit u = u n im pl em ente d b i t bi t 23 - 1 4 un im pl e m e n te d : read as ? 1 ? bi t 13 - 6 f a m i d7 :f amid0 : de vi ce fam i l y i den tifi er b i t s 00 010001 = pic 24f j6 4g a004 fam i l y bi t 5- 0 dev5 :dev0: i ndi vi dua l d e vic e iden tif i er b i t s 00 0100 = pi c 24f j16 g a 002 000101 = pi c 24f j32 g a 002 00 0110 = pi c 24f j48 g a 002 00 0111 = pi c 24f j64 g a 002 00 1100 = pi c 24f j16 g a 004 00 1101 = pi c 24f j32 g a 004 00 1110 = pi c 24f j48 g a 004 00 1111 = pi c 24f j64 g a 004
pic24fj64ga004 family ds39881d-page 212 ? 2010 microchip technology inc. regis t er 24-4: dev r e v : dev i ce re vis i on re giste r uu uuuuu u ? ? ? ? ? ? ? ? bi t 23 bi t 16 uuuuuuur ? ? ? ? ? ? ?m a j r v 2 bi t 15 bi t 8 rr uuurr r majrv1 majrv0 ? ? ? d ot 2 d ot 1 d o t 0 bi t 7 bi t 0 le gen d : r = r ead -on l y bit u = u nim pl em ente d b i t bit 23 - 9 un im pl e m e n te d : r ead as ? 0 ? bi t 8- 6 maj r v 2 : m aj r v 0: ma jo r rev i s i on ide n ti fie r bit s bi t 5- 3 un im pl e m e n te d : r ead as ? 0 ? bi t 2- 0 dot2 :do t 0 : m i n o r r e v i s i o n id ent ifi e r bi t s
? 2010 microchip technology inc. ds39881d-page 213 pic24fj64 ga004 family 24. 2 o n- c h ip v o l t age regula t or al l of the pi c 2 4fj 6 4 g a0 04 fa mi ly of d e v i c e s po w e r th eir c ore dig i t a l lo gic at a nom in al 2 . 5v . th is ma y c r ea te an i s s u e fo r des ig ns t hat a r e req u ire d to op era t e a t a hi ghe r typ i c a l v o lt age , su ch a s 3 . 3v . t o si mp lif y s y s t em de si gn, a l l d e v i c e s i n th e pic 2 4 f j 64g a00 4 fa mi ly inc o rp orat e an on-c h i p reg u la tor t hat a llo w s th e d e vi ce to r un it s co r e l o g ic fr om v dd . th e r e g u l a t o r is co nt r o l l e d by t h e d i s v r e g pi n. t y i n g v ss t o th e pi n enab le s the r e g u l a t o r , w h i c h in t u rn , p r o- v i d e s po w e r t o th e co re f r om th e ot he r v dd pi ns . wh en th e r eg ul a to r i s en ab le d, a lo w - e s r capac it or ( s u c h a s c e r a m i c ) mu st b e co nn ec te d t o the v ddco re /v ca p pi n (f ig ure 2 4-1 ) . th is h e l p s to m a i n t a i n the s t abi li ty of th e r e g u l a t o r . t h e r e com m en de d va lu e fo r t h e f i l t e r ca p a ci t o r i s pro v id ed in se cti o n 2 7 . 1 ?d c c h a r ac ter i sti cs? . if d i svreg i s ti ed t o v dd , t he re gul ato r is d i s abl ed . in th is ca se , s e p a r ate po w e r fo r th e c o re lo gic at a n o m i - n al 2 . 5v m us t be s upp li ed to t he d ev i ce on th e v ddc o r e /v ca p p i n to r un the i/o p i ns at hi ghe r vol t ag e l e v e ls , t y p i ca ll y 3.3v . alt e rna t iv el y , t he v d dco re /v ca p a nd v dd pi ns c a n b e t i ed t oge the r to o pera t e at a lo w e r no mi n a l vo l t ag e. r e f e r t o figure 24-1 f o r p o s s i b le c onf igu r ati ons . 2 4 . 2 . 1 v ol t a ge re gula tor t r ack i n g mode an d low - v o lt a g e dete ction w hen it i s e nab led , the on -ch i p re gul ato r pro v id es a c ons t a nt vo lt a ge of 2.5 v n om i na l t o the di git al co re l ogi c. th e re gul ator c a n prov id e thi s l e v e l fr om a v dd of abo ut 2 . 5v , all the way u p to th e d e v i c e ? s v ddm a x . it d oes n o t h a ve th e c a p abi lit y t o bo os t v dd le ve ls bel ow 2 . 5v . in o r der to prev en t ?bro w n out ? c o n d it ion s w h e n the vo lt- a ge d r op s to o l o w fo r the reg u la tor , the regu la tor e n te rs t r a c k i ng m ode . i n t r a c k i ng m ode , t he regu lat o r o u tp ut fo ll ows v dd , w i th a ty pic al vo lt a ge drop of 100 mv . w hen t he de vi ce e n te rs t r ac ki ng m o d e , it i s no l ong er p o ss ib le to o pera t e at fu ll s pee d. t o prov id e inf o rm atio n a bou t w hen the dev ic e en ters t r ac ki ng m o d e , th e o n -c hip reg u la tor i n c l ud es a s i m p l e , l o w - v o l t ag e detec t circu i t. w hen v dd dr o p s be l ow f u ll - s pe ed o pe r - a t ing v o lt age , the c i rc uit se t s t he low -v o l t a ge d e tect i n t e r r u p t f l ag , l v d i f ( i f s 4 < 8 > ). th i s ca n be us ed t o g ene rate an in terru pt and p u t t he app li cat i on i n to a l o w - po w e r op erati o n a l m ode , or tri gge r an ord e rl y s hut dow n . l ow - v ol t ag e d ete cti on is o nl y av ail abl e w hen th e re gul ato r is en abl ed. figure 24-1: conne ctions for the on-chip regulator 24. 2.2 o n-chip regul a tor a nd p o r w h e n th e vo lt age re gu la tor is e n a b l ed, it t a ke s ap pro x i - ma te ly 2 0 ? s f o r i t t o ge ne rat e ou tp ut. d u ri ng th is ti me , de si gn at ed as t st a r t u p , c o d e ex ec ut io n is d i s a b l e d . t st a r t u p is ap pl ie d ev ery ti me t h e d e v i ce r e s u m e s o p e r at io n a f t e r an y p o w e r-d ow n , i n c l ud in g sl ee p mo de . if th e re gu lato r i s di sab l e d , a s e p a ra te power-u p t i m e r (pw r t) i s aut om ati c al ly en ab led . th e p w r t add s a fi xe d de la y o f 64 m s n o m ina l d e la y a t de vi ce st ar t- u p . v dd disvreg v ddcore /v cap v ss pic24fj64ga 3.3v (1) 2. 5v (1) re g u l a to r di sab l e d (di svreg ti e d to v dd ): v dd dis v re g v dd co re /v ca p v ss pi c24f j64g a 2. 5v (1 ) reg u l at o r di sab l e d (v dd ti ed to v dd co re ): v dd d i svr eg v dd co re /v ca p v ss pi c24f j64g a c efc 3.3v (10 ? f ty p ) r e gul a t or e n a b l e d ( d i s v r eg t i e d t o v ss ): no t e 1 : t hes e are t y pical oper at ing volt ages . ref e r to secti o n 27.1 ?dc characteristics? for the full operating ranges of v dd and v ddcore .
pic24fj64ga004 family ds39881d-page 214 ? 2010 microchip technology inc. 24. 2.3 o n- c h ip regul a tor a nd b o r when the on- c h ip regulator is enabled, pic 2 4fj 6 4 g a0 04 family dev ices also have a simple brow n-out cap ability . if the volt age supplied t o the re g- ulator is inadequat e to maint ain t he tr ack i ng l evel, the regulator r e set circuitr y w ill generate a br ow n- out r e set. this event is captur ed by the b o r flag bit (r c o n < 1>) . the brow n - out volt age levels are speci- fied in s e c t i o n 2 7. 1 ? d c c h ar a c t e r i s t ic s ? . 24. 2.4 p o w er- u p re q u ire m en t s th e o n -c hip reg u la tor is des ig ned to me et th e p o w e r-u p re qui rem ent s for the de vice . if the ap pli c a t io n d oes n o t u s e t he re gul ato r , the n s t ric t po w e r-up co ndi tio n s m u s t b e a dhe red to. wh ile po w e rin g u p , v d dco re mu st n e ve r ex c eed v dd b y 0.3 vo lt s . 24. 2.5 v olt a ge regul a tor s t a ndb y mo de wh e n e n a b l ed , th e on - c h i p r e gu l a t o r al w a ys co ns um es a s m all i n c r em ent al am ou nt of c u rre nt ov er i dd /i pd , i nc l ud ing w h en th e dev ic e is i n sle ep m ode , eve n th oug h the cor e dig i t a l lo gic doe s no t requ ire p ow er . t o p r ov ide ad dit i on al sa vin g s in ap pli c a t io ns w here po w e r re so urc e s are cri t ic al , th e re gu lato r a u tom a t i c a ll y p l ac es i t se lf int o s t a ndb y mod e w hen ev er t he dev ic e g oes in to sle ep m o d e . th is feat ure i s c ont roll ed b y th e vreg s b i t (rco n<8 > ). by defa u l t, th is bi t i s cle a re d, w h ich en abl es s t and by mo de . fo r se lec t pic 2 4fj 64g a0 04 fa mi ly dev ic es , the tim e re qui red fo r regu lat o r w a k e -up f r om s t a ndb y mo de i s c ont roll ed by t he wu tsel <1:0 > c onfi gur atio n bit s (c w 2 <14 : 13 >). t he d e fa ult w a ke -up tim e f o r al l d e vi ce s is 19 0 ? s. wh ere th e wu tsel c onfi gur atio n b i t s are im pl em ent ed, a f ast w ak e-up op tio n i s als o a v ai la ble . w hen w u t sel<1 :0> = 01 , th e regu la tor wa k e -u p t i me i s 2 5 ? s. w hen the re gul ato r ? s s t an db y m ode is t u rne d of f (vregs = 1 ), f l as h p r og ram m e m o ry st ay s p o w e re d i n sl eep m ode a nd the de vic e ca n w a ke -up in les s tha n 10 ? s. wh en vr eg s is s e t, t he po w e r co ns um ptio n w h i l e in s l ee p mo de w i ll b e ap p r ox im at e ly 4 0 ? a h i gh er th an pow e r co ns um ptio n w h en t he re gu lato r is al lo w e d to en ter s t a ndb y m o d e . 24. 3 w at chdog t i m e r ( w d t ) fo r pic 2 4 f j 64g a00 4 f a m ily de vi ce s, t he wd t i s dr ive n by the lpr c os ci ll ator . whe n the wd t i s en ab led , th e c l oc k so urc e is a l so en abl ed. th e no mi nal wd t cl oc k s ourc e fro m lp r c i s 31 kh z . th is feed s a p r es ca ler th at c an b e co nfi gure d for e i th er 5- bit (d ivi d e - by- 32) or 7-b i t (di v i de-b y -1 28) op era t io n. th e p r es c a ler is s e t by th e f wpsa con f ig urat ion bi t. w it h a 31 kh z i n pu t , t h e pr e s c a le r y ie l ds a no mi n a l wdt ti m e -ou t p e ri od (t wdt ) o f 1 m s in 5 - bit m ode , or 4 m s i n 7 - bi t mo de . a v a ri abl e p o s t sc al er d i vi de s d o w n t he w d t pre s c a l e r ou tpu t a nd al low s fo r a wi d e rang e of tim e -ou t p e ri ods . th e p o s t s c al er is co ntro lle d by the wd t ps3:wd t ps0 c o n f ig urat ion bi t s (fla sh c onf igu r ati o n w o r d 1< 3:0 > ), w h ic h a l l o w t h e se l e c t i o n o f a t o t a l of 1 6 s e t t i ng s, f r o m 1: 1 t o 1 : 32, 768 . u s ing th e p r es ca ler and po st sc ale r , ti me -out per iod s ra ngi ng from 1 m s to 1 31 se con ds ca n be ac hi ev ed. th e w d t , p r es ca ler and po st s c a l e r are res e t: ? o n a n y de vic e r e se t ? o n t he c o m p l e ti on of a cl oc k s w itc h , w heth e r i n vo ke d b y s o f t w are ( i .e. , s e tti ng the osw e n bi t af ter c h a ngi ng the no s c bit s ), or by h a rdw a re (i .e., fai l -saf e c l o c k m oni tor) ? w he n a pwrsa v ins t ru cti on is ex ec uted (i .e., slee p o r idl e m o d e i s e n te red) ? w he n t h e d e v i c e exits s l e e p or i d l e mo de t o re sum e norm a l op erat ion ?b y a c lrwdt in str uct ion du ring no rma l e x ec ut ion if the wd t i s e nab led , it w ill co nti nue to ru n d u rin g sl eep o r idl e mo des . wh en th e wd t ti me -out o c c u rs , t h e de vi ce w i ll w a k e t h e de v i c e a n d co de ex ec u t i o n w i ll c ont inu e from w her e the pw rsav i n st r u ct io n wa s e x e - c u te d. th e c o rres p o ndi ng sl eep or idl e bit s (r c o n < 3:2 > ) w ill n eed t o be cl ea red in s o f t w are af t e r th e d e vi ce wak e s up . th e w d t fl ag bit, wd t o (r c o n < 4 > ), is not aut o- m a ti ca lly c l e a red f o ll ow in g a w d t t i m e -ou t. t o de tec t s ubs eq uen t w d t e v e n t s , the fl ag mu st be c l e a red i n so ft war e . note: for more information, see section 27.0 ?electric a l c h a r ac t e r i st i c s? . note : t hi s fe a t ur e i s im pl e m e nt e d on l y on pi c24 f j6 4g a 0 0 4 f a m i l y de vi ce s wit h a m a j o r si lic on rev i si on l e v e l o f b or la ter (d evr ev re gi ste r va lue is 30 42h or g r eat er). note : th e clrwdt an d pwrsav in str u cti o n s c l ea r the p r es caler and postsc ale r co unt s w h en ex ec u t e d .
? 2010 microchip technology inc. ds39881d-page 215 pic24fj64 ga004 family 24. 3.1 w i ndo we d o p e r a t io n th e w a t c h dog t i me r has an o p ti ona l fix e d w i n dow mo de o f op e r at i o n . i n th i s w i nd ow ed mo d e , clrwdt in st r u ct i o n s ca n o n l y r e s e t t h e w d t d u r i ng t h e l a s t 1/ 4 of t h e pr o g r am me d wd t p e r io d. a clr wdt in st r u ct i o n e x ec ut ed befo r e t hat w i nd ow c au s es a wd t r ese t, s i m i l a r to a w d t ti me- out. wi nd ow ed wd t mo de i s e nab led by prog ram m i ng th e wi n d i s co nf i g ur a t io n b i t ( c w 1 <6 > ) t o ? 0 ?. 2 4 . 3 . 2 c ontrol regi s t er th e wd t is e nab le d or dis a b l ed b y the f w d t en c o nf i gu r a t i o n bi t . w he n t he f w d t e n c o nf i g ur a t io n bi t i s s e t, the wd t i s a l w a y s ena bl ed. th e wd t can be o pti ona ll y c ont roll ed i n s of t w a re w h e n th e fwd t en c o nfig ura t ion bit h a s b een prog ram m e d to ? 0 ?. the w d t i s en abl ed in s o f t w a r e by s e tt ing th e swd t en c ontr o l bit (r c o n < 5> ). th e swd t en c ont rol bi t i s cl eare d on any dev ic e r e se t. the s o f t w a re wd t o p tio n al low s t he us er to en abl e the w d t f o r c r iti c a l c o d e s egm en t s an d d i s abl e th e w d t d u rin g n o n - cr i t ic al se gm e n ts f o r m a x i mu m po we r sa vi ng s . figure 24-2: wd t blo c k diagram 24. 4 j t a g i n te rfa c e pic 2 4fj6 4 g a0 04 f a m ily de vi ces im pl em ent a j t ag i n ter f ac e, w h ic h su ppo rt s bo und ary s c a n dev ic e te sti n g . 24. 5 p r ogram v e r i f i ca ti on and code prot ecti o n fo r all d e v i c e s i n the p i c 24f j64 g a004 f a m ily of d e vi ce s, t he o n -c hip prog ram me mo ry s p a c e i s tr eate d a s a s i n g le bl oc k. c ode p r ote c ti on for thi s blo c k i s c ont roll ed by one c o nfig ura t ion b i t, g c p . th is b i t i nhi bit s e x t e rna l re ads an d w r i t es to the pro g ra m m e m o ry s p a c e. it ha s no di rect e f fe ct in no rma l e x ec ut ion mo de . w r ite pro t ec tio n is co ntro lle d by the gw r p bit in th e c o nfig ura t ion w o rd. w hen g w r p i s p r ogra m m e d to ? 0 ?, i n ter nal w r ite a n d eras e o perat io ns t o pro g ra m m e m o ry are bl oc ked . 24. 5.1 c o n f i g ura t i on reg i s t er pr ot e c t i o n th e c onf igu r ati on reg i s t ers are pr otec ted aga i ns t i nad ver t ent or u nw an t ed ch ang es or re ads in tw o w a ys . th e pri m a r y p r ote c ti on m e th od i s th e s a m e as that of th e r p re gi ste r s ? shad ow regi ste r s c ont ain a c o m pl i - m ent ary v alu e w h ic h i s c on s t a ntl y co mp ared w i th th e ac tu al v a l ue. t o s a f egu ard ag ain s t unpred ic t a b l e ev ent s, c o nf igu r a- ti on bit ch an ges re sul t in g f r om in div i d u al c e ll le ve l di sru p ti ons (su c h a s esd ev en t s ) w i l l c a us e a p a rit y er ror a nd t r igg e r a de vi ce r e se t. th e da t a fo r the c o nfi gura t io n reg i s t ers is deri v e d from th e fla s h c o nfi gura t io n w o rds i n pro g ram me mo ry . wh en the g c p bi t i s set , th e s o u r ce da t a for dev i c e c onf igu r ati on is als o p r ote c te d a s a c ons eq uen ce. lprc input wdt overflow wake from sleep 31 khz pre sca l e r p o stscaler f w psa swdten fw d t e n rese t all dev i ce re se ts s l eep or idl e m ode l p rc co n t r o l c lrwdt in s t r . p wrsav in s t r . (5 -b i t / 7-b i t ) 1: 1 to 1: 32.7 6 8 wdtps3:wdtps0 1 ms/4 m s e x i t s l eep or idle mode wdt coun te r t ran sitio n to ne w clo ck so u r ce
pic24fj64ga004 family ds39881d-page 216 ? 2010 microchip technology inc. 24. 6 in- c ir cuit ser i a l progra m m i ng pic 2 4fj 6 4 g a0 04 fam i l y m i c r oc on trol lers c an be se ri- a lly pro gram m ed w h ile in the e nd app lic ati on cir c ui t. th is is si mp ly don e w i t h tw o lin es for c l o ck (pg c x ) an d d a t a (pg d x) an d t h ree o t her li nes f o r p o w e r , g r oun d a nd t he p r og ram m i ng v ol t ag e. th is al low s cu st om ers to m an ufac t u r e bo ards w i th un prog ram m e d de vi ce s an d th en prog ram th e m i c r oc ont roll er j u s t b e fore s h ip pin g th e pro du c t. t his als o a llo w s th e mo st r ece nt fi rmw a re o r a c u s t om fi rmw a re to be pro g ram m ed. 24. 7 i n-ci rcui t debugger wh en mpl a b ? ic d 2 is se le cte d a s a de bug ge r , th e i n-ci r cu it debu ggi ng f unc tio nal ity is enable d. th is func - ti on all ow s s i mp le de bug gin g f unc tio ns w he n u s e d w i th m p lab i d e. d e b ugg ing fun c t i on ali t y is co ntro lle d th roug h the em u c x (emu lat i on /d ebu g c l oc k) an d em u d x (em u l a ti on/ d ebu g d a t a ) p i ns . t o us e the i n -c ircuit de bug ge r fu nc tio n of the d e v i c e , th e de si gn m u s t im ple m e n t ic sp c o n nec tio n s to mcl r , v dd , v ss , pg cx, pg d x and th e em ud x / em ucx p i n p a i r . in a d d i tio n , wh en t he fe atu r e i s ena ble d, so me of th e re so urc es are n o t ava ila bl e f or ge ne ral us e. th ese re so urc e s i n cl ude t he firs t 80 by te s of da t a ra m an d t w o i/o p i ns .
? 2010 microchip technology inc. ds39881d-page 217 pic24fj64 ga004 family 25 . 0 de ve l o pm en t s u p p o rt th e pic ? mi cro c o n tro lle rs a r e s upp orte d w i th a ful l ra nge of hard w are and so f t w a r e de ve lop m e n t t ool s: ? i n t eg rate d d e v e l opm en t env i ro nm en t - m plab ? ide sof t wa re ? a ss em bl e r s/ c o mp il er s / li n k e r s - m p asm tm as s e m b ler - m plab c 1 8 a nd mpl ab c 30 c c o m p il ers -m p l i n k tm o b j e c t li nk er/ mp l i b tm o b jec t li bra r ian - m plab a s m 3 0 as s e m b ler/ lin k e r /lib rary ? s i m u l at ors - m plab s i m s o f t wa re si m u lato r ?e m u l a t o r s - m plab i c e 20 00 i n -circ u i t em ula t or - m plab real ice? i n -circ u i t em ula t or ? i n - c i rc uit d ebu gg er - m plab i cd 2 ? d ev ic e progra m m e rs - p icst ar t ? plus d e v e l opm en t pro g ram m e r - m plab p m 3 dev i c e prog ram m e r - p ick i t? 2 de vel o p m e n t pro g ram m e r ? l ow -c os t d e m o n s tra t io n a nd d e ve lop m e n t bo ards an d ev al uat ion kit s 25. 1 m plab i n tegr ate d devel opment envi ronment sof t w a re th e m p lab id e s o f t w a r e b r ing s a n ea se of s o f t w a re de ve lop m e nt p r ev iou s l y un se en i n th e 8/1 6-b it m i c r o- c ont roll er m a rke t. th e mpl ab i d e i s a wi nd ow s ? op era t in g s y s t em -ba s e d ap pl ica t io n th at c o n t ai ns : ? a s i n gle gra phi ca l i nter f ac e to al l d ebu ggi ng tool s - s im ul a t or - p ro gram m e r (s ol d s e p a r ate l y ) - e m u l a tor (s o l d s e p a ra tel y ) - i n- c i r c u i t d e b u g g e r ( s o l d s epar a t el y ) ? a f u ll -fea ture d ed ito r wi th co lo r-co ded co nte x t ? a m u l t ip le proj ec t m ana ger ? c us tom i z a b l e dat a w i n dow s wi t h d i rec t e d it of c ont ent s ? h ig h-l e ve l so u r ce co de deb ugg ing ? v isu a l dev ic e i n i t ial i z e r f o r ea sy re gis t er in i t ia li z a t i on ? m ous e ove r v a ria b le in sp ec tion ? d rag an d d r op var i ab les fro m s o u r ce to w a tc h w i n dow s ? e x t en si ve on-l i n e he lp ? i nt e g r a t i o n of se l e c t t h ir d p a r t y t o ol s, su ch a s hi-t ec h so f t wa re c co m p i l e rs a n d iar c co m p i l e r s th e m p lab id e al low s y ou t o : ? e di t yo ur s o u r ce f i l e s ( e i t he r a sse mb l y o r c ) ? o ne tou c h as se mb le (o r c o m p il e) a nd dow n l oa d to pic m c u em ul ator and si mu lat o r to ol s (a utom at ic all y u pda tes al l p r oje c t inf o rm ati o n) ? d eb ug us ing : - s ou r c e f i l e s ( a sse mb l y o r c ) - m ix ed ass e m b l y a n d c - m ac hin e c o d e m p lab id e s u p port s mu lti p le d ebu ggi ng to ols i n a s i ng le dev el opm en t p a r adi gm , from th e co st -ef f ec tiv e s i m u la tors , t h rou gh low - c o s t i n -c irc u it de bug gers , to fu ll-f eat ured emu l a t ors . thi s el im ina t es the l e a r nin g c urv e w h en up gra din g t o tool s w i th i n cr eas ed fl exi bi lit y an d p ow er .
pic24fj64ga004 family ds39881d-page 218 ? 2010 microchip technology inc. 25. 2 m p a s m assembler th e mp asm as se mb ler is a full -fea ture d, un ive r sa l ma cr o as se mb l e r f o r a l l p i c mcus . th e m p asm as se mb ler g ene rates re loc a t abl e ob jec t fi le s fo r th e m p link o b jec t l i nk er , int e l ? s t an da rd h e x fi le s, m ap file s to det a i l m e m o ry us age a n d s y m b o l re fere nc e, a b s o lu te lst fil e s th at con t ai n sou r ce l i ne s a nd g ene rate d m a c h in e c ode and c o f f fil e s for d ebu ggi ng. th e m p asm as s e m b le r fea t ure s i n c l ud e: ? i n t eg rati on into m p lab id e proj ec t s ? u s e r-d efin ed ma cro s t o s t rea m l i ne as se mb l y co d e ? c o ndi tion al as se mb ly for m ul t i-p urpo s e s our ce fil e s ? d i r ect i v e s tha t al low c o m p l e te co ntro l o v er the a s s e m b ly pr oce s s 25. 3 m plab c18 and m p lab c30 c com p i l er s th e mpl ab c 1 8 a n d m p lab c 30 c ode de ve lop m e n t sy st em s are c o m p le te an si c c o m p i l ers for m i c r oc hip ? s pi c 1 8 a nd pic 2 4 fam i l i es o f m i cr oco n tro l - l e rs an d th e d s pic 3 0 a nd ds pic 33 fam i l y o f d i gi t a l si g- n al c ontro ll ers . t hes e co mp il ers pr ovi de p ow erfu l i n teg r ati o n c a p a b il iti e s , s upe rio r c ode o p tim i z a t i on an d e a se of us e n o t foun d w i t h ot her com p i l e r s. fo r e a sy s o u r ce lev e l de bug gi ng, the co mp il ers pro v id e s y m b o l info rm atio n tha t i s opt im iz ed to the m p lab id e d ebu gge r . 25. 4 m plink object l i nker / mplib object libr ari a n th e m p lin k o b je ct l i nk er c o m b in es re lo cat abl e o bje ct s c r eat ed by the mp asm ass em ble r an d th e mp l a b c 1 8 c c o mp il e r . it c a n l i n k r e lo ca tab l e ob j e c t s fro m pre c o m p ile d lib rari es , u s i ng di rect iv es fro m a l i nk er s c r ipt . th e m p lib o b je ct li bra r ian m a n a g e s th e cre a ti on an d m od i fic at i on of li brary fi le s o f p r ec om pil ed co de. whe n a ro utin e from a l i bra r y is c a l l ed fro m a so urce file , onl y th e m odu les tha t c ont a i n t hat routi n e w i ll b e li nk ed i n w i th the ap pli c a t io n. thi s all o w s la rge li bra r ies t o b e u s ed ef fic i e n tl y i n m a n y d i f f ere n t a ppl ic ati ons. th e o b je ct lin ke r/li brar y fe atu r es in clu d e : ? e f f ic ie nt l i n k i ng of s i n g le li bra r ies i n s t ead of m any s m a lle r fi les ? e n han ce d c ode m ain t ai nab ili ty by groupi ng re lat ed m od ule s toge the r ? f l e x i bl e c r ea tio n o f li brari e s wi th ea sy m odu le li st i n g, r e p l ac em en t , de l e t i on an d e x tr a c t i on 25. 5 m plab asm30 ass e m b l e r , l i nker and lib r ari a n m p lab asm 30 ass e m b l e r pro duc es re loc a t a bl e m a c h in e c o d e f r om s y m bol ic a s s e m b ly l ang uag e f o r ds pic 3 0f dev ic es . mpl ab c 3 0 c c o m p il er us es th e as s e m b le r to pro duc e it s ob jec t f ile . th e ass e m b l e r ge ne rate s rel o c a t a ble obj ec t fi les tha t ca n th en b e ar chi v e d or lin ke d w i th oth e r re loc a t a bl e ob jec t fi les an d a r c h iv es t o c r ea t e an e x e c u t ab l e f i l e. n o tab l e f e at u r es of the as se mb ler inc l u de: ? s u ppo rt fo r the en tire ds pic 30f in stru ct ion se t ? s u ppo rt fo r fix e d - poi nt a n d flo a ti ng-p o in t da t a ? c om m and li ne inte rfac e ? r ic h dire cti v e se t ? f l ex i bl e m ac r o l ang ua ge ? m plab i d e c o m p ati b il ity 25. 6 m plab si m sof t w a r e si mulat o r th e m p l ab si m sof t wa re sim u la tor al lows c o d e d e v e l o pm en t i n a p c - h o s t e d e n v ir o nm en t b y si mu l a t - i ng the pic m c u s an d ds pic ? d s c s on an i n s t ruct io n l e ve l. on an y g iv en i n s t ruc t io n, t he dat a are a s ca n b e ex am in ed o r mo difi ed a nd s t im ul i ca n be app lie d from a co mp rehe ns iv e s t im ulu s con t rol l e r . r e g i s t ers ca n b e l ogg ed to fi le s f o r fu rther run - time ana ly sis . t he trac e bu f f er and l ogi c ana ly ze r d i s pla y ex ten d t he po w er of th e s i m u la tor to rec o rd and trac k p r ogra m e x e c u t io n, ac ti ons o n i/o , mos t per iph e ral s an d i n te rna l r egi ste r s. th e m p l ab sim so f t ware si m u lat o r ful l y s u p p ort s s y m b o lic de bug gin g u s in g th e m p lab c 1 8 an d m p lab c 3 0 c c o m p ile rs, and the m p asm an d m p lab a s m3 0 as se mb lers . t he so f t w are si mu lat or of fe rs t he f l ex ib ili ty to d ev elo p a nd deb ug co de o ut s id e of th e h a rdw a re lab o rat o ry en vi ronm en t, m a k i n g i t a n ex c e ll ent , ec on om ica l s o f t w a re d e v e l opm en t too l .
? 2010 microchip technology inc. ds39881d-page 219 pic24fj64 ga004 family 25. 7 m plab i c e 2000 hi gh-per f or m a nc e in - c ir c u it e m ul a t o r th e mpl ab i c e 20 00 in -c irc u it em ula t or is i n te nde d to pro v i de the pro duc t d e v e lo pm ent en gin eer w i th a c o m p le te mi cro c o n tro lle r de si gn too l set fo r pic m i c r oc ont roll ers . sof t w a re c o n t rol of th e m p lab ic e 2 000 i n -c irc u i t emu l at or is adv an ced by t he m p lab in teg r ate d d e v e lo pm ent en vi ronm en t, w h i c h a llo w s e d iti n g , bu ild ing , do w n lo adi ng and so urc e de bug gin g fro m a s i ng le env iro n m ent . th e m p lab ic e 2 000 is a fu ll-f eatu r ed emu l a t or s y s t em w i th en han ce d trac e, tri gge r a nd da t a mo nit o r- i ng f eat ures . in terc ha nge abl e p r oc es sor mo dul es all o w th e s y s t em to be ea sil y reco nfi gur ed f o r em ul ati on of di ffe r e nt p r o c es so r s . t h e ar c h i t ec t u r e of t h e mp l a b ic e 200 0 in -c irc u i t em ula t or all o w s ex p a n s i on to s upp ort new pi c mi cro c o n tro lle rs. th e m p lab ic e 2 000 in-c ir cui t em ula t or s y s t em ha s b een de si gne d as a rea l -ti m e em ula t io n s y s t em w i th a d va nc ed fea t ure s t hat are ty pic a l l y fou nd on mo re e x pe ns iv e de ve lop m e nt t ool s. t he p c p l a t form an d m i c r os of t ? wi ndo w s ? 32 -bit o pera t in g sy st em w e re c hos en t o bes t m ake thes e fe atur es a v ai la ble i n a s i m ple , u nifi ed appli cat i on . 25. 8 m plab real ice in- c irc u it emulat or syst em mp lab r eal ic e in-c ircuit e m ulator sy stem is mic r ochip? s next generation high-spee d em ulator for m i crochip flas h d s c and mc u dev ices . it d ebugs and program s pic ? fla s h m c u s and ds p i c ? flash d s c s w i th the easy - to-us e , po w e rful graphic a l user interface of the mplab integ r ated d e velo pment environme n t (id e ), inc l uded w i th each kit. the mplab r e al ic e p r o be is conne cted to the de sign eng ineer ? s p c using a high-s peed u sb 2.0 interface and is connec ted to the t a rget w i th either a c onnector com p atible w i th the popu lar mplab ic d 2 sys tem (r j1 1) or w i th the new high-s peed, n o ise tolerant, low - v o lt ag e d i f f erenti a l sig nal ( l vd s) interconne ction (ca t 5). m p lab r e al ic e is fiel d u pgradeable through future firmw a re dow nloads in mplab id e. in upcom ing releas es of mplab id e, new devic es w ill be supported, and n ew features w ill b e added, suc h as sof t w are break- poi nt s and a ssem b ly c ode trace. m p l a b r eal ic e of fer s signi f i cant adv ant ages ov er comp etitive em ulators inc l uding low - c ost, full - s peed e m ulation, r e al-time variab le w atches, trac e analy s is, c omplex breakpoi nt s, a rugged ized pr o be interfac e and long ( u p to three meters) interc onnection cables . 25. 9 m plab i cd 2 in- c ir cuit debu gger mi crochip? s in-c ircuit d ebugger , m p l a b ic d 2 , is a pow erful, low - cos t , r u n-t i me dev elopm ent tool, conn ecting to the hos t p c via an r s -232 or high - s peed u s b interfac e. thi s tool is base d on the flas h p i c mc u s and c an be use d t o develop for thes e and other pic mc u s and dspic d s c s . the mplab ic d 2 u t il iz es th e i n -c ircu it de bug gin g c a p a bi li ty bui lt into th e f l a s h de vi ce s. th is fe atu r e, al ong w i th m i cro c h i p? s i n -c i r c u i t serial program ming tm (ics p tm ) protoco l , of fers cost- ef f e ctive, in-ci r c uit flash debu gging from the g r ap h i c al us er i n te rfac e o f the mpl ab inte grat ed d e vel o p m e n t en vir onm en t. thi s en abl es a des ig ner to dev elo p an d de bu g sou r ce c o d e by s e tti ng bre a k poi nt s , si ngl e ste p - pi ng a nd w atc hi ng va ria ble s, an d c p u s t atu s an d pe rip hera l re gi ste r s. r unn ing at ful l s p e ed e n a b le s te st ing har d w a r e and ap pli c at io ns in re al t i m e. m p lab ic d 2 a l s o s e rv es a s a de ve lop m e n t programm e r f o r s ele ct ed pi c dev ic es . 25. 10 mplab pm3 dev i ce progr a m m er th e m p lab p m 3 d e vi ce prog ram m e r is a uni ve rsa l , c e c o m p li ant d e v i c e pro g ra mm er w i t h pro g ram m a bl e v olt age ve rifi cat i on at v ddm i n an d v dd m a x fo r m a x i m u m reli ab ili ty . it feat ures a l a rg e lc d d i sp la y (1 28 x 64 ) for men u s an d erro r m e ss ag es and a m o d u - l a r , de t a c hab le s o c k et a s s e m b ly to su ppo r t v a ri ou s p ack ag e ty pe s. t he ic sp? c abl e as s em bly is in cl ude d as a st and ard item . i n s t an d-al one mo de , the m p lab pm 3 d e v i c e prog ram m e r ca n rea d , v e rif y an d pro g ram pic de vi ces w i tho u t a pc c o n nec tio n . it ca n als o s e t c ode p r ote c ti on in thi s mo de . th e mpl ab pm 3 c onn ec t s to the ho st pc v i a an r s -2 32 or u sb ca bl e. th e m p lab pm 3 h as hi gh-s pe ed co mm un ica t io ns an d op tim i z e d al gor ithm s for qu ic k p r og ram m i ng of larg e m e m o ry dev ic es an d in co rpora t es an sd /m mc c a rd f o r fi le sto r age an d s ec ure dat a ap pl ica t io ns .
pic24fj64ga004 family ds39881d-page 220 ? 2010 microchip technology inc. 25. 1 1 pi cst art plus devel opm en t pr ogramm e r t he p i c s t a r t p l us d ev el o pm en t p r og r am m e r is an e a sy -to - us e, low - c o s t, prot oty pe pro g ram m e r . it c onn ec t s to th e pc v i a a c o m (rs-232 ) p o rt. m p lab i n t e gr a t ed d e v e lo pm en t e n v i r o nm e n t so f t w a r e m a k e s u s i ng th e prog ram m e r si mp le an d ef fic i e n t. th e p i c s t a r t p l us d e v e l o pm en t p r og r a m m e r su pp o r t s mo st p i c d e v i c e s i n d i p pac ka ge s up t o 4 0 pi n s . l a r g e r p i n co unt d e vi ce s, su ch a s the p i c 1 6c 92 x an d pic 1 7c 76 x, m a y be sup por ted w i th a n a dap ter s o c k e t . th e pic s t a r t plu s d e v e lo pm ent pro g ram m e r is c e co mp l i a n t . 25. 12 pi ckit 2 devel opm en t p r ogrammer t h e p i c k i t ? 2 d e v e l o pm en t p r og r a mme r i s a l o w - c o st p r ogra m m e r a nd s e le cte d fl ash dev ic e de bug ger w i th a n ea sy -to-u s e int e rfac e f o r pro g ram m i ng ma ny of m i c r oc hip ? s b as eli ne, mi d-ra nge and pic 1 8f fa mi li es o f fl as h m e m o ry mi cro c on trol ler s . th e pic k it 2 s t arte r kit i n c l ud es a pro t oty p i ng d e v e lo pm ent boa rd, t w elv e s equ en tial l e s s o n s , s o f t w a re an d h i -tec h ? s pic c ? l i te c co mp ile r , a nd is des ig ned to hel p g e t up t o s pee d q u ic kl y u s in g p i c ? mi c r oc on t r ol l e r s . th e ki t pr o v i d es e v er yth i ng ne ede d t o p r ogra m , ev al uate an d d ev elo p a ppl ic ati ons us in g m i c r oc hip ? s po w e rfu l , m i d- rang e fl as h m e m o ry fa mi ly of m i c r oc on trol lers . 25. 13 demonstr ati on, devel opment and eval uati on boards a w i de v a ri et y of d e m o ns tra t i on, de v e l opm e n t an d ev al ua ti on bo ar d s f o r va r i o u s p i c mc u s a n d dsp i c d s c s al lo w s q u i c k ap pl ic at io n de ve lo pm e n t o n fu ll y fu nc - ti on al s y s t e m s . mo st b o a r ds in cl ud e pro t o t y p i n g a r ea s fo r ad di ng c us t o m c i r c u i t r y an d pr o v id e ap pl ic at io n f i r m w a re an d so ur c e co de f o r e x am in at io n a n d m o d i f i c a t i on . th e b oard s su ppo rt a v a rie t y of fea t ures , i n c l ud ing led s , te mp eratu r e se ns ors , sw itc he s , s pea ke rs, r s -23 2 in terfa c e s , lc d dis p la ys , pote n ti ome t ers a nd ad diti ona l eeprom m e m o ry . th e de mo ns trati o n and dev el opm en t bo ards c an b e us ed i n tea c h i ng env iro nm ent s, for p r oto t yp ing c us t om c i rc uit s an d for le arn i ng a bou t va riou s m i c r oc ontr o ll er ap pl ic atio ns . in addi tio n to the pi c d e m ? a nd d s pi c d e m ? d e mon- str a t i on/ dev elop ment bo ard ser i es of cir c ui t s , micr ochi p has a l i ne of eval uat ion ki t s and d e mon s tr ati on softw ar e fo r ana log f ilt er de sign , k ee l oq ? se cu r i t y i c s, ca n , irda ? , p ow er s mar t b att er y ma nage ment , s e e v al ? ev al uat ion s y s t em , s i g m a - d e l t a a d c , fl o w ra te s ensin g, plu s man y mo re. c h e c k th e m i c r oc hip w e b p a ge (w w w .mi c ro ch ip.c om ) fo r th e c o m p le te l i s t o f de mo ns trati on, de vel o p m e n t an d e v a l ua tio n k i t s .
? 2010 microchip technology inc. ds39881d-page 221 pic24fj64 ga004 family 2 6 .0 ins t r uction s e t s u m m ary th e pic 24 f ins t ruc t i on se t add s ma ny e nha nc em ent s to the pre v io us pic ? m cu in st r u ct i o n se ts, wh il e ma in - t a in ing a n ea sy m i g r ati on fro m pr evi o u s pic mc u in st r u ct i o n se t s . m o s t i n s t r u ct i o ns a r e a si n g l e p r og r a m m e m o ry w o rd . o n ly thr ee i n s t ruc t io ns requ ire tw o pr o g r am m e m o ry lo ca t i on s. ea ch si ngl e-w o rd in st ruct ion is a 24-b i t w o rd d i v i de d i n to an 8 - bit op co de, w h i c h s pec ifi e s th e i n s t ruc t io n ty pe an d o ne or mor e o pera nds, w h ic h f u rthe r s pecif y t h e op e r at i o n of t h e i n s t r u c t i o n. t h e i n s t r u ct i o n se t is h i gh ly o r tho gon al a nd i s gro u p ed in to fo ur ba si c ca t e g o r ie s: ? w ord or b y te -ori ent ed o p e r ati ons ? b i t -ori ent ed o p e r atio ns ? l iter al o p e r atio ns ? c on trol op erat ion s t abl e 2 6-1 sh ow s the gen era l s y m b o l s us ed i n de s c r i bi ng t h e in s t r u ct i o n s . t h e p i c 2 4f i n s t r u ct i o n se t s u m m a r y in t a b l e 26-2 li st s a ll the ins t ru cti ons , a l on g w i th th e s t at us fla g s af fect ed by ea ch inst ruct i on. m o s t wo rd or by te-o rien ted w reg i s ter in s tru c t ion s (i nc lud i ng barr e l s h i f t in struct ion s ) h a ve thre e o pera nds : ? t h e f i rs t sourc e o pera nd w hic h i s t y p i ca ll y a re gis t er ?wb ? wi thou t a n y add res s m o d i fi er ? t he se co nd so u r ce op er a n d wh i c h i s t y pi ca l l y a re gis t er ?ws ? wi th o r wi t hou t an ad dres s mo difi er ? t h e d e s t in atio n o f th e re sul t wh i c h is ty pic a l l y a re gis t er ?wd ? wi th o r wi th out an add res s m o d i fi er ho w e v e r , word o r b y te -ori ente d fil e reg i s t er in s t ru c t ion s h a ve tw o ope rand s: ? t h e f ile reg i s t er s p e c if ied by th e v a lu e ? f ? ? t h e d e s t in atio n, w h ic h c oul d e i th er b e th e file re gis t er ? f ? or t he w 0 reg i s t er , wh ic h is de not ed a s ?w r e g? m o s t bi t-ori e n t ed inst ruct i ons (in c l udi ng sim p l e ro t a te /s h i f t in s tru c ti ons ) h a v e two ope ran d s : ? t h e w reg i s t er (w i t h o r wi th out an add res s m o d i fie r) or fil e re gis t er (sp e c i fie d b y t he v a l ue of ? w s? or ?f ?) ? t he bi t in th e w r e gi st e r or f i le r e g i s t er (s pe cif i ed by a lite r al va lue or ind i rec t l y b y t he c ont ent s o f reg i s t er ?wb ? ) th e li tera l in str u ct ion s th at i n vo lv e da t a m o v e m e nt ma y us e som e of t he f oll ow in g o pera nds : ? a l i te ral v a l ue to b e lo ad ed i n to a w regi st er or fil e re gis t er (sp e ci fie d b y t he v a l ue of ?k ? ) ? t h e w reg i st er o r fil e re gis t er where the li tera l v a lu e i s t o be lo ade d (s pe ci fied by ?w b? or ? f ? ) h o w e v e r , l i t e r a l i n st r u c t io n s t h at i n vo lv e ar i t hm et i c o r l ogi ca l o per atio ns u s e s om e o f the fol l o w ing op era nds : ? t h e fi rst so urc e o perand w h ic h i s a reg i s t er ? w b? w i th o u t a n y ad dr e s s mo di f i er ? t h e s e c ond s ourc e o per and wh ic h i s a l i teral va l u e ? t he de st i n at i o n of t h e r e su lt ( o nl y i f n o t t h e sa m e as th e fi rst so urc e o pera nd) w hic h i s t y p i ca ll y a re gis t er ?wd ? wi t h o r wi th out an add res s m o d i fi er th e con t rol i n s t ruc t io ns m a y us e so me of th e f oll ow in g op era nds: ? a p r ogr am me mo ry a ddr ess ? t he mo de o f t h e ta bl e r e ad a n d t a b l e wr it e in s t r u ct i o ns al l i n st ruc t io ns are a s i n g le w o rd , e x c ept for ce rt ai n do ub le-w o r d ins t ruc t i ons , w h ic h w e re ma de do u- bl e-w o rd i n st ruc t ion s so tha t al l th e re qui r ed inf o rm a- ti on is av ail a b l e i n t hes e 48 b i t s . i n th e s e c ond w o rd , th e 8m s b s a r e ? 0 ? s . i f t h i s se co nd w o r d i s ex ec ut e d as an i nst ruc t ion (by i t se lf), it w i ll exe c u t e a s a nop . m os t si ngl e-w or d in stru cti on s are ex ec uted in a si ngl e i n st ruc t ion c y c l e , un le ss a co ndi tio nal te st is tru e o r th e pr ogra m cou n te r is c han ged as a resu lt of t he inst ruc- ti on. in th es e ca se s, the e x e c u t ion t ak es tw o i ns t ruc t io n c y c l e s , w i th t he ad dit i on al in stru ct ion c y c l e ( s) ex ec ute d as a nop . n o t a b l e ex ce pti ons are the br a (u nc ond i - ti ona l/c o m p u t ed bran ch ), i ndi rec t call/got o , al l t abl e re ads a nd w r ite s , an d re turn/retfie ins t ru cti o ns , w h i c h a r e s i n g le -w ord in stru ct ion s but t a ke tw o or thre e cy cl es . c e r t a i n i n s t r u c t i o ns th a t i n vo lv e s k i p p i ng ov e r t h e s u b - s equ ent in st ruc t ion re qui re either tw o or t h ree c y c l e s if th e s k i p is per form ed, dep end in g on w h eth e r th e i n st ruc t ion bei ng s k i pp ed i s a s i n g le -w ord or tw o-w o rd i n st ruc t ion . m o re ov er , do ubl e-w o rd m o v e s re qui re tw o c y c l e s . the do ubl e-w o rd in str u ct ion s exe c u t e in tw o in s t r u ct i o n cy cl e s . note : th is c hap ter is a b r ie f s u m m a r y o f th e pic 2 4f ins t ruc t i on s e t arc h it ec ture , an d i s n ot i nte nde d t o b e a c omp reh ens iv e reference source.
pic24fj64ga004 family ds39881d-page 222 ? 2010 microchip technology inc. t a ble 2 6 -1: s y m bols us ed i n opcode de scri ptions f i el d d escri p ti o n #t ex t m eans lit eral def ined by ? text ? (t e xt ) m eans ?co n t ent of text ? [ t ext ] m eans ?t he loca t i on ad dresse d by text ? { } o pt ional f i e l d or operat i o n r egi s t er bit f i eld . b b yt e m ode select i o n . d d ouble-w o rd m ode s e lect ion . s s hadow regist er s e lect . w w o rd mo de se l e c t ion (def au l t ) bit 4 4 - bit bi t s e lect i on f i eld (used in wor d addre ssed inst r u ct i ons ) ?? {0 .. .1 5 } c, dc, n, o v , z m cu s t at us bit s : carry , digit carry , negat ive, o v erf l ow , s t i c ky z e ro ex pr a b solut e addr ess, label or ex press i on (res o lved by t he l i nk er) f f ile r egi s t er addres s ?? { 0000h. . . 1f f f h} li t 1 1 - bit unsigned l i t e ral ?? {0 , 1 } li t 4 4 - bit unsigned l i t e ral ?? { 0 .. .1 5 } li t 5 5 - bit unsigned l i t e ral ?? { 0 .. .3 1 } li t 8 8 - bit unsigned l i t e ral ?? { 0. . . 255} li t 1 0 1 0-bit unsigned l i t e ral ?? { 0 . . . 255} f o r byt e m ode, { 0 : 1023} f o r w o rd mode li t 1 4 1 4-bit unsigned l i t e ral ?? { 0. . . 1638 4} li t 1 6 1 6-bit unsigned l i t e ral ?? { 0. . . 6553 5} li t 2 3 2 3-bit unsigned l i t e ral ?? { 0 . . . 8388 608} ; lsb m u st be ? 0 ? none f i eld doe s not require an ent ry , m a y be blank pc p r ogram c ount er slit 10 1 0 -bit signed lit eral ?? { - 512. . . 51 1} slit 16 1 6 -bit signed lit eral ?? { - 32768. . . 32767} slit 6 6 -bit signed lit eral ?? { - 16. . . 16 } wb ba se w r e g i st e r ?? { w 0. . w 15} w d d e st inat ion w regist er ?? { wd , [wd ] , [wd ++] , [wd - - ] , [ ++wd ] , [ - - w d ] } w d o d est i nat ion w regist er ?? { w nd, [ w nd] , [ w nd++] , [ w nd--] , [ ++w nd] , [ - - w nd] , [ w nd+w b ] } w m , w n d i v i d end, divisor working r egist er p a ir (dire ct addres sing) w n o ne of 16 working regist ers ?? { w 0. . w 15} w n d o ne of 16 dest i nat ion w o rking r egist er s ?? { w 0. . w 15} w n s o ne of 16 sourc e work ing reg i s t ers ?? { w 0. . w 15} w r eg w 0 (work i ng reg i s t er used in f i l e regist er i n s t ru ct ions ) w s s ourc e w regist er ?? { w s, [ w s] , [w s+ + ] , [w s - - ] , [+ + w s] , [-- w s ] } w so s ourc e w regist er ?? { wn s, [wn s], [ w n s ++ ], [w n s - - ], [ ++wn s], [ - - w n s], [ w n s+wb ] }
? 2010 microchip technology inc. ds39881d-page 223 pic24fj64 ga004 family t able 2 6 -2: i ns truction s e t ov erv i e w a s sem b l y mn em on ic a s sem b l y s y nt ax d esc r i pti o n # o f wo r d s # o f c ycl es s t at us fl ag s a f f ect ed add add f f = f + w r e g 1 1 c, dc, n, ov , z add f,wre g w r e g = f + w r e g 1 1 c, dc, n, ov , z add #lit1 0,wn wd = lit1 0 + wd 1 1 c, dc, n, ov , z add wb,ws ,wd w d = wb + ws 1 1 c, dc, n, ov , z add wb,#l it5,wd w d = w b + lit5 1 1 c , dc, n, ov , z addc addc f f = f + w r e g + ( c ) 1 1 c , dc, n, ov , z addc f,wre g w r e g = f + w r e g + ( c ) 1 1 c , dc, n, ov , z addc #lit1 0,wn w d = lit1 0 + w d + ( c ) 1 1 c , dc, n, ov , z addc wb,ws ,wd w d = w b + w s + ( c ) 1 1 c , dc, n, ov , z addc wb,#l it5,wd w d = wb + lit5 + (c) 1 1 c , dc, n, ov , z and and f f = f . a n d . w r e g 1 1 n, z and f,wre g w r e g = f . a n d . w r e g 1 1 n, z and #lit1 0,wn wd = lit1 0 .and. wd 1 1 n, z and wb,ws ,wd wd = wb . a nd. ws 1 1 n, z and wb,#l it5,wd w d = wb .a nd. lit5 1 1 n , z asr asr f f = ar ith m e t ic rig h t sh ift f 1 1 c , n, o v , z asr f,wre g w r e g = a r ith m e t ic righ t s h ift f 1 1 c , n, o v , z asr ws,wd wd = ar it h m e t ic rig h t sh if t ws 1 1 c, n, o v , z asr wb,wn s,wnd w n d = a r i t hm eti c r i ght s h i f t w b b y w n s 1 1 n , z asr wb,#l it5,wnd wn d = a r ith m e t ic rig h t sh if t wb b y lit5 1 1 n , z bclr bclr f,#bi t4 b i t c l ear f 1 1 n one bclr ws,#b it4 b i t c l ear w s 1 1 n one bra bra c,exp r b r anc h i f c arr y 1 1 ( 2) n one bra ge,ex pr b r anc h i f g r e a te r th an or e q ua l 1 1 ( 2 ) n one bra geu,e xpr b r anc h i f u n si gn ed gre a te r th an or e qua l 1 1 ( 2 ) n one bra gt,ex pr b r anc h i f g r e a te r th an 1 1 ( 2 ) n one bra gtu,e xpr b r anc h i f u n si gn ed gre a te r th an 1 1 ( 2 ) n one bra le,ex pr b r anc h i f l e ss tha n o r e q u a l 1 1 ( 2 ) n one bra leu,e xpr b r anc h i f u n si gn ed les s tha n o r e q ual 1 1 ( 2 ) n one bra lt,ex pr b r anc h i f l e ss tha n 1 1 ( 2 ) n one bra ltu,e xpr b r anc h i f u n si gn ed les s tha n 1 1 ( 2 ) n one bra n,exp r b r anc h i f n ega ti ve 1 1 ( 2 ) n one bra nc,ex pr b r anc h i f n o t c a rr y 1 1 ( 2 ) n one bra nn,ex pr b r anc h i f n o t n e gat i ve 1 1 ( 2 ) n one bra nov,e xpr b r anc h i f n o t o ver fl ow 1 1 ( 2 ) n one bra nz,ex pr b r anc h i f n o t z e r o 1 1 ( 2 ) n one bra ov,ex pr b r anc h i f o ver fl ow 1 1 ( 2 ) n one bra expr b r anc h u n cond i t i o n a l l y 1 2 n one bra z,exp r b r anc h i f z e r o 1 1 ( 2 ) n one bra wn c o mp ute d b r anch 1 2 n one bset bset f,#bi t4 b i t s e t f 1 1 n one bset ws,#b it4 b i t s e t w s 1 1 none bsw bsw.c ws,wb w r i t e c bi t t o w s< w b > 1 1 n one bsw.z ws,wb w r i t e z b i t to w s< w b> 1 1 n one btg btg f,#bi t4 b i t t o g g le f 1 1 n one btg ws,#b it4 b i t t o g g le w s 1 1 none btsc btsc f,#bi t4 bit t e st f, skip if cle a r 1 1 (2 or 3) n one btsc ws,#b it4 bit t e st ws, skip if cle a r 1 1 (2 or 3) n one
pic24fj64ga004 family ds39881d-page 224 ? 2010 microchip technology inc. btss btss f,#bi t4 b i t t e st f, s kip if s e t 1 1 (2 or 3) n one btss ws,#b it4 bit t e st ws , sk ip if se t 1 1 (2 or 3) n one btst btst f,#bi t4 bit t e st f 1 1 z btst.c ws,#b it4 b i t t e st w s to c 1 1 c btst.z ws,#b it4 b i t t e st w s to z 1 1 z btst.c ws,wb b i t t e st w s to c 1 1 c btst.z ws,wb b i t t e st w s to z 1 1 z btsts btsts f,#bi t4 b i t t e st the n s e t f 1 1 z btsts.c ws,#b it4 b i t t e st w s to c, th en s e t 1 1 c btsts.z ws,#b it4 b i t t e st w s to z , the n s e t 1 1 z call call lit23 c a l l s u b r ou ti ne 2 2 n one call wn c a l l in di re ct s u b r ou ti ne 1 2 n one clr clr f f = 0x 000 0 1 1 n one clr wreg w r e g = 0x 000 0 1 1 n one clr ws w s = 0x0 0 0 0 1 1 n one clrwd t clrwdt c l e a r w a tch dog t i m e r 1 1 w dt o, s l eep com com f f = f 11 n , z com f ,wre g wreg = f 11 n , z com ws,wd wd = ws 11 n , z cp cp f c o m p a r e f with wreg 1 1 c, dc, n, ov , z cp wb,#l it5 c o m p a r e wb with li t 5 1 1 c, dc, n, ov , z cp wb,ws c o mpar e w b w i t h w s (w b ? w s ) 1 1 c , d c , n , ov , z cp0 cp0 f c o mpar e f w i t h 0 x 00 00 1 1 c , d c , n , ov , z cp0 ws c o mpar e w s w i t h 0 x00 00 1 1 c , dc , n , ov , z cpb cpb f c o m p a r e f with wreg , with bo r r o w 1 1 c , dc, n, ov , z cpb wb,#l it5 c o m p a r e wb with li t 5 , wit h bo r r o w 1 1 c, dc, n, ov , z cpb wb,ws c o mpar e w b wi t h w s, w i t h b o rr ow (w b ? w s ? c ) 1 1 c, dc, n, ov , z cpseq cpseq wb,wn c o mpar e w b w i t h w n , s k i p i f = 1 1 (2 or 3) n one cpsgt cpsgt wb,wn c o mpar e w b wi t h w n , s ki p if > 1 1 (2 or 3) n one cpslt cpslt wb,wn c o mpar e w b wi t h w n , s ki p if < 1 1 (2 or 3) n one cpsne cpsne wb,wn c o mpar e w b wi t h w n , s ki p if ? 11 (2 or 3) n one daw daw wn wn = de cim a l ad ju st wn 1 1 c dec dec f f = f ? 1 1 1 c, dc, n, ov , z dec f,wre g w r e g = f ? 1 1 1 c, dc, n, ov , z dec ws,wd w d = w s ? 1 1 1 c , dc, n, ov , z dec2 dec2 f f = f ? 2 1 1 c , dc, n, ov , z dec2 f,wre g w r e g = f ? 2 1 1 c , dc, n, ov , z dec2 ws,wd w d = w s ? 2 1 1 c , dc, n, ov , z disi disi #lit1 4 d i s abl e int e rr up t s fo r k inst ruct i on c ycl es 1 1 n one div div.sw wm,wn s i g ned 16 /16 - bi t int ege r d i vi d e 1 18 n , z , c, o v div.sd wm,wn s i g ned 32 /16 - bi t int ege r d i vi d e 1 18 n , z , c, o v div.uw wm,wn u n si gn ed 16/ 16- bi t i n te ger di vi d e 1 18 n , z , c, o v div.ud wm,wn u n si gn ed 32/ 16- bi t i n te ger di vi d e 1 18 n , z , c, o v exch exch wns,w nd s w a p w n s w i t h w nd 1 1 n one ff1l ff1l ws,wn d f i nd f i r st o ne fro m l e f t (m s b ) s i d e 1 1 c ff1r ff1r ws,wn d f i nd f i r st o ne fro m ri g ht ( l s b ) s i de 1 1 c t a ble 2 6 -2: i ns truction s e t ov erv i e w (continue d) as s e m b ly mn em on ic a s sem b l y s y nt ax d esc r i pti o n # o f wo r d s # o f c ycl es s t at us fl ag s a f f ect ed
? 2010 microchip technology inc. ds39881d-page 225 pic24fj64 ga004 family goto goto expr go to a d dr es s 2 2 n o n e goto wn g o t o in di re ct 1 2 n one inc inc f f = f + 1 1 1 c , dc, n, ov , z inc f,wre g w r e g = f + 1 1 1 c , dc, n, ov , z inc ws,wd w d = w s + 1 1 1 c , dc, n, ov , z inc2 inc2 f f = f + 2 1 1 c , dc, n, ov , z inc2 f,wre g w r e g = f + 2 1 1 c , dc, n, ov , z inc2 ws,wd w d = w s + 2 1 1 c , dc, n, ov , z ior ior f f = f . ior. w r e g 1 1 n, z ior f,wre g w r e g = f . ior. w r e g 1 1 n, z ior #lit1 0,wn w d = lit1 0 .i or. w d 1 1 n, z ior wb,ws ,wd w d = w b .ior . w s 1 1 n, z ior wb,#l it5,wd w d = w b .ior . lit5 1 1 n , z lnk lnk #lit1 4 li n k fr am e p o i n te r 1 1 n o n e lsr lsr f f = l o g i ca l rig h t sh if t f 1 1 c , n, o v , z lsr f,wre g wr e g = l o g i ca l rig h t sh if t f 1 1 c , n, o v , z lsr ws,wd wd = l o g i ca l rig h t sh ift ws 1 1 c, n, o v , z lsr wb,wn s,wnd w n d = log i cal ri g ht s h i f t w b by w n s 1 1 n , z lsr wb,#l it5,wnd w n d = log i cal ri g ht s h i f t w b by l i t 5 1 1 n , z mov mov f,wn m o ve f t o w n 1 1 none mov [wns+ slit10],wnd m o ve [w n s+s li t 10] to w n d 1 1 n one mov f m o ve f t o f 1 1 n , z mov f,wre g m o ve f t o w r e g 1 1 n, z mov #lit1 6,wn m o ve 16 -b it lite ra l to w n 1 1 none mov.b #lit8 ,wn m o ve 8- bi t li ter a l t o w n 1 1 n one mov wn,f m o ve w n to f 1 1 n one mov wns,[ wns+slit10] m o ve w n s to [ w ns+s lit10 ] 1 1 mov wso,w do m o ve ws t o wd 1 1 no n e mov wreg, f m o ve w r e g t o f 1 1 n , z mov.d wns,w d m o ve dou b le fro m w ( ns) : w ( n s+1) to w d 1 2 none mov.d ws,wn d m o ve dou b le fro m w s to w ( nd +1): w ( nd ) 1 2 none mul mul.ss wb,ws ,wnd { w nd + 1 , w n d} = s i gn ed( w b ) * s i g ned (w s) 1 1 n one mul.su wb,ws ,wnd { w nd + 1 , w n d} = s i gn ed( w b ) * u n si gn ed (w s) 1 1 n one mul.us wb,ws ,wnd { w nd + 1 , w n d} = un s i gne d(w b ) * s i gn ed (w s) 1 1 n one mul.uu wb,ws ,wnd {wnd + 1, w nd} = u ns i gned( w b) * u nsi gn ed(w s) 1 1 n one mul.su wb,#l it5,wnd { w nd + 1 , w n d} = s i gn ed( w b ) * u n si gn ed (l i t 5) 1 1 n one mul.uu wb,#l it5,wnd { w nd + 1 , w n d } = u n si gn ed( w b ) * u n si gn ed (l i t 5) 1 1 n one mul f w 3 :w 2 = f * w r e g 1 1 n one neg neg f f = f + 1 1 1 c , dc, n, ov , z neg f,wreg wreg = f + 1 1 1 c , dc, n, ov , z neg ws,wd wd = ws + 1 1 1 c , dc, n, ov , z nop nop n o op er ati o n 1 1 n one nopr n o op er ati o n 1 1 n one pop pop f p o p f fro m t o p- of- s t a c k (tos ) 1 1 n one pop wdo p o p fr om t o p - o f -s tack ( t o s ) to w d o 1 1 n one pop.d wnd p o p fr om t o p-o f -s tack (t o s ) to w ( n d ) : w ( nd + 1 ) 1 2 n one pop.s p o p s h ado w r e g i ster s 1 1 a l l push push f p u sh f to t op- of- s t a ck (tos ) 1 1 n one push wso p u sh w s o to t o p - of -s tack ( t o s ) 1 1 n one push.d wns p u sh w ( ns) : w ( n s + 1 ) to t op- of- s t a ck (tos ) 1 2 n one push.s p u sh s hadow registers 1 1 none t able 2 6 -2: i ns truction s e t ov erv i e w (continue d) a s sem b l y mn em on ic a s sem b l y s y nt ax d esc r i pti o n # o f wo r d s # o f c ycl es s t at us fl ag s a f f ect ed
pic24fj64ga004 family ds39881d-page 226 ? 2010 microchip technology inc. pwrsa v pwrsav #lit1 g o i n to s l e ep or idl e mod e 1 1 w d t o , s l eep rcall rcall expr r e la tive ca ll 1 2 no n e rcall wn c o m p u t e d ca ll 1 2 no n e repea t repeat #lit1 4 r epe at n e xt i n str u cti o n l i t 1 4 + 1 ti m e s 1 1 n one repeat wn r epe at n e xt i n str u cti o n ( w n) + 1 t i m e s 1 1 n one reset reset so f t wa r e de vice re se t 1 1 no n e retfi e retfie r e tur n f r om in ter r up t 1 3 ( 2 ) n one retlw retlw #lit1 0,wn r e tu r n wit h l i t e r a l in wn 1 3 ( 2 ) n o n e retur n return r e tur n f r om s u b r ou ti ne 1 3 ( 2 ) n one rlc rlc f f = rotate le f t thro ug h ca rry f 1 1 c , n, z rlc f,wre g w r e g = rotate le f t thro ug h ca rry f 1 1 c , n, z rlc ws,wd wd = ro t a t e l e f t th r o u g h ca r r y ws 1 1 c, n, z rlnc rlnc f f = rotate le f t (no carr y) f 1 1 n , z rlnc f,wre g w r e g = rotate le f t (no carr y) f 1 1 n , z rlnc ws,wd wd = ro t a t e l e f t ( n o ca r r y) ws 1 1 n, z rrc rrc f f = rotate righ t th rou g h car r y f 1 1 c , n, z rrc f,wre g w r e g = rotate righ t th rou g h car r y f 1 1 c , n, z rrc ws,wd wd = ro t a t e rig h t th r o u g h ca r r y w s 1 1 c, n, z rrnc rrnc f f = rotate righ t ( n o ca rry) f 1 1 n , z rrnc f,wre g w r e g = rotate righ t ( n o ca rry) f 1 1 n , z rrnc ws,wd wd = ro t a t e rig h t ( n o ca r r y) ws 1 1 n, z se se ws,wn d w n d = s i g n - e x t end ed w s 1 1 c , n, z setm setm f f = f f f f h 1 1 n one setm wreg w r e g = ff ff h 1 1 n o n e setm ws w s = ff ff h 1 1 n o n e sl sl f f = le f t s h if t f 1 1 c , n, o v , z sl f,wre g w r e g = le f t s h if t f 1 1 c , n, o v , z sl ws,wd w d = l e f t s h if t w s 1 1 c, n, o v , z sl wb,wn s,wnd w n d = left s h ift w b by w n s 1 1 n , z sl wb,#l it5,wnd w n d = left s h ift w b by lit5 1 1 n , z sub sub f f = f ? w r e g 1 1 c, dc, n, ov , z sub f,wre g w r e g = f ? w r e g 1 1 c, dc, n, ov , z sub #lit1 0,wn wn = wn ? lit1 0 1 1 c, dc, n, ov , z sub wb,ws ,wd w d = w b ? w s 1 1 c, dc, n, ov , z sub wb,#l it5,wd w d = w b ? lit5 1 1 c , dc, n, ov , z subb subb f f = f ? w r e g ? ( c ) 1 1 c , dc, n, ov , z subb f,wre g wr e g = f ? wreg ? ( c ) 1 1 c , dc, n, ov , z subb #lit1 0,wn wn = wn ? lit 1 0 ? ( c ) 1 1 c , dc, n, ov , z subb wb,ws,wd wd = wb ? ws ? (c ) 1 1 c , dc, n, ov , z subb wb,#l it5,wd wd = wb ? lit 5 ? ( c ) 1 1 c , dc, n, ov , z subr subr f f = w r e g ? f 1 1 c , dc, n, ov , z subr f,wre g w r e g = w r e g ? f 1 1 c , dc, n, ov , z subr wb,ws ,wd wd = ws ? wb 1 1 c, dc, n, ov , z subr wb,#l it5,wd wd = lit5 ? wb 1 1 c, dc, n, ov , z subbr subbr f f = w r e g ? f ? (c ) 1 1 c , dc, n, ov , z subbr f ,wre g wr e g = wreg ? f ? ( c ) 1 1 c , dc, n, ov , z subbr wb,ws ,wd wd = ws ? wb ? ( c ) 1 1 c , dc, n, ov , z subbr wb,#l it5,wd wd = lit 5 ? wb ? ( c ) 1 1 c , dc, n, ov , z swap swap.b wn w n = n i b bl e s w ap w n 1 1 n one swap wn w n = b y te s w ap w n 1 1 none tblrd h tblrdh w s,wd r ead p r og < 2 3 : 16 > to w d < 7 :0 > 1 2 n one t a ble 2 6 -2: i ns truction s e t ov erv i e w (continue d) as s e m b ly mn em on ic a s sem b l y s y nt ax d esc r i pti o n # o f wo r d s # o f c ycl es s t at us fl ag s a f f ect ed
? 2010 microchip technology inc. ds39881d-page 227 pic24fj64 ga004 family tblrd l tblrdl ws,wd r ead p r og < 1 5 : 0> t o w d 1 2 n one tblwt h tblwth ws,wd w r i t e w s < 7 :0 > to p r og < 23:1 6 > 1 2 n one tblwt l tblwtl ws,wd w r i t e w s to p r og < 15: 0> 1 2 n one ulnk ulnk u n lin k f r a m e po in t e r 1 1 n o n e xor xor f f = f .x or . w r e g 1 1 n , z xor f,wre g w r e g = f . x o r . w r e g 1 1 n, z xor #lit1 0,wn w d = lit1 0 .x o r . w d 1 1 n, z xor wb,ws ,wd w d = w b .x or. w s 1 1 n, z xor wb,#l it5,wd w d = w b .x or. l i t 5 1 1 n, z ze ze ws,wn d w n d = ze ro- e xten d w s 1 1 c , z , n t able 2 6 -2: i ns truction s e t ov erv i e w (continue d) a s sem b l y mn em on ic a s sem b l y s y nt ax d esc r i pti o n # o f wo r d s # o f c ycl es s t at us fl ag s a f f ect ed
pic24fj64ga004 family ds39881d-page 228 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 229 pic24fj64 ga004 family 27 .0 el ectr i c al charac teris t ics th is s e c t io n prov id es a n o v e r vi ew of the pic 2 4fj 64g a0 04 fam i l y elec tric al c hara c te ris t ic s. ad dit i on al in form ati o n w i l l b e pr ovi d e d in fut u re rev i s i on s o f th is doc um en t as it be com e s av ai lab l e . ab so lute m a x i m u m ratin g s f o r the pic 2 4fj 64g a0 04 fam i l y are l i s t ed b e lo w . e x po su re to the s e m a x i m u m ra tin g c ond iti ons for e x te nd ed pe rio d s m a y af fect de vice re lia bil i ty . func ti ona l op erat ion of the dev ic e at t hese, o r any oth e r c ond iti ons a bove t he p a ra me ters in dica te d i n th e o pera t io n l i s t ing s of th is sp ec ifi c a t ion , i s n o t i m p lie d. absol u te maxi m u m rat i ng s (? ) am bi ent tem p e r atur e un de r bia s .. ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ..... .-4 0 c to +13 5 c s tora g e tem p e r atu r e ... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... .... .. ..... ...... ..... -6 5c to +15 0 c v o lt a ge on v dd wit h re sp ect to v ss .. ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... .. -0. 3 v to +4. 0 v v o lt a ge on a n y co mb in ed a nal og and di git a l pin an d mc lr , wi th re sp ec t to v ss ..... ..... ...... ..... .... -0. 3 v to (v dd + 0. 3v) v o lt a ge on a ny di git al onl y p i n w i th res pec t to v ss . ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... .. -0. 3 v to +6. 0 v v o lt a ge on v ddco re wit h re spe c t to v ss ..... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... .. -0. 3 v to +3. 0 v ma xi mu m c u r r e nt o u t o f v ss pi n .. ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ... 3 00 m a ma xi mu m c u r r e nt i n t o v dd pi n (no t e 1 ) .. ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ... 2 50 m a m a x i m u m ou tput cu rren t su nk by an y i / o pin..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... . ..... ..... ...... ..... 25 m a m a x i m u m ou tput cu rren t so urc e d by any i/ o p i n ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... 25 m a m a x i m u m cu rren t s unk by al l p o rt s .... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... . ..... ...... ..... ...... ... 2 00 m a m a x i m u m cu rren t s ourc e d by al l po rt s (note 1) . ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ... 2 00 m a note 1 : m a x i m u m al low a ble cu rren t is a func ti on o f d e vi ce m a xi mu m pow e r di ss ip a t io n (s ee t a ble 2 7 - 1). ?n oti c e: s t res s e s a bov e t hose li s t ed und er ?ab s o l ute m a xi mu m r a tin g s ? ma y c a u s e per ma nen t da ma ge t o th e d evi ce . t his is a s t res s rati ng onl y and fu nct i on al ope r ati on of the de vi ce at tho s e or a ny ot her co ndi tio ns ab ove th os e i ndi ca ted in th e ope rati on li sti n g s of thi s sp ec ific at ion i s not im pl ied . exp o su re to ma xi mu m rati ng c o nd iti ons f o r e x te nde d p e rio d s ma y af f e c t de vi ce reli abi li ty .
pic24fj64ga004 family ds39881d-page 230 ? 2010 microchip technology inc. 27. 1 dc c h aract eri s ti cs f i g ure 27- 1: pi c24f j6 4g a00 4 f a m i l y v o lt age - fre q uen c y grap h (indu strial) f i g ure 27- 2: pi c24f j6 4g a00 4 f a m i ly v o lt age - fre q uen cy grap h (ex t ende d te mp eratur e) fre quen c y vo l t a g e ( v ddco re ) (1 ) 3.0 0 v 2.0 0 v 32 mhz 2.7 5 v 2.5 0 v 2.2 5 v 2.75 v 16 mhz 2.35 v for freq uen ci es bet w e en 16 mh z an d 32 m h z, f max = (45.7 m h z / v ) * ( v ddc o r e ? 2v ) + 16 mh z . note 1 : w he n the vo lt a ge regu lat o r i s d i s abl ed, v dd an d v d dco re m u s t b e m a in t a i ned s o th at v d dco re ?? ? v dd ?? ? 3.6 v . pic 2 4 f j6 4g a 004 /32 g a 0 04/ 64g a 0 0 2 /3 2g a 002 fre quen c y voltage (v ddcore ) (1) 3. 0 0v 2. 0 0v 24 mhz 2.75 v 2. 5 0 v 2. 2 5v 2.75v 2.3 5 v for freq uen ci es bet w e en 16 mh z an d 24 m h z, f max = ( 22.9 m h z / v ) * (v ddc o r e ? 2v ) + 16 mh z . note 1 : w he n the vo lt a ge regu lat o r i s d i s abl ed, v dd an d v d dco re m u s t b e m a in t a i ned s o th at v d dco re ?? ? v dd ?? ? 3.6 v . p i c 24f j64 ga 0 04/ 32g a 0 0 4 /64 g a 002 /32g a 0 0 2 16 mhz
? 2010 microchip technology inc. ds39881d-page 231 pic24fj64 ga004 family t able 2 7 -1: t her m al ope rating c o nd itions rating sy mbo l min t yp m a x u nit pic 2 4fj 6 4 g a0 04 fam i l y : o pera t in g j unc ti on t e m p e r atu r e r a nge t j -4 0 ? + 140 c operat in g am bi ent t e mp erat ure r a nge t a -4 0 ? + 125 c po we r di ssi p a t i o n : int e rna l ch ip power di ss ip ati on: p in t = v dd x ( i dd ? ? i oh ) p d p int + p i / o w i/o pi n po w e r dis s i p a t io n: p i / o = ? ({v dd ? v oh } x i oh ) + ? (v ol x i ol ) ma xi mu m a l lo we d p o wer dissipa t io n p dm a x (t j ? t a )/ ? ja w t able 2 7 -2: t her m al p ackaging ch aracter istic s cha r a c te ris t ic sy m b o l t y p m a x unit note s p a ck age th er m a l r e si st a n c e , 3 0 0 mi l s o ic ? ja 49 ? c / w (n ot e 1) p a c k a g e t h e r ma l r e s i s t an ce , 6x 6x 0. 9 mm q f n ? ja 33 .7 ? c / w (n ot e 1) p a c k a g e t h e r ma l r e s i s t an ce , 8x 8x 1 m m qf n ? ja 28 ? c / w (n ot e 1) pa ck age th erm a l r e si st a nc e, 1 0x 10x 1 mm tq fp ? ja 39 .3 ? c/w (n ot e 1) note 1 : j unc ti on t o a m bi en t the r m a l re si st anc e, thet a- ja ( ? ja ) num be rs are a c h i ev ed by p a c k a g e s i m u la tio n s .
pic24fj64ga004 family ds39881d-page 232 ? 2010 microchip technology inc. t a ble 2 7 -3: dc cha racter istic s : t e m p e rature and v o lt age s p e cifica t i o n s d c ch aracteri s tics s t an dar d oper at ing c o ndi tio n s: 2.0v t o 3. 6v (un l ess oth e r w i se st ate d ) ope r a t in g t e mp er a t ur e - 40 c ? t a ? +8 5c fo r ind u s t ria l -4 0c ? t a ? +1 25c f o r ex ten ded param no . sym bol c h ar ac ter i sti c m i n t yp (1 ) ma x u nit s co nditi ons op er ating v o lt a g e dc 1 0 s u pp l y v o lt a g e v dd 2.2 ? 3.6 v r e gu lato r en abl e d v dd v ddco re ? 3 . 6 v r eg ul a t or d i s ab l ed v ddc o r e 2.0 ? 2.7 5 v r e gu l ato r di sa ble d dc 1 2 v dr ram da t a re te nt ion vo l t a g e (2 ) 1.5 ? ? v dc 1 6 v po r v dd s t ar t v ol t age to ens ure in tern al pow e r-on r e se t s i gn al ?v ss ?v dc 1 7 s vd d v dd ris e ra te to ens ure in tern al pow e r-on r e se t s i gn al 0. 05 ? ? v/ ms 0-3. 3v in 0. 1s 0-2. 5v in 60 ms no t e 1 : d a t a in ? t yp ? c o lu mn is at 3.3 v , 25 c unles s o t he rw is e s t ate d . p a ram e te rs are for d e s i gn gu ida n c e on ly and are not tes t ed . 2: t h is is th e li mi t to wh ic h v dd ca n be lo w ered wi th out lo sin g r a m da t a.
? 2010 microchip technology inc. ds39881d-page 233 pic24fj64 ga004 family t able 2 7 -4: dc ch aracter istic s : ope rating cu rren t ( i dd ) dc characteristics s t andard o p e r at i ng c o n d i t i ons: 2. 0v t o 3. 6v ( unl ess ot herw i se st at ed) o p er at i n g t e m p e r a t u r e - 40 c ? t a ? +8 5 c f or i n du st r i al -4 0 c ? t a ? +1 25 c f o r ex t e nd ed p a ra met e r no . t yp ic a l (1 ) m a x u nit s cond i t ions ope r at ing cur r e nt ( i dd ) : p m d b i t s ar e se t (2 ) d c 2 0 0 . 6 50 0 . 85 0 m a - 40 c 2. 0v (3 ) 1 m i p s d c 20 a 0. 65 0 0. 8 50 m a +25 c d c 20 b 0. 65 0 0. 8 50 m a +85 c d c 20 c 0. 65 0 0. 8 50 m a +1 25 c d c 2 0 d 1. 2 1 . 6 m a - 4 0c 3. 3v (4 ) d c 2 0e 1 . 2 1. 6 m a + 2 5 c d c 2 0f 1 . 2 1. 6 m a + 8 5 c d c 20 g 1. 2 1 . 6 m a +1 25 c d c 2 3 2 . 6 3. 4 m a - 40 c 2. 0v (3 ) 4 m i p s d c 2 3a 2 . 6 3. 4 m a + 2 5 c d c 2 3b 2 . 6 3. 4 m a + 8 5 c d c 23 c 2. 6 3 . 4 m a +1 25 c d c 2 3 d 4. 1 5 . 4 m a - 4 0c 3. 3v (4 ) d c 2 3e 4 . 1 5. 4 m a + 2 5 c d c 2 3f 4 . 1 5. 4 m a + 8 5 c d c 23 g 4. 1 5 . 4 m a +1 25 c d c 2 4 13 . 5 1 7. 6 m a - 40 c 2. 5v (3 ) 16 m i ps d c 2 4a 13 . 5 1 7. 6 m a + 2 5 c d c 2 4b 13 . 5 1 7. 6 m a + 8 5 c d c 2 4c 13 . 5 1 7. 6 m a + 12 5 c d c 2 4d 1 5 20 m a - 40 c 3. 3v (4 ) d c 2 4e 1 5 20 m a + 2 5 c d c 2 4f 1 5 20 m a + 8 5 c d c 2 4g 1 5 20 m a + 12 5 c dc3 1 1 3 1 7 ? a- 4 0 c 2. 0v (3 ) lpr c ( 3 1 k h z) d c 3 1a 1 3 17 ? a+ 2 5 c d c 3 1b 2 0 26 ? a+ 8 5 c d c 3 1c 4 0 50 ? a + 12 5 c d c 3 1d 5 4 70 ? a- 4 0 c 3. 3v (4 ) d c 3 1e 5 4 70 ? a+ 2 5 c d c 31 f 95 124 ? a+ 8 5 c d c 3 1g 12 0 2 6 0 ? a + 12 5 c note 1 : d a t a i n ? t yp i cal ? co l u m n i s at 3 . 3 v , 2 5 c u n l es s o t h e r w i se st at ed . p a r a m e t e r s a r e f o r de si gn gu i d an ce on l y an d ar e no t t e st e d . 2: the suppl y cu r r ent i s m a i n l y a f u nct i o n of t he ope r a t i ng vo l t ag e a nd f r eq uen cy . o t h e r f a ct or s, su ch as i / o pi n l o a d i ng and sw i t ch i n g r a t e, osc i l l at or t y pe , i nt er n al code e x ec ut i o n p at t e r n a nd t e m per at ur e, a l so hav e a n i m pact on t h e cur r ent cons um pt i on. the t es t co ndi t i on s f o r al l i dd m eas ur em ent s ar e as f ol l ow s : o s c i d r i v e n w i t h ex t e r na l sq uar e wa ve fro m r a il to r a i l . all i/o p i n s a r e c o n f ig u r e d a s in p u t s a n d p u ll e d to v dd . mcl r = v dd ; w d t an d fsc m ar e d i s abl ed . c p u , s r am , pr og r a m m e m o r y an d dat a m e m o r y ar e ope r a t i ona l . n o per i phe r al m odu l e s ar e o per at i n g and a l l of t he pe r i phe r al m odu l e d i s a bl e ( p m d ) b i t s ar e se t . 3: o n - c h i p v o l t age r e g u l a t o r di sa bl ed ( d i svr eg t i ed t o v dd ). 4: o n - ch i p v o l t age r e g u l a t o r ena bl ed ( d i svr e g t i ed t o v ss ) . lo w - v o l t age d e t e ct ( l v d ) a nd br ow n - o u t d e t e ct ( b o d ) a r e e nab l e d.
pic24fj64ga004 family ds39881d-page 234 ? 2010 microchip technology inc. t a ble 2 7 -5: dc cha racter istic s : idle curre nt (i idle ) dc charac teristics s t an dar d o p er at i n g c ondi t i o n s: 2. 0v t o 3. 6v ( u n l ess ot her w i se st at ed) o pe r a t i ng t e m per at ur e - 40 c ? t a ? + 8 5 c f o r i n du st r i al - 40 c ? t a ? + 1 2 5 c fo r ex te n d e d p a ra m e te r no . ty p i c a l (1 ) m a x u nit s co ndit i o n s id le c u rr e n t ( i idl e ): co r e off , cloc k o n b a s e c u r r e n t , pmd bit s a r e se t (2 ) dc4 0 1 5 0 2 0 0 ? a- 4 0 c 2. 0v (3 ) 1 m i p s d c 40 a 15 0 200 ? a+ 2 5 c d c 40 b 15 0 200 ? a+ 8 5 c d c 40 c 16 5 220 ? a + 125 c d c 40 d 25 0 325 ? a- 4 0 c 3. 3v (4 ) d c 40 e 25 0 325 ? a+ 2 5 c d c 40 f 25 0 325 ? a+ 8 5 c d c 40 g 27 5 360 ? a + 125 c dc4 3 0 .5 5 0 .7 2 m a - 4 0 c 2. 0v (3 ) 4 m i p s d c 43 a 0. 5 5 0. 72 m a +2 5c d c 43 b 0. 5 5 0. 72 m a +8 5c d c 4 3c 0 . 60 0. 8 m a + 1 2 5 c d c 4 3d 0 . 82 1. 1 m a - 40 c 3. 3v (4 ) d c 4 3e 0 . 82 1. 1 m a + 25 c d c 4 3f 0 . 82 1. 1 m a + 85 c d c 4 3g 0 . 91 1. 2 m a + 1 2 5 c dc4 7 3 4 m a - 4 0 c 2. 5v (3 ) 16 m i ps dc4 7 a 3 4 ma +2 5 c dc4 7 b 3 4 ma +8 5 c d c 4 7 c 3. 3 4 . 4 m a + 125 c d c 47 d 3. 5 4 . 6 m a - 4 0 c 3. 3v (4 ) d c 47 e 3. 5 4 . 6 m a +2 5c d c 47 f 3. 5 4 . 6 m a +8 5c d c 4 7 g 3. 9 5 . 1 m a + 125 c dc5 0 0 .8 5 1 .1 ma - 4 0 c 2. 0v (3 ) f rc ( 4 mips ) d c 5 0a 0 . 85 1. 1 m a + 25 c d c 5 0b 0 . 85 1. 1 m a + 85 c d c 5 0c 0 . 94 1. 2 m a + 1 2 5 c d c 50 d 1. 2 1 . 6 m a - 4 0 c 3. 3v (4 ) d c 50 e 1. 2 1 . 6 m a +2 5c d c 50 f 1. 2 1 . 6 m a +8 5c d c 5 0 g 1. 3 1 . 8 m a + 125 c note 1 : d a t a i n ? t yp i c al ? col u m n is a t 3 . 3v , 25 c un l e ss ot he r w i se st at e d . par a m e t e r s ar e f o r d e si g n gu i dan ce onl y and ar e no t t e st e d . 2: th e te s t co n d i ti o n s fo r a ll i idl e m e as ur em en t s a r e as f ol l ow s : o s c i d r i ve n w i t h ex t e r n al s qua r e w a ve f r om r a i l t o r a i l . al l i / o p i n s ar e co nf i g ur ed a s in pu t s a nd p u l l e d t o v dd . mc l r = v dd ; w d t and fsc m ar e di sa bl ed . c p u , s r a m , p r o gr a m m em o r y a n d da t a m e m or y ar e op er at i o na l . n o pe r i p h er al m o du l e s ar e op er at i n g an d al l o f t he p e rip h e r a l mo d u l e dis a b le (p md) b i t s a r e se t. 3: o n - c h i p v o l t age regulator di sa bl ed ( d i svr eg t i ed t o v dd ). 4: o n - c h i p v o l t age r e g u l a t o r ena bl ed ( d i svr e g t i ed t o v ss ) . lo w - v o l t age d e t e ct ( l v d ) a nd br ow n - o u t d e t e ct ( b o d ) a r e e nab l e d.
? 2010 microchip technology inc. ds39881d-page 235 pic24fj64 ga004 family dc5 1 4 6 ? a- 4 0 c 2. 0v (3 ) lprc (31 khz) dc5 1 a 4 6 ? a+ 2 5 c dc5 1 b 8 1 6 ? a+ 8 5 c d c 5 1c 2 0 50 ? a + 125 c d c 5 1d 4 2 55 ? a- 4 0 c 3. 3v (4 ) d c 5 1e 4 2 55 ? a+ 2 5 c d c 5 1f 7 0 91 ? a+ 8 5 c d c 51 g 10 0 180 ? a + 125 c t able 2 7 -5: dc ch aracter istic s : idle curre nt (i idle ) ( c o n t i nued ) dc charac teristics s t an dar d o p er at i n g c ondi t i o n s: 2. 0v t o 3. 6v ( unl ess ot her w i se st at ed) o pe r a t i ng t e m per at ur e - 40 c ? t a ? + 8 5 c f o r i n du st r i al - 40 c ? t a ? + 1 2 5 c fo r ex te n d e d p a ra m e te r no . ty p i c a l (1 ) m a x u nit s co ndit i o n s id le c u rr e n t ( i idl e ): co r e off , cloc k o n ba s e c u r r e n t , pmd bit s a r e se t (2 ) note 1 : d a t a i n ? t yp i c al ? col u m n is a t 3 . 3v , 25 c un l e ss ot he r w i se st at e d . par a m e t e r s ar e f o r d e si g n gu i dan ce onl y and ar e no t t e st e d . 2: th e te s t co n d i ti o n s fo r a ll i idl e m eas ur em en t s a r e as f ol l ow s : o s c i d r i ve n w i t h ex t e r n al s qua r e w a ve f r om r a i l t o r a i l . al l i / o p i n s ar e co nf i g ur ed a s in pu t s a nd p u l l e d t o v dd . mc l r = v dd ; w d t and fsc m ar e di sa bl ed . c p u , s r a m , p r o gr a m m em o r y a n d da t a m e m or y ar e op er at i o na l . n o pe r i p h er al m o du l e s ar e op er at i n g an d al l o f t he p e rip h e r a l mo d u l e dis a b le (p md) b i ts are set. 3: o n - c h i p v o l t age r e g u l a t o r di sa bl ed ( d i svr eg t i ed t o v dd ). 4: o n - ch i p v o l t age r e g u l a t o r ena bl ed ( d i svr e g t i ed t o v ss ) . lo w - v o l t age d e t e ct ( l v d ) a nd br ow n - o u t d e t e ct ( b o d ) a r e e nab l e d.
pic24fj64ga004 family ds39881d-page 236 ? 2010 microchip technology inc. t a ble 2 7 -6: dc cha racter istic s : p o w e r - d o w n cur rent ( i pd ) dc charac teristics s t andar d o p er at i ng condi t i ons: 2. 0v t o 3. 6v ( u n l ess ot her w i se st at ed) o per at i ng t em p er at ur e - 4 0 c ? t a ? +8 5 c f o r i n du st r i al -4 0 c ? t a ? + 1 2 5 c fo r e xte n d e d p a r a me te r no . ty p i c a l (1 ) m a x u nit s condit i o n s powe r - down c u r r e n t ( i pd ) : pm d bit s a r e s e t , vre g s bi t i s ? 0 ? (2 ) dc6 0 0 .1 1 ? a - 40 c 2. 0v (3 ) ba se po we r- d o wn cu r r e n t (5 ) d c 60 a 0. 15 1 ? a + 25 c dc6 0 m 2 . 2 7 .4 ? a + 60 c dc6 0 b 3 . 7 1 2 ? a + 85 c d c 60 j 15 50 ? a + 12 5c dc6 0 c 0 . 2 1 ? a - 40 c 2. 5v (3 ) d c 60 d 0. 25 1 ? a + 25 c dc6 0 n 2 . 6 1 5 ? a + 60 c dc6 0 e 4 . 2 2 5 ? a + 85 c d c 60 k 16 10 0 ? a + 12 5c dc6 0 f 3 . 3 9 ? a - 40 c 3. 3v (4 ) dc6 0 g 3 . 5 1 0 ? a + 25 c dc6 0 o 6 . 7 2 2 ? a + 60 c dc6 0 h 9 3 0 ? a + 85 c d c 60 l 36 12 0 ? a + 12 5c dc6 1 1 .7 5 3 ? a - 40 c 2. 0v (3 ) w a t c hdo g t i m e r c ur r ent : ? i wd t (5 ) d c 61 a 1. 75 3 ? a + 25 c d c 61 m 1. 75 3 ? a + 60 c d c 61 b 1. 75 3 ? a + 85 c dc6 1 j 3 . 5 6 ? a + 12 5c dc6 1 c 2 . 4 4 ? a - 40 c 2. 5v (3 ) dc6 1 d 2 . 4 4 ? a + 25 c dc6 1 n 2 . 4 4 ? a + 60 c dc6 1 e 2 . 4 4 ? a + 85 c dc6 1 k 4 . 8 8 ? a + 12 5c dc6 1 f 2 . 8 5 ? a - 40 c 3. 3v (4 ) dc6 1 g 2 . 8 5 ? a + 25 c dc6 1 o 2 . 8 5 ? a + 60 c dc6 1 h 2 . 8 5 ? a + 85 c dc6 1 l 5 . 6 1 0 ? a + 12 5c note 1 : d a t a i n t he t y pi ca l c o l u m n i s at 3. 3v , 2 5 c u n l e ss ot her w i se s t a t ed. par a m e t e r s a r e f o r de si gn g u i dan ce o n l y an d ar e not t e st ed . 2: bas e i pd i s m e a su r e d w i t h a l l pe r i ph er al s an d cl oc ks sh ut dow n. a l l i / o s a r e c onf i g u r e d as i n p u t s an d pul l e d hi gh . w d t , et c. , a r e a l l sw i t ch ed o f f . 3: o n - ch i p v o l t age r e g u l a t o r di sa bl ed ( d i svr eg t i ed t o v dd ). 4: o n - ch i p v o l t age r e g u l a t o r ena bl ed ( d i svr e g t i ed t o v ss ) . lo w - v o l t age d e t e ct ( l v d ) a nd br ow n - o u t d e t e ct ( b o d ) a r e e nab l e d. 5: the ? cur r ent is t h e add i t i on al c ur r e nt con su m ed w h en t he m o dul e i s en abl e d. t hi s cu r r en t sh oul d b e add ed t o t h e ba se i pd c u rr e n t.
? 2010 microchip technology inc. ds39881d-page 237 pic24fj64 ga004 family dc6 2 8 1 6 ? a - 40 c 2. 0v (3 ) rtcc + timer1 w/32 khz crystal: ? rtcc ? i ti 32 (5) d c 62 a 12 16 ? a + 25 c d c 62 m 12 16 ? a + 60 c d c 62 b 12 16 ? a + 85 c d c 62 j 18 23 ? a + 12 5c dc6 2 c 9 1 6 ? a - 40 c 2. 5v (3 ) d c 62 d 12 16 ? a + 25 c d c 62 n 12 16 ? a + 60 c d c 62 e 12 . 5 16 ? a + 85 c d c 62 k 20 25 ? a + 12 5c d c 62 f 10 . 3 18 ? a - 40 c 3. 3v (4 ) d c 62 g 13 . 4 18 ? a + 25 c d c 62 o 14 . 0 18 ? a + 60 c d c 62 h 14 . 2 18 ? a + 85 c d c 62 l 23 28 ? a + 12 5c dc6 3 2 ? ? a- 4 0 c 2.0 v (3 ) r t cc + t i me r 1 w/ l o w-po w e r 32 k h z c r ys t a l ( s o c se l<1 : 0 > = 01 ): ? rt c c ? i ti 32 (5 ) dc6 3 a 2 ? ? a+ 2 5 c dc6 3 b 6 ? ? a+ 8 5 c dc6 3 c 2 ? ? a- 4 0 c 2.5 v (3 ) dc6 3 d 2 ? ? a+ 2 5 c dc6 3 e 7 ? ? a+ 8 5 c dc6 3 f 2 ? ? a- 4 0 c 3.3 v (4 ) dc6 3 g 3 ? ? a+ 2 5 c dc6 3 h 7 ? ? a+ 8 5 c t able 2 7 -6: dc ch aracter istic s : p o w e r- d o w n cur rent ( i pd ) (c o n t i n u ed ) dc charac teristics s t andar d o p er at i ng condi t i ons: 2. 0v t o 3. 6v ( u n l ess ot her w i se st at ed) o per at i ng t em p er at ur e - 4 0 c ? t a ? +8 5 c f o r i n du st r i al -4 0 c ? t a ? + 1 2 5 c fo r e xte n d e d p a r a me te r no . ty p i c a l (1 ) m a x u nit s condit i o n s powe r - down c u r r e n t ( i pd ) : pm d bit s a r e s e t , vre g s bi t i s ? 0 ? (2 ) note 1 : d a t a i n t he t y pi ca l c o l u m n i s at 3. 3v , 2 5 c u n l e ss ot her w i se s t a t ed. par a m e t e r s a r e f o r de si gn g u i dan ce o n l y an d ar e not t e st ed . 2: bas e i pd i s m e a su r e d w i t h a l l pe r i ph er al s an d cl oc ks sh ut dow n. a l l i / o s a r e c onf i g u r e d as i n p u t s an d pul l e d hi gh . w d t , et c. , a r e a l l sw i t ch ed o f f . 3: o n - ch i p v o l t age r e g u l a t o r di sa bl ed ( d i svr eg t i ed t o v dd ). 4: o n - ch i p v o l t age r e g u l a t o r ena bl ed ( d i svr e g t i ed t o v ss ) . lo w - v o l t age d e t e ct ( l v d ) a nd br ow n - o u t d e t e ct ( b o d ) a r e e nab l e d. 5: the ? cur r ent is t h e add i t i on al c ur r e nt con su m ed w h en t he m o dul e i s en abl e d. t hi s cu r r en t sh oul d b e add ed t o t h e ba se i pd c u rr e n t.
pic24fj64ga004 family ds39881d-page 238 ? 2010 microchip technology inc. t a ble 2 7 -7: dc cha racter istic s : i/o p i n in put s p e c ifications dc characteristi cs st and a r d o p er atin g c ondi tio n s: 2.0v to 3. 6v ( unl ess ot her w ise st ated ) o p e r a t i n g t e mp er a t ur e - 40 c ? t a ? +8 5c fo r ind u s t ria l -4 0 c ? t a ? + 125 c f o r e xt end ed para m no . sym c h a r act eristi c m in t y p (1 ) ma x u nit s condit i ons v il in put lo w v o l t age (4 ) di1 0 i/o pi ns v ss ? 0 .2 v dd v di1 1 pm p pin s v ss ?0 . 1 5 v dd vp m p t t l = 1 di1 5 mcl r v ss ? 0 .2 v dd v di1 6 osci (xt m o d e ) v ss ? 0 .2 v dd v di1 7 osci (hs mo d e ) v ss ? 0 .2 v dd v di1 8 i/o pi ns with i 2 c? bu f f e r v ss ? 0 .3 v dd v s m b us d i sa bl e d di1 9 i/o pi ns with sm bus bu f f e r v ss ? 0 .8 v smbus enabled v ih input hig h v o lt a g e (4 ) di2 0 i/o pi ns : w i th anal og fun c ti ons d i gi t al o nly 0.8 v dd 0.8 v dd ? ? v dd 5. 5 v v di2 1 pm p pin s : w i th anal og fun c ti ons d i gi t al o nly 0 . 25 v dd + 0 . 8 0 . 25 v dd + 0 . 8 ? ? v dd 5. 5 v v pm pt tl = 1 di2 5 mcl r 0.8 v dd ?v dd v d i 2 6 o s c i (xt mo de) 0.7 v dd ?v dd v di2 7 osci (hs mo d e ) 0 .7 v dd ?v dd v di2 8 i/o pi ns with i 2 c bu f f e r : w i th anal og fun c ti ons d i g i ta l o n l y 0.7 v dd 0.7 v dd ? ? v dd 5. 5 v v di2 9 i/o pi ns with sm bus bu f f e r : w i th anal og fun c ti ons d i g i ta l o n l y 2.1 2.1 ? ? v dd 5. 5 v v2 . 5 v ? v pi n ? v dd di3 0 i cn p u cnx x pull- up curre n t 50 25 0 4 00 ? av dd = 3.3 v , v pi n = v ss i il in pu t le ak ag e c u r r e n t (2 , 3 ) di5 0 i/o po rt s ? ? + 1 ? av ss ? v pi n ? v dd , pin at h i gh -im p e dan ce d i 51 a na l og i np u t p i ns ? ? + 1 ? av ss ? v pi n ? v dd , pin at h i gh -im p e dan ce di5 5 mcl r ??+ 1 ? av ss ?? v pin ?? v dd di56 osci ? ? + 1 ? av ss ?? v pi n ?? v dd , xt a nd h s mo des note 1 : d a t a i n ?t yp? co lum n is at 3 . 3v , 2 5 c u n le ss ot herw i se st ated . pa ram e ter s a r e fo r de si gn gui d an ce onl y a nd a r e n o t t e s t ed. 2: th e l eak ag e c u rre nt o n the mclr p i n is stro ngl y dep end ent on the app li ed v ol t ag e l ev el. the sp ec ifie d l eve ls rep r es ent nor mal op era t ing c ond iti ons . h i g he r lea k a ge cu rrent ma y b e m ea s u r ed a t d i f f eren t in pu t v o lt age s. 3: n eg ati ve cu rren t is defined as current sourced b y the pin . 4: ref e r to t abl e 1 -2 fo r i/o pi n b u f f er t y pe s.
? 2010 microchip technology inc. ds39881d-page 239 pic24fj64 ga004 family t able 2 7 -8: dc ch aracter istic s : i/o p i n outp ut s p e cific atio n s d c c haract eristics s t andard o p erat i ng c o ndi t i ons: 2. 0v to 3. 6v ( unl ess ot herw i se st at ed) o p er at i n g t e m p e r a t u r e - 40 c ? t a ? +8 5c f or i n dus t r i al -4 0 c ? t a ? +1 25 c f o r ex t e nd ed par a m no. sy m c h a r act er i s t i c m i n t y p (1 ) m a x u nit s cond i t ions v ol ou t p u t lo w v o l t a g e d o 10 al l i / o pi ns ? ? 0 . 4 v i ol = 8 . 5 ma, v dd = 3. 6 v ?? 0 . 4 v i ol = 5. 0 m a , v dd = 2. 0 v d o 16 al l i / o pi ns ? ? 0 . 4 v i ol = 8 . 0 ma, v dd = 3. 6 v , 125 c ?? 0 . 4 v i ol = 4 . 5 ma, v dd = 2. 0 v , 125 c v oh ou t p u t high v o lt a g e d o 20 al l i / o pi ns 3 ? ? v i oh = - 3 .0 ma, v dd = 3. 6 v 1. 65 ? ? v i oh = - 1 .0 ma, v dd = 2. 0v d o 26 al l i / o pi ns 3 ? ? v i oh = - 2 .5 ma, v dd = 3. 6 v , 125 c 1. 65 ? ? v i oh = - 0 .5 ma, v dd = 2. 0 v , 125 c no t e 1 : d at a i n ? t yp? col um n is a t 2 5c un l ess o t her w i se s t a t e d. par am e t e r s a r e f or des i gn gu i dan ce o nl y and ar e not t e st ed. t able 2 7 -9: dc c h aracter istic s : p r o g ra m me mory d c c haract eristics s t andard o p er at i ng c o n d i t i ons: 2. 0v to 3. 6v ( unl ess ot herw i se st at ed) o pe r a t i ng t e m p er at ur e - 40 c ? t a ? + 85 c f o r i ndu st r i a l -4 0 c ? t a ? + 125 c f o r e xt end ed par a m no. sym c h a r act er i s t i c m i n t y p (1 ) m a x u nit s co ndit ion s pr ogr am flash m e m or y d 130 e p c e l l e ndu r a nc e 1 00 00 ? ? e/ w - 40 ? c t o +1 2 5 ? c d 131 v pr v dd fo r re a d v min ?3 . 6 v v min = m i ni m um op er at i ng vo l t a ge d 132 b v pew v ddcore fo r s e lf - t i m e d wr i t e 2. 25 ? 2. 75 v d 133 a t iw se lf- t ime d w r ite cy c l e ti m e ?3 ? m s d 134 t ret d c ha r a ct er i s t i c r e t ent i on 20 ? ? y ear p r ov i ded n o ot he r sp ec i f i ca t i on s ar e v i o l at ed d 135 i dd p sup p l y c u r r ent du r i ng pr ogr am m i ng ?7 ? m a no t e 1 : d a t a in ? t yp? col u m n is a t 3 . 3 v , 25 c unl es s ot he r w i s e st at ed .
pic24fj64ga004 family ds39881d-page 240 ? 2010 microchip technology inc. t a ble 2 7 -10: inte rnal v o lt ag e re gulator s p ecific ations ope r a t ing con d it ions : - 40 c < t a < + 1 25 c ( u nl es s ot he r w i se s t at ed ) par a m no. s y mb o l c h ar ac t e ri st i c s m i n t y p m a x u ni t s c o mme n t s v rgout re g u la to r ou tp u t v o l t a g e ? 2 . 5 ? v v bg ba nd g a p r e f e r enc e v o l t a g e ? 1. 23 ? v c efc ex t e r n al f i l t er c a p a ci t o r v a l u e 4 . 7 1 0 ? ? f s e r i e s re si st an ce < 3 o h m r e co m m end ed; < 5 o h m r equ i r e d . t vreg v ol t a ge r e gu l a t o r s t ar t - up ti m e ?1 0? ? s p o r , bo r or when vregs = 1 ?2 5? ? sv r e g s = 0 , w u t sel<1 :0> = 01 (1 ) ? 190 ? ? sv r e g s = 0 , w u t sel<1 :0> = 11 (2 ) t pw rt ? 6 4 ? m s disvreg = v dd note 1 : a v a ila ble on ly in dev ic es wi th a m a j o r s i l i c on r e vi si on lev e l of b or l a te r (d evr ev re gis t er val u e is 30 42h or g r ea t e r) . 2: w u t sel c o nfig ura t io n bi t s se ttin g i s a ppl ic abl e o nly i n de vi ce s w i th a ma jo r si lic on rev i s i o n le ve l o f b o r l a ter . th is sp ec ific at ion al so app lie s to a ll devic es prio r to rev i s i on le ve l b w h ene ve r vr eg s = 0 .
? 2010 microchip technology inc. ds39881d-page 241 pic24fj64 ga004 family 27. 2 ac c h aract eri s ti cs and t i m i ng par a meter s t h e in f o r m at i o n co n t a i ne d i n th i s se ct i o n d e f i ne s t h e p i c 2 4f j 6 4 g a 0 04 f a m i l y a c ch a r ac t e r i st i c s a n d t i mi ng p a ram e t e rs . t able 2 7 -1 1 : t e mp e rature and v o lt age s p e cifications ? ac figure 27-3: lo a d conditions for de vic e t i ming spe cifications t able 2 7 -12: cap ac itiv e loading r e quire m e n t s on outp ut pin s ac characteristi cs s t and a r d o p er at ing c ond i t i o n s : 2.0v t o 3.6v ( u n l es s o t he r w ise st a t ed ) o per atin g t e mp era t ure - 40c ? t a ? +85 c for indu st rial - 40c ? t a ? +12 5 c fo r ex tend ed op er at i n g vol t ag e v dd ra ng e a s de sc ri be d i n sec t io n 2 7. 1 ? d c c h ar ac te r i st ics ? . param no. sy mbol c h arac ter i sti c m i n t yp (1 ) ma x u nit s con dition s do 5 0 c os c 2 o sc o / c l ko pi n ? ? 1 5 p f i n xt and hs m ode s w h en e x te rna l c l oc k is us ed to d r iv e o s ci. do 5 6 c io al l i/o pi ns an d o s c o ? ? 50 p f ec mo de. do 5 8 c b sclx , sdax ? ? 4 0 0 p f i n i 2 c? mo d e . no t e 1 : d a t a in ? t yp ? c o lu mn is at 3.3 v , 25 c unles s o t he rw is e s t ate d . p a ram e te rs are for d e s i gn gu ida n c e on ly and are not tes t ed . v dd /2 c l r l pi n pin v ss v ss c l r l = 464 ? c l = 50 pf f or al l p i ns e x c ept os c o 15 pf f o r o s c o out put lo ad co nd i t i o n 1 ? for all pins except osco load condition 2 ? for osco
pic24fj64ga004 family ds39881d-page 242 ? 2010 microchip technology inc. figure 27-4: ex tern al clock t i ming os c i cl ko q 4 q 1 q2 q3 q4 q1 os20 os25 os3 0 os3 0 os 4 0 os41 os31 os 3 1 q1 q2 q3 q4 q2 q3 t a ble 2 7 -13: ex tern al clo ck t i ming re quire m e n t s a c ch aracteri s tics s t an dar d oper at ing c o ndit i on s: 2.0 to 3.6v (u nles s ot her w ise s t at ed) o p erati n g tem p e r atu r e - 40 c ? t a ? +8 5c fo r in dus tria l -40c ? t a ? +125c for extended para m no. sym c har a cter is tic m in t y p (1 ) ma x u ni t s co nditi ons os 1 0 f os c exte rnal cl ki freq uen cy (exte r nal c l oc ks a llo w ed onl y i n ec m o d e ) dc 4 dc 4 ? ? ? ? 32 8 24 6 mh z mh z mh z mh z ec , -40c ? t a ? +85 c ecpl l, -4 0c ? t a ? +85 c ec , -40c ? t a ? +12 5 c ecpl l, -4 0c ? t a ? +12 5 c os ci lla tor freq uen cy 3 3 10 31 3 10 ? ? ? ? ? ? 10 8 32 33 6 24 mh z mh z mh z khz mh z mh z xt xt pll, -40c ? t a ? +85 c h s , -40c ? t a ? +85 c sosc xt pll, -40c ? t a ? +12 5 c h s , -40c ? t a ? +12 5 c os 2 0 t os c t os c = 1 / f os c ? ? ? ? se e p a ram e t e r os10 fo r f os c va lue os 2 5 t cy i n st r u ct i o n cyc l e t i m e (2 ) 62 .5 ? d c n s os 3 0 t o s l , to s h exte rnal cl o c k in (o sci) h i gh or l ow t i me 0. 45 x t os c ?? n s e c os 3 1 t o s r , to s f exte rnal cl o c k in (o sci) r i se or f all t i m e ?? 2 0 n s e c o s 40 t c kr c l k o ri se t i m e (3 ) ?6 1 0 n s os 4 1 t c k f cl k o f a l l t i me (3 ) ?6 1 0 n s no t e 1 : d a t a in ? t yp ? c o lu mn is at 3.3 v , 25 c unles s o t he rw is e s t ate d . p a ram e te rs are for d e s i gn gu ida n c e on ly and are not tes t ed . 2: ins t ruc t io n cy cl e peri od (t cy ) eq ual s tw o tim es t he in put os ci ll ator ti me ba se p erio d. all s pec if ied v alu es a r e bas ed on ch arac teri za tio n da t a for t hat p a rt ic ula r os ci lla tor typ e u nde r st and ard ope rati ng co ndi tion s w i th the dev ic e e x e c u t ing c ode . ex cee di ng t hes e s pe c i f ied li mi t s ma y re su lt i n a n u ns t abl e o s c i l l ato r op era t ion and /or h i gh er th an exp e c t ed cu rrent co nsu m p t io n. al l d e vi ce s a r e te ste d to op erat e at ?mi n .? v a l ues w i th an ext e rna l c l o c k ap pli ed to th e o s c i/c l k i pi n. whe n an ex ternal cl oc k i npu t is u s ed , th e ?m ax .? c y c l e tim e lim it is ?d c ? (no cl oc k) f o r a ll d e v i c e s . 3: me asu r em en t s a r e t a k e n in ec m o d e . th e c l ko si gna l is m easure d on the o s c o pin . c l ko is low fo r the q 1 -q 2 pe riod (1/ 2 t cy ) and hi gh for the q 3 - q 4 pe riod (1/2 t cy ).
? 2010 microchip technology inc. ds39881d-page 243 pic24fj64 ga004 family t able 2 7 -14: pll clock t i mi ng s p e cifica t i o n s (v dd = 2.0 v t o 3. 6v) a c ch aracteri s tics s t a ndar d o p e r at ing c ondi tio n s: 2. 0 v t o 3. 6v (un l ess oth e r w i se st ated ) o p e r ati ng tem per atur e - 40 c ? t a ? +8 5c fo r ind u s t ria l -40 c ? t a ? +1 25c f o r ex ten ded para m no. sym c h a r act eristi c (1 ) mi n t y p (2 ) m a x u nit s condi tions os 5 0 f pl l i pll inpu t fre que nc y r ang e 3 3 ? ? 8 6 mhz mhz ecpl l, hspl l, xt pll mo d e s , - 4 0 c ? t a ? +8 5c ecpl l, hspl l, xt pll mo d e s , - 4 0 c ? t a ? +1 25c os 5 1 f sys pll ou tpu t f r e que ncy r ang e 8 8 ? ? 32 24 mhz mhz -4 0c ? t a ? + 85c -4 0c ? t a ? + 125 c os 5 2 t lo ck pll s t a r t-up t i m e (loc k t i m e ) ?? 2 m s os 5 3 d cl k clko s t abi li ty (j it ter) -2 1 2 % m eas u re d o v e r 10 0 m s p e ri od no t e 1 : t hese p a ra me ters are c hara c te riz ed but not tes t ed in ma nu fact uri ng. 2: d a t a in ? t yp ? c o lu mn is at 3.3 v , 25 c unles s o t he rw is e s t ate d . p a ram e te rs are for d e s i gn gu ida n c e on ly and are not tes t ed . t able 2 7 -15: ac ch aracter istic s : inte rnal rc accurac y ac characteristi cs s t a ndar d o per ati ng c on dition s : 2 . 0v t o 3.6 v (un l ess oth e r w i se st ate d) o p e r atin g t e m pera t ure - 40c ? t a ? +85 c for indu st rial -40c ? t a ? +12 5 c fo r ex tend ed pa ram no. ch aract eristic m i n t y p m a x uni t s c ondi tions in t e r n al f r c ac c u r a cy @ 8 mh z (1 ) f2 0 fr c -2 ? 2 % 2 5 c 3. 0v ? v dd ? 3. 6 v -5 ? 5 % - 4 0 c ? t a ?? +1 25c note 1 : fr equ ency cal i b r ate d at 25 c and 3.3 v . o s c t u n bi t s ca n be us ed to com p e n s a te for tem p era t ure drif t. t able 2 7 -16: inte rnal rc a ccuracy a c ch aracteri s tics s t a ndar d op er ati ng c o n d itions : 2 . 0v to 3.6 v (un l ess othe r w i se st ate d ) o pera t in g te mp erat ure - 4 0 c ? t a ? + 85c for i ndu stri al -4 0c ? t a ? + 125 c for exte nd ed pa ram no. chara c teris t ic m i n t yp m a x u n i t s cond ition s l p r c @ 31 kh z (1 ) f21 - 15 ? 1 5 % 2 5 c 3. 0 v ? v dd ? 3.6v -15 ? 15 % - 40 c ? t a ?? +85 c -20 ? 20 % 1 25c no t e 1 : c h an ge of lp r c freq uen cy as v dd ch ang es .
pic24fj64ga004 family ds39881d-page 244 ? 2010 microchip technology inc. figure 27-5: clko and i / o t i m i ng chara cteris tics note: refer to figure 27-3 for load conditions. i/o pin (inp ut) i/ o p i n (o u t put ) di3 5 old value new value di4 0 do31 do32 t a ble 2 7 -17: clko and i / o t i m i ng re q u irem ent s ac characteristi cs st and a r d oper ati ng c o n d it ion s : 2 . 0v to 3.6 v ( unl ess o t her w ise st at ed) o pera t in g te mp erat ure - 4 0 c ? t a ? + 85c for in du stri al -4 0c ? t a ? + 125 c for exte nd ed para m no. sym c h a r act er isti c m in t y p (1 ) m a x u nit s cond ition s do3 1 t io r p ort o u tpu t ris e t i me ? 1 0 2 5 n s do3 2 t io f p ort o u tpu t fal l t i me ? 1 0 2 5 n s di3 5 t in p in tx pi n h i g h o r lo w t i m e (o utp u t) 20 ? ? ns di4 0 t rb p cnx hi g h o r l o w t i me (in put) 2? ? t cy note 1 : d at a i n ?t yp? co lum n is at 3 . 3v , 2 5c u nle ss ot herw i se st ated .
? 2010 microchip technology inc. ds39881d-page 245 pic24fj64 ga004 family t able 2 7 -18: adc m o dule spe cifications ac characteri s ti cs s t a n d a rd o p e r atin g cond itio ns : 2 . 0v to 3.6 v (un l es s oth e r w is e st a t ed ) o p era t in g te mp era t ure - 40c ? t a ? +85 c for indu str i al - 40c ? t a ? +12 5 c fo r ext end ed pa r a m no . s y mb ol ch a r ac te r i st i c mi n . t y p m a x . u ni t s c o n d i t i on s d e vi ce su p p l y ad0 1 a v dd mod u l e v dd s u p p l y gr ea te r of v dd ? 0. 3 or 2.0 ?l e s s e r o f v dd + 0 . 3 or 3. 6 v ad0 2 a v ss mod u l e v ss sup p l y v ss ? 0 . 3 ? v ss + 0. 3 v ref e re nce in pu t s ad0 5 v re f h r e fe ren c e v o l t ag e h i g h a v ss + 1.7 ? a v dd v ad0 6 v re f l r e fe ren c e v o l t ag e lo w a v ss ?a v dd ? 1. 7 v ad0 7 v re f a b s o l u t e re fe ren c e v o ltag e av ss ? 0. 3 ? a v dd + 0 . 3 v an alo g i npu t ad1 0 v in h -v in l f u l l -s ca le in pu t s p an v re f l ?v re f h v (not e 2 ) ad1 1 v in ab so lu te in pu t v o ltag e a v ss ? 0. 3 ? a v dd + 0 . 3 v ? ad 12 v in l ab s o lut e v in l inpu t v o lt age av ss ? 0.3 av dd /2 v ad1 7 r in r e co mme nd ed i m pe da nc e of a n al og v o ltag e s o ur ce ? ? 2. 5k ? 10 -bi t a dc ac c u ra c y ad 2 0 b n r r e s ol uti o n ? 10 ? b it s ad 2 1 b i n l i n t egr al n o n l i n e a r i ty ? 1 < 2 lsb v in l = a v ss = v re f l = 0 v , av dd = v re f h = 3v ad2 2 b dnl di f f e r e n ti a l no n l i n e a ri ty ? 1 < 1 .2 5 l sb v in l = a v ss = v re f l = 0 v , av dd = v re f h = 3v ad2 3 b g er r ga i n err o r ? 1 3 l s b v in l = a v ss = v re f l = 0 v , av dd = v re f h = 3v ad2 4 b e of f of fse t err o r ? 1 2 l s b v in l = a v ss = v re f l = 0 v , av dd = v re f h = 3v a d 25 b ? mon o t o ni cit y (1 ) ? ? ? ? g u a r an te ed no te 1 : th e a dc con v e r sio n r e sul t n e v e r de cr ea se s wit h a n in cr ea se in t h e in pu t vo lta g e a n d ha s no m i s s in g co de s. 2: me asu r em en t s tak en w i t h ex te r na l v re f + an d v re f - us e d a s th e a d c v o l t ag e ref e re nc e.
pic24fj64ga004 family ds39881d-page 246 ? 2010 microchip technology inc. t a ble 2 7 -19: adc conv e r sion t i mi ng requir em ents (1) a c ch aracteri s tics s t and a rd o p e r ating condi tions : 2.0 v to 3 . 6v (u nles s o t her w ise st a t ed) o p e r ati ng tem p e r atur e - 40 c ? t a ? +8 5c fo r ind u s t ria l -4 0 c ? t a ? + 1 25 c f o r e xt e nd ed pa ram no. sy mbol ch arac teristi c m i n. t y p m a x . u nit s conditi ons clo c k pa ra m e te rs ad50 t ad ad c cl oc k perio d 75 ? ? ns t cy = 7 5 ns , ad 1c o n 3 in de fau l t s t at e ad51 t rc adc in te rn a l rc os ci l l a t o r perio d ? 250 ? ns co nvers i on r a te ad55 t con v c onv ers i o n t i m e ? 1 2 ? t ad ad56 f cn v thro ugh put ra te ? ? 50 0 k s p s av dd ? 2. 7v ad57 t samp s a mp l e t i me ? 1 ? t ad clo c k pa ra m e te rs ad61 t ps s sam p le s t art d e la y fr om se ttin g sam p le bi t (sam p) 2? 3 t ad no t e 1 : beca us e the s am pl e c ap s wi l l e v e ntu all y l os e c har ge, cl ock ra tes be low 1 0 k h z c an af fec t l i ne arit y perfo rm anc e, e s p e c i al ly at ele v a t ed temp e r atur es.
? 2010 microchip technology inc. ds39881d-page 247 pic24fj64 ga004 family 2 8 .0 p a ckaging i n formatio n 28. 1 p acka ge mark ing inf o rmat ion leg e nd: xx... x c us tom e r-s pe ci fic in form ati o n y y ea r co de (las t d i gi t o f ca le nda r ye ar) yy y e a r co de (las t 2 di git s o f c a le nda r y ear) ww w eek c ode (w ee k o f j anu ary 1 i s w e ek ?01 ? ) n n n a lp han um eri c tr ace ab ili ty cod e pb-f ree jed e c d e si gn ator for m a t t e t i n (sn ) * th is p a c k age is pb-f ree. the pb-fre e j e d e c de si gna tor ( ) c an b e fo un d on th e ou ter p a c k a g in g f o r th is p a c k age . no t e : i n th e ev ent th e ful l mi cro c h i p p a r t num be r can no t b e ma rke d on o ne li ne, i t w ill be c a rri ed ov er to th e nex t lin e, th us li mi tin g the n u m ber of a v ai la ble ch arac te rs fo r c u s t om er-s pec if ic inf o rm atio n. 3 e 28-l ead so ic ( . 3 00? ) xxx xxxxxxxxxxxxxxxxx xxx xxxxxxxxxxxxxxxxx xxx xxxxxxxxxxxxxxxxx yywwnnn example pic24fj16ga002/so 0810017 28-lead qfn xxx xxx xx xxx xxx xx y y wwnn n example 24 fj48 ga 00 2/ ml 0810017 3 e 3 e 28 - l ead sp dip xxxxxxxxxxxxxxxxx xxxxxxxxx xxxxxxxx yyww n n n ex am p l e -i/sp pic 2 4fj 16g a0 02 08 100 17 3 e 28-lead ssop xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example 2 4 f j 16g a0 02 /ss 0810017 3 e
pic24fj64ga004 family ds39881d-page 248 ? 2010 microchip technology inc. xxxxxxxxxx 44 - l ead qf n xxxxxxxxxx xxxxxxxxxx yywwnnn 24fj32ga ex am p l e 00 4- i/m l 0810017 4 4- lea d t q f p xx xx xx x xx x xx xx xx x xx x xx xx xx x xx x yy ww n n n ex am ple 24f j 32g a 004 - i /pt 0 8 1 00 17 3 e 3 e
? 2010 microchip technology inc. ds39881d-page 249 pic24fj64 ga004 family 28. 2 p acka ge det a i l s th e f o ll ow in g s e c t io ns giv e t he tec hni ca l de t a i l s of the p a c k age s.

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pic24fj64ga004 family ds39881d-page 258 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 259 pic24fj64 ga004 family ap pe ndix a: re vis i o n h i s t or y revi sio n a (march 2007) o r ig ina l da t a sh eet fo r th e pic 2 4 f j6 4g a00 4 fam ily of d e vi ce s. revi sio n b (march 2007) c h ang es to t a b l e 26-8 ; p a c k a g i ng di agra m s up dat ed. revi sio n c (janua ry 2 0 0 8 ) ? u pd ate of ele c tr ica l s p e c i f ic ati ons to inc l u de d c c har act e ris t i c s for exte nde d t e m p e r atur e d e vi ce s. ? u pd ate for a/d c onv erte r c hap ter t o i n cl ude i n for m a t ion on in tern al b and ga p v o l t ag e re fere nc e . ? a d ded ? appe ndix b: ?additio n al g u idan ce f o r pic2 4 f j 6 4 g a0 0 4 f a m i l y app lic a t ions ? . ? g e n e r a l r e vi si on s t o in co r p or a t e c o r r e ct i o n s i n cl ud ed i n d o c u m ent erra t a to da te (d s8 03 33). revi sio n d (janua ry 2010) ? u pd ate of el ec tric al s pe c i f ic ati ons to in cl ude 60c s pec if ic atio ns for pow e r-dow n cu rren t to d c c har act eris t i c s . ? r em ov es re feren c e s t o j t ag p r og ram m i ng th rou gho ut th e d o c u m ent . ? o the r m i no r ty pog rap h ic c o rrec t i ons thr oug hou t.
pic24fj64ga004 family ds39881d-page 260 ? 2010 microchip technology inc. ap pe ndix b : additional guidance fo r pi c2 4 f j6 4g a0 04 family ap plicat i o ns b. 1 a ddi ti onal meth ods f o r power reduct i o n d e v i ce s i n t h e p i c 2 4f j 6 4 g a 0 04 f a m i l y i n cl ud e a n u m - b e r of c o re fea t ure s to si gni fic ant ly redu ce the a ppl ic a- ti on? s p o wer re qui rem ent s . fo r tru l y p o wer- s e n s i tiv e a ppl ic ati ons, it is pos si bl e to furth e r re duce th e a ppl ic ati on? s po w er dem an ds b y t ak i n g adv an t ag e of th e d e v i c e ? s re gu lato r ar chi t ec tur e . t hes e m e t hod s h e lp de cre a s e p o w e r in tw o w a ys : b y dis abl in g th e i n ter nal v o l t ag e regu la tor to el im in ate i t s po w e r co n- s u m p ti on, and by re du cin g th e v o lt age on v ddc o r e to l ow er t he dev ic e? s dyn am i c cu rren t req uir eme nt s . u s ing th es e me thod s, it is p o s s i b le to re duc e slee p c u rre nt s (i pd ) f r om 3.5 ? a t o 2 50 na (t ypi c a l v a l ues , re fer t o s pecif ica t io ns d c 60d an d d c 6 0 g i n t a b le 2 7 - 6) . f o r dy na mi c p o w er c o n s um pt i o n , t h e re duc tio n i n v dd core f r om 2.5v , prov id ed b y th e re gul ato r , to 2 . 0v c an p r ov ide a po w e r red u ct ion of a bou t 30 %. w hen u s i ng a r egu late d po w e r so urce or a b a tt ery w i th a co ns t a n t ou tpu t v o lt age , it is po ss ible t o d e cr eas e po w e r co ns um pt i o n b y di sa b l i n g t h e r e gu l a t o r . i n t h is c a s e (fi gur e b -1 ), a s i m p l e di ode ca n b e us ed to re duc e the v o lt a g e fro m 3v o r g r eat er t o t he 2v -2 .5v re qui red for v ddc o r e . thi s m e t hod is onl y a d v i s ed o n p o w e r sup p l i es , s u c h a s lit h iu m c o in ce ll s, w h ic h m a i n t a in a c ons t a n t v o l t age ov er the lif e o f th e b a tte ry . figure b-1: pow e r red uction ex am ple fo r const ant v o lt a g e su p p li es a si mi lar me tho d c a n be u s ed fo r n on-re gul ate d s ourc e s (fig ure b -2). in this ca se , it ca n be b e n e fic i a l to use a lo w q uie sc en t cur r ent e x te rna l vo lt a ge re gul a- t o r . dev i ce s su ch a s t h e mcp 1 70 0 co ns um e o n l y 1 ? a t o r eg u l a t e t o 2v or 2. 5 v , w h ic h is l o w er th a n t h e c u rre nt re qu ired to po w e r t he int e rna l v o l t ag e re gul ato r . figure b-2: pow e r red uction ex am pl e f o r non-regulate d s upp lies v dd d i svr eg v dd co re v ss pic24fj64ga 3.0v d1 coin cell 2.3v v dd dis v r e g v dd co re v ss pi c24f j64g a 3.3v ?aa ? m c p170 0 2.0v
? 2010 microchip technology inc. ds39881d-page 261 pic24fj64 ga004 family inde x a a / d co nv erter analog i nput m odel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 t r a n s fe r fu n c t i o n .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 9 addit i on al g u idance f o r f a mily a pplicat i ons . . . . . . . . . . . . . . . . . . . . . 260 as sembl e r m p a s m a s s e m b le r . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 1 8 b block diagram s 10-b i t high- speed a/ d con v ert e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 ac cess i ng pr ogram mem o ry wit h ta b l e i n s t r u c t io n s . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 4 7 a d d r e s s a b l e p m p e x a m p l e .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 7 4 ca l l s t a c k fr a m e . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 4 5 comparator operating m odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 compa r at or v o l t age ref e re nce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 cpu pr ogramm e r?s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 crc rec onfigured for p o ly nom ial . .. .. .. .. .. .. .. ... .. .. .. .. .. 188 crc s h if ter det a ils . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 187 dat a ac cess f r om p r ogram s pace addr ess g enerat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 i 2 c module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 i nput c apt ure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 legacy p m p ex ample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 o n -chip re gul at or connect i ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 ou t p u t co m p a r e ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 8 p i c2 4 f cpu co r e .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 2 6 pi c24f j64g a004 f a mily (g eneral) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pm p mas t er por t exam ples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174?176 pm p module o verview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 p s v o p e r a t io n . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 4 8 re se t sy ste m . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 5 5 rtcc . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 7 7 s h a r e d i/o p o r t str u c t u r e . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 0 5 s i m p l i fi e d uart . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 9 sp i mas t er/ f rame mas t er connec t i on . . . . . . . . . . . . . . . . . . . . . . 149 sp i mas t er/ f rame slave connec t i on . . . . . . . . . . . . . . . . . . . . . . . . 149 sp i mas t er/ s lave connec t i on (enhanc ed buf f er m ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 sp i mas t er/ s lave connec t i on (st andard mode) . . . . . . . 148 sp i slave/ f r ame mas t er connec t i on . . . . . . . . . . . . . . . . . . . . . . . . 149 sp i slave/ f r ame slav e connec t i on . . . . . . . . . . . . . . . . . . . . . . . . . . 149 sp i x m odul e (e nhanced mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 sp i x m odul e (s t andar d m ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 s y st e m c l o c k di a g r a m . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 9 5 t i m e r 1 .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 2 5 t i m e r2 and t i mer 4 (16- bit modes ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 t i m e r2/ 3 and t i m e r4/ 5 (32 - bit mo de) . . . . . . . . . . . . . . . . . . . . . . . 128 t i m e r3 and t i mer 5 (16- bit modes ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 w a t c hdog t i mer (w dt ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 c c c o mpilers m p l a b c1 8 . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 1 8 m p l a b c3 0 . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 1 8 code exam ples b a s i c clo c k swit c h i n g ex a m p l e . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 0 1 conf i gur i n g ua rt 1 i nput and o ut put fu n ctio n s ( p p s ) . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 1 0 er a si n g a pr o g r a m m e m o r y bl o c k . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 5 2 i / o p o rt read/ w r it e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 i n it iat i ng a p r ogram ming s equence . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 loading t he w r i t e buf f ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 si n g l e - w o r d f l a s h p r o g r a m m i n g . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 5 4 code prot ect i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 c o n f ig u r a tio n bi ts .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 0 7 co r e f e a t u r e s .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... . 9 cp u a l u .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 2 9 c o n t r o l re g i st e r s . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 2 8 c o r e r e g i st e r s . .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 2 7 pr ogramm e r?s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 crc crcx o r regis t er .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 190 o p erat i on in p o wer sav e m odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 us e r in t e r f a ce . .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 8 8 cust omer change not i f i cat i on s e rvice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 cu st o m e r no tif i ca tio n se r vic e . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 6 5 cust omer s upport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 d dat a m e mory a d d r e ss s p a c e . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 3 3 m e m o r y m a p . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 3 3 n e a r d a ta sp a ce . .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . 3 4 o r ganizat i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 s f r s p a c e ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. .. 3 4 s o ft w a r e sta c k . .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 4 5 de ve lo p m e n t s u p p o r t . .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 2 1 7 d e vi ce f e a tu r e s ( s u m m a r y ) .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 1 1 di sv reg pin .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 1 2 do ze m o d e .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 0 4 e elect r ical charact e rist ics a / d sp e cifi c a t io n s .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 2 4 4 ab s o l u te m a x i m u m r a t i n g s .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 2 2 9 current specif icat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233?237 i / o p i n s pecif icat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 38?239 in t e r n a l c l o ck sp e c if i ca t io n s .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 2 4 2 load condit i ons and requirement s f o r a c ch a r a c t e r i s t ic s . . . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 4 0 pr o g r a m m e m o r y sp e ci f i ca t i o n s . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 2 3 9 t hermal o perat ing condit i ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 v/ f g r aphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 volt age ra t i ngs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 volt age re gul at or spec i f icat i ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
pic24fj64ga004 family ds39881d-page 262 ? 2010 microchip technology inc. equat ions a / d clo c k c o n ve r s i o n p e r i o d . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. 1 9 8 baud rat e reload calculat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 ca lc u l a t in g t h e p w m pe r i o d . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. 1 3 6 ca lc u l a t io n f o r m a xi m u m pwm re so lu ti o n .. .. .. .. .. ... .. 1 3 6 device and spi cl oc k speed relat i ons hi p . . . . . . . . . . . . . . . 150 uart baud rat e wit h br g h = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 uart baud rat e wit h br g h = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 e r r a t a .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 8 f f l as h conf igurat i on w o rds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32, 207?210 f l as h p r ogram m e mor y and t able i n s t ruc t ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 enhanc ed i c sp o per at ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 p r o g r a m m in g al g o r i th m .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 5 2 rts p op e r a tio n . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 5 0 s i n g l e - wo r d p r o g r a m m in g . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 5 4 i i /o po r t s a n a l o g p o r t c o n f ig u r a t io n . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 6 i nput c hange no t i f i ca t i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 o pen-drain conf igura t ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 p a r a l l e l ( p io ) . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 5 peripher al pin select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 p u ll- u p s . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 6 i 2 c clo ck ra te s . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 5 3 peripher al rem apping o p t i ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 re se r v e d ad d r e s se s .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 5 3 s l a ve a d d r e ss m a s kin g . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. 1 5 3 i d le m o d e .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 0 4 i n st r u ct i o n s e t ov e r vi e w .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 2 2 3 s u m m a r y .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 2 2 1 i n s t ruc t ion-b a sed power - sav i ng m odes . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 i n t e r-i nt egr at ed circuit . see i 2 c. . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. 1 5 1 i n te r n e t ad d r e ss . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 2 6 5 i n t e rrupt s al t e r n a t e in te r r u p t ve ct o r ta b l e ( a ivt ) .. .. .. .. .. .. .. .. . . . . . . 6 1 and r e set se quence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 i m p l e m e n t e d ve ct o r s . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 3 i n te r r u p t ve ct o r t a b l e ( i vt) . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 6 1 re g i ste r s .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. . 6 4 ? 9 2 set up an d s e rvice proc edures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 t r a p ve ct o r s . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 2 v e c t o r ta b l e . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 6 2 j jt a g i n te r f a ce . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 2 1 4 m m i cr o ch i p in t e r n e t we b sit e .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 2 6 5 mp lab a s m 30 a ssem b ler, linker, libr arian . . . . . . . . . . . . . . . . . . . 218 mp lab i cd 2 i n -circuit debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 mp lab i c e 2000 h i gh- perf orm ance universal i n - c i r cu it e m u l a t o r . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 2 1 9 mp lab i n t egr at ed developm ent env i r onment s o ft wa r e ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 2 1 7 m p l a b pm 3 de vi ce p r o g r a m m e r . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. 2 1 9 m p l a b rea l i c e in - cir c u i t em u l a t o r s ys t e m .. .. .. .. .. .. ... .. 2 1 9 m p l i nk ob je ct l i n k e r / m p l ib ob je ct l i b r a r ia n . .. .. .. .. .. ... .. 2 1 8 n ne a r da t a s p a ce . .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 3 4 o os cillat o r configurat ion clo ck s w i t ch in g . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 1 0 0 seque nce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 in i t i a l c o n f ig u r a t i o n o n p o r . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . 9 6 o scillat o r m odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 o u t put c o mpare p w m m o d e .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 6 per i od and dut y cy cle calc ul at ion . . . . . . . . . . . . . . . . . . . 137 single o u t put p u l s e g enera t ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 p pac kaging d e t a il s . .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 2 4 9 m a r ki n g . .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 2 4 7 par a l l el mast er port . see pm p. . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 6 7 per i pher al en abl e bit s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 per i pher al m odul e disable (pm d ) bit s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 per i pher al pin select (pp s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 av ai lable peripher al s and pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 c o n f ig u r a t i o n c o n t r o l . .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . 1 0 9 c o n si d e r a tio n s fo r u se .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. . 1 1 0 i npu t mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 m a p p in g ex ce p t io n s .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. . 1 0 9 o ut p ut m apping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 per i pher al pr i o ri t y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 re g i ste r s . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 1 1 1 ? 1 2 4 pi cst a rt plus deve l opm ent p r ogram mer . . . . . . . . . . . . . . . . . . . . . 220 pinout des cript i o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13?18 pm p m a s t e r po r t ex a m p l e s . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . 1 7 4 ? 1 7 6 p o we r - s a v i n g fe a t u r e s .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 1 0 3 p o we r - u p re q u ir e m e n t s . .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. 2 1 3 pro duct i dent if i c at ion sys t em . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 67 pro g ram mem o ry a c ce ss us i n g ta b l e in st r u ct i o n s.. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . 4 7 ad d r e ss c o n st r u ct i o n .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. . 4 5 a d d r e ss s p a c e .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 1 f l a s h co n f i g u r a t io n w o r d s . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . 3 2 m e m o r y m a p .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 1 o r ganizat i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 pr o g r a m sp a c e v i si b i l i t y . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . 4 8 pulse - w i dt h modulat i on. se e p w m . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 3 6 r reader respons e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 regist er m aps a / d c o n ve r te r ( a dc) .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 4 1 clo ck co n t r o l . .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 4 4 cp u . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 3 5 c r c .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 4 2 du a l co m p a r a t o r .. .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 4 2 i 2 c ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 8 icn . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 3 5 i n p u t ca p t u r e . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 7 in t e r r u p t c o n tr o l l e r . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. . 3 6 nv m . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 4 4 ou t p u t c o m p a r e ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 8 p a d co n f i g u r a t io n . .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. 4 0 pa r a ll e l m a st e r / s l a ve po r t . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . 4 1 per i pher al pin select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 p m d . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 4 4
? 2010 microchip technology inc. ds39881d-page 263 pic24fj64 ga004 family p orta . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 4 0 p ortb . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 4 0 p ortc .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 4 0 real-time clock and calendar (rtcc) . . . . . . . . . . . . . . . . . . . . . 42 s p i ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 9 t i m e r s .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 7 ua rt . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 3 9 regist ers ad1ch s (a/ d i nput s e l e c t ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 a d 1 c on1 ( a / d co n t r o l 1 ) .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 3 a d 1 c on2 ( a / d co n t r o l 2 ) .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 4 a d 1 c on3 ( a / d co n t r o l 3 ) .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 9 5 ad1cs s l (a / d i nput s c an select ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 ad 1 p c f g ( a /d po r t c o n f i g u r a t i o n ) .. .. .. .. .. .. .. . . . . . . . . . . . . 1 9 7 al c f g r pt ( a l a r m c o n f i g u r a t i o n ) .. .. .. .. .. .. .. .. . . . . . . . . . . . . 1 8 1 alm i ns ec (a l a r m minut es an d sec onds value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 alm t h d y (alarm m ont h and day value) . . . . . . . . . . . . . . . . 184 alw dhr (a l a rm w eekday and hours value) . . . . . . . . . . 184 cl k d iv ( clo ck div id e r ) . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 9 9 cm c o n ( c o m p a r a t o r c o n t r o l) .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 2 corcon ( c o r e co n t r o l) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 6 5 corcon ( c p u co n t r o l) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 2 9 crccon (crc cont r o l ) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 189 crcx o r (crc x o r p o ly nomial) . . . . . . . . . . . . . . . ... .. .. .. .. .. 190 cvrc o n (com parat or v o lt age re f e r e n ce co n t r o l ) . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 6 cw1 ( f la sh co n f ig u r a t io n wo r d 1 ) .. .. .. .. .. .. .. ... .. .. .. .. .. 2 0 8 cw2 ( f la sh co n f ig u r a t io n wo r d 2 ) .. .. .. .. .. .. .. ... .. .. .. .. .. 2 1 0 de vi d ( d e v i c e id) . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 1 1 de vre v ( d e vic e re vi si o n ) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 2 1 1 i 2 cx con ( i 2 c x co n t r o l) . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 4 i 2 cx ms k (i2c x s l ave mode addre ss mas k) . . . . . . . . . . . . 158 i 2 cx s t a t ( i 2 c x st a tu s) . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 5 6 i c x c o n ( i nput capt ure x cont r o l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 i e cn ( i nt errupt e nable cont rol 0-4) . . . . . . . . . . . . . . . . . . . . . . 73?77 if sn ( i n t e r r u p t f l a g st a t u s 0 - 4 ) .. .. .. .. .. .. .. .. .. .. . . . . . . . . 6 8 ? 7 2 i n tcon1 ( i n t e r r u p t co n t r o l 1 ) ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 6 6 i n tcon2 ( i n t e r r u p t co n t r o l 2 ) ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 6 7 i p cn ( i nt errupt p r iorit y cont rol 0- 18) . . . . . . . . . . . . . . . . . . . . 78?92 mi nse c ( r t c c m i n u t e s and seco nds v a lue) . . . . . . . . . 183 mt hdy (rt cc mon t h and day v a lue) . . . . . . . . . . . . . . . . . . . . 182 nv m c on ( f la sh m e m o r y co n t r o l) .. .. .. .. .. .. .. ... .. .. .. .. .. .. 5 1 ocx c on ( o u t p u t co m p a r e x co n t r o l ) .. .. .. .. ... .. .. .. .. .. 1 3 9 os ccon (os cillat o r control) . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 97 o s ct un (f rc o sc i l l at or t une) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 pa dcf g 1 (p ad conf igurat i o n cont rol) . . . . . . . . . . . . 173, 180 p m a ddr ( p m p ad d r e ss ) . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 7 1 pm ae n (p mp e nable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 p m con ( p m p c o n t r o l) . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 6 8 pm mo de (p mp m ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 p m p s t a t ( p m p st a t u s) . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 7 2 rcf gca l (rt cc c a l ibration and c onf igurat ion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 rcon ( r e se t co n t r o l) .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 5 6 rpi nrn (pp s i nput m apping 0 - 23) . . . . . . . . . . . . . . . . . . 111?117 rpo r n (pp s o u t put m apping 0-12) . . . . . . . . . . . . . . . . 118?124 s p i x co n 1 ( s p i x co n t r o l 1 ) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 4 6 s p i x co n 2 ( s p i x co n t r o l 2 ) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 4 7 sp i x st at ( spi x st at us and cont rol) . . . . . . . . . . . . . . . . . . . . . . . 144 s r ( a l u st at u s ) . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 2 8 , 6 5 t 1 co n ( t im e r 1 co n t r o l) . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. 1 2 6 t x con ( t im e r 2 a n d tim e r 4 co n t r o l) . . . . . . . . . . . ... .. .. .. .. .. 1 3 0 t y con ( t im e r 3 a m d t i m e r 5 co n t r o l) .. .. .. .. .. ... .. .. .. .. .. 1 3 1 uxm o de (uart x m ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 u xr x r e g ( u a r tx r e c e iv e ) . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 1 6 6 uxs t a ( u art x st at us and cont rol) . . . . . . . . . . . . . . . . . . . . . . . . 164 ux tx r e g ( u a r tx t r a n sm i t) .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . 1 6 6 w k dy hr (rt cc w eek day and hour s v a lue) . . . . . . . . 183 ye ar ( r t c c ye a r va l u e ) .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 1 8 2 res e ts clo ck s o u r ce s e le ct io n . . . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 5 7 d e l a y ti m e s . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . 5 8 rcon f l a g s op e r a t i o n . . . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 5 7 s f r s t a t e s ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. .. 5 9 re vi si o n his to r y . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 2 5 9 rt cc al a r m co n f i g u r a t i o n . .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 1 8 6 ca lib r a t i o n . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 8 5 regist er m apping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 78 s ser i al peripher al i n t e rf ace. se e sp i. . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 4 1 s f r s p a c e . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. 3 4 slect i ve periphera l power cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 so f t w a r e s i m u l a to r ( m pl a b si m ) .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 2 1 8 s o ft w a r e sta c k . . ... .. .. .. .. .. .. .. .. .. ... . . .. . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. .. 4 5 t tim e r 1 . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 2 5 t i m e r2/ 3 and t i m e r4/ 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 27 t i m i ng diagra m s clko and i / o t i m i ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 43 ex te r n a l c l o ck t i m i n g .. .. .. . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . 2 4 1 u ua r t baud rat e g enerat or (brg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 60 br eak an d s ync sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 i r da support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 o p erat i on of uxc t s and uxrts c o n t r o l p i n s .. .. .. .. . 1 6 1 re c e iv in g . .. ... .. .. .. .. .. .. .. .. .. ... . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. 1 6 1 tr a n s m i tti n g .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 1 6 1 v v dd co re /v ca p p i n . .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 1 2 v o lta g e re g u l a to r ( o n - ch ip ) ...................................... .. .. .. 2 1 2 and bo r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 and po r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 st andby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 tr a cki n g m o d e .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 2 1 2 w w a tc h d o g t i m e r ( w d t ) . .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 1 3 w i n o w e d o p e r a tio n . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . 2 1 4 www ad d r e ss . . ... .. .. .. .. .. .. .. .. .. ... . . .. . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. 2 6 5 www, o n - l ine s uppor t . .. .. .. .. ... . . . . . . . . . . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 8
pic24fj64ga004 family ds39881d-page 264 ? 2010 microchip technology inc. notes :
? 2010 microchip technology inc. ds39881d-page 265 pic24fj64 ga004 family the m i crochip w e b s i te m i c r oc hip pro v i des onl in e s upp ort v i a o u r w ww s i te at w w w .m ic roc h i p .c om . thi s w e b si te i s us ed as a m ean s to m ake fi les an d i nfo rma t io n e asi ly av ai lab l e to c u s t om ers . ac ce ss ib le by us ing yo ur f a v o rit e in tern et brow se r , th e w e b si te c o n t ai ns the foll ow in g in f o rm at i o n: ? prod uct su pport ? d a t a s hee t s and erra t a , a ppl ic atio n n ote s a nd sa mpl e p r og ram s , d es i gn re so urc es, us er ? s gui de s a nd hard w are sup po r t do c u m e n t s, la t e s t s o ft w a r e r e l e as es an d a r ch iv e d so ftw ar e ? g e n e ral t e chni cal suppo rt ? f r equ ent ly ask e d q u e s ti ons (f aq), tec h n i c a l s u p port req ues t s , o n li ne dis c u s s i o n gr oup s, mi cro c hi p c o n s ul t a n t pr o g r am m e m b er l i s t i n g ? b u s i ne ss o f mi cr och i p ? prod uc t se le cto r an d o r deri ng gui des , l ate st mi croc hi p p r es s re le ase s , li st i n g o f s e m in a r s a n d even ts, l is t i n gs of m i c r oc hip s ale s o f fi ce s, dis t rib uto rs and fac t ory re pres en t a ti ve s cus tome r c hange no tification se rv i c e m i c r oc hip ? s c u s t om er not ifi c at ion s e rv ice h e lp s kee p c u s t om ers cu rrent on m i c r oc hip prod uc t s . subs cri b e r s w il l r e ce iv e e- m a i l no t if i ca t io n w h en ev e r t h e r e ar e c han ge s, upd ate s , rev i s i on s or errat a re la ted to a s pec if ied p r odu ct fa mi ly o r d ev elo pm en t t ool o f inte res t . t o re g i s t er , ac ce ss t h e mi c r oc hi p w e b s i t e a t w w w .m ic roc hi p.c om , c l i c k o n c u st ome r c h ang e no tifi ca tion an d fo llo w the reg i s t rati on ins t ru cti ons . cus tome r sup p o r t u s ers of mi cro c hi p p r od uct s c a n rec e i v e as si st a n c e th roug h s e v e ra l c han nel s: ? d is tri buto r or r epre s e n t a tiv e ? l oc al s a l e s offi ce ? f i e ld app l i c at ion eng i ne er (f ae) ? t ec hni ca l su ppo rt ? d ev el opm en t sy ste m s in form ati on lin e c us t o m er s sh oul d con t ac t the i r dis t rib uto r , re pres en t a ti ve o r fi el d app lic ati o n en gi nee r (f ae) f o r s upp ort. loc al sa les of fic es are als o a v a ila bl e to hel p c u s t om ers . a lis tin g of s a l e s o f fi ce s an d lo ca tion s i s i n cl ud ed i n th e b a c k o f th is doc um en t. t e c hnic a l s uppo r t is a vail a ble throug h the w e b si te at : http:/ /sup port.m i croc hip.c o m
pic24fj64ga004 family ds39881d-page 266 ? 2010 microchip technology inc. re ade r res p o n s e it is ou r in ten t io n to pro v i de you w i t h th e b es t do cu me nt a t ion po ss ib le to e ns ure suc c es s fu l u s e of y ou r m i c r oc hip pro d- u c t. if yo u w i sh to prov id e y ou r c om m en t s on org ani za tio n, c l a r ity , su bj ect m atte r , a nd w ays i n w h ic h o ur d oc um ent a t io n c an bet ter s e rv e y o u , pl ease f ax y our co mm ent s t o th e t e c hni ca l pu bli c a t io ns ma nag er a t (48 0 ) 7 92-4 1 5 0 . pl eas e l i s t th e fo llo w i ng in form ati o n , an d u s e this o u tli n e to p r ov id e us wi t h y our co mm ent s a b o u t th is do cum e n t . to : t e c hni ca l pu bli c a t io ns ma nag er r e : r e ade r r es pon se t o t a l pag e s sent __ ___ ___ from : na m e c o mp any ad dres s ci ty / s t ate / zi p / cou n try t e l eph one : (__ ___ __ ) __ ___ ___ _ - _ ___ __ ___ appl ic ati on (o pti ona l): w o uld yo u l i k e a repl y? y n devi ce : lite ratu re nu mb er: qu es tion s: f ax: (__ ___ _) _ ___ __ ___ - __ ___ __ __ ds39881d pi c 2 4fj64ga004 family 1. what ar e t h e be st f e at u r es of t h i s d o c u me nt ? 2 . h o w d oes th is doc um en t m eet yo ur h a rdw a re a nd s o f t w a re devel opm en t ne eds? 3 . do y o u fin d th e o r gan iz ati on of th is do cum e n t e a sy to fol l ow? if n o t, why ? 4 . wh at addi tio n s to t he do c u m ent do yo u think wo u l d enh anc e the stru ctu r e a nd su bje c t? 5 . wh at de le tio n s from th e docu me nt c o u l d be m a d e wi tho u t a f fe cti ng the ov eral l u s e f ul nes s? 6 . is the r e a n y inc o rre ct or m i s l e adi ng info rm atio n (w h a t a nd w here ) ? 7 . h ow wo uld yo u i m p r ov e th is doc um en t?
? 2010 microchip technology inc. ds39881d-page 267 pic24fj64 ga004 family p r o d u c t i d e n t i fic a ti on sy stem to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . a r chi t e c tur e 2 4 = 1 6 - bi t mo di fi ed h a r v ar d w i t h o u t d s p f l as h m e mo ry fa mi l y f j = f l a s h p ro g ra m mem o r y p r odu ct g r ou p g a 0 = g e ner al p u rp ose mi cr oco n tr ol l e r s p i n c o un t 02 = 2 8- p i n 04 = 4 4- p i n t emp er atu r e r ang e e = -4 0 ? c to + 125 ? c ( e x t en ded ) i= - 4 0 ? c to +8 5 ? c ( i n d u str ia l) p a ck a g e sp = spdi p so = so i c ss = sso p ml = q fn pt = t q f p p a tter n t h r ee- di g i t qt p , s q tp , c o d e o r s p eci a l r equ i r em en t s ( b l a n k ot her w i se) e s = e ng i n ee ri ng s am pl e exam p l es: a) p i c 2 4 f j3 2ga 0 02 - i /m l: g en e r a l pu r po s e p i c 2 4f , 32 - k by t e pr og r am me mo ry , 2 8 -p i n , i ndu s t r i a l te mp. , qfn packa ge. b ) pi c2 4 f j6 4 g a0 0 4 - e/ pt : g en e r a l pu r po se p i c 2 4f , 64 - k by t e pr og r am me mo ry , 4 4 -p i n , e xt end ed tem p ., tq fp pack age . mi cro c h i p t r ad emark arch i t ec tu re f l ash m e mo ry f a mi l y p r o g r am m e mo ry s i z e (k b) p r odu c t gr ou p p i n c oun t temperature range pack ag e pat t er n pi c 24 fj 64 ga0 04 t - i / pt - xxx tape and reel fl ag (i f ap p l i cab l e )
ds39881d-page 268 ? 2010 microchip technology inc. ame r icas co rp o r ate o ffi ce 2355 w e s t chandler b l vd. chandler , a z 85224-6199 t e l: 4 80-792-7200 f a x: 48 0-792-7277 t e chn i c a l su pport : ht t p : / / s upport . m i crochip. com w e b a ddress : www .mic roc h ip.c om atlan t a dulut h , ga t e l: 678-957- 9614 f a x: 678-957- 1455 bo sto n w e st bor ough, ma t e l: 774-760- 0087 f a x: 774-760- 0088 ch i cag o ita sc a , il t e l: 630-285- 0071 f a x: 630-285- 0075 cl eve l a n d i ndepe ndence, o h t e l: 216-447- 0464 f a x: 216-447- 0643 dal l as addison , t x t e l: 972-818- 7423 f a x: 972-818- 2924 detro i t f a rmington hills , m i t e l: 248-538- 2250 f a x: 248-538- 2260 ko kom o k o k o m o , in t e l: 765-864- 8360 f a x: 765-864- 8387 lo s a n ge l e s miss i o n v i ejo, ca t e l: 949-462- 9523 f a x: 949-462- 9608 san t a cl ar a sant a c l ar a, ca t e l: 408-961- 6444 f a x: 408-961- 6445 t o r ont o miss i s sauga, o n t a rio, canada t e l: 905-673- 0699 f a x: 90 5-673-6509 as ia/p acific asi a paci fi c o ffi ce s u it es 3707-14, 37t h f l oor t o wer 6, t he g a t e w a y har bour ci t y , k owloon hon g k ong t e l : 852-2401-1200 f a x: 85 2-2401-3431 au stral i a - syd n e y t e l : 61-2-9868-67 33 f a x: 61 -2-9868-6755 ch ina - bei j i n g t e l : 86-10-8528-2 100 f a x: 86 -10-8528-210 4 ch in a - ch e n g d u t e l : 86-28-8665-5 5 1 1 f a x: 86 -28-8665-788 9 c hin a - c h ongq ing t e l : 86-23-8980-9 588 f a x: 86 -23-8980-950 0 c h in a - h o ng k o ng sa r t e l : 852-2401-1200 f a x: 85 2-2401-3431 ch in a - nan j in g t e l : 86-25-8473-2 460 f a x: 86 -25-8473-247 0 c hin a - q i ng da o t e l : 86-532-8502- 7355 f a x: 86 -532-8502-72 05 ch i n a - sh an g h ai t e l : 86-21-5407-5 533 f a x: 86 -21-5407-506 6 ch i n a - sh en yan g t e l : 86-24-2334-2 829 f a x: 86 -24-2334-239 3 ch i n a - sh en zh en t e l : 86-755-8203- 2660 f a x: 86 -755-8203-17 60 c h in a - w uha n t e l : 86-27-5980-5 300 f a x: 86 -27-5980-51 18 ch i n a - xi an t e l : 86-29-8833-7 252 f a x: 86 -29-8833-725 6 ch i n a - xi amen t e l : 86-592-2388138 f a x: 86 -592-2388130 c hin a - z huha i t e l: 8 6 -7 56 -3 210 040 f a x: 86 -7 56 -32 1 0 049 as ia/p a c ific i n d i a - ban g al o r e t e l: 91-80- 3090-4444 f a x: 91-80- 3090-4123 i n d i a - new delh i t e l: 91-1 1 -4160-8631 f a x: 91-1 1 - 4160-8632 i ndi a - p un e t e l: 91-20- 2566-1512 f a x: 91-20- 2566-1513 jap an - y o ko h a ma t e l: 81-45- 471- 6 166 f a x: 81-45- 471-6122 ko rea - daeg u t e l: 82-53- 744-4301 f a x: 82-53- 744-4302 ko rea - seo u l t e l: 82-2- 554-7200 f a x: 82-2-5 58-5932 or 82-2-558 -5934 mal aysi a - ku al a l u m p u r t e l: 60-3- 6201-9857 f a x: 60-3-6 201-9859 mal aysi a - pen a n g t e l: 60-4- 227-8870 f a x: 60-4-2 27-4068 p h il ip pin e s - m a ni la t e l: 63-2- 634-9065 f a x: 63-2-6 34-9069 s i ng a por e t e l: 65-6334-8870 f a x: 65-6334- 8850 t a i w an - hsin ch u t e l: 886-3- 6578-300 f a x: 886-3- 6578-370 t a i w a n - ka ohs i ung t e l: 886-7- 536-4818 f a x: 886-7- 536-4803 t a iw a n - t a ip e i t e l: 886-2- 2500-6610 f a x: 886-2- 2508-0102 th a i l a nd - ba ngk o k t e l: 66-2- 694-1351 f a x: 66-2-6 94-1350 e urop e a u stri a - w e l s t e l: 43-7242-2244- 39 f a x: 43-7242-2244- 393 d e n m a r k - c op e nha ge n t e l: 45-4450-2828 f a x: 45-4485-2829 f r an ce - p ari s t e l: 33-1-69-53 -63-20 f a x: 33-1-69-30- 90-79 g e rman y - m u n i ch t e l: 49-89-627- 144-0 f a x: 49-89-627-14 4-44 i t al y - m i l an t e l: 39-0331-74261 1 f a x: 39-0331-466781 n e th e r l a n d s - dru n en t e l: 31-416-690399 f a x: 31-416-690340 s p a i n - ma d r i d t e l: 34-91-708- 08-90 f a x: 34-91-708-08 -91 u k - w o k i ng ha m t e l: 44-1 18-921- 5869 f a x: 44-1 18-921- 5820 w or ldwi de s ales an d s er vi ce 01 /05 / 10

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